Commit 6710cc6e authored by David Cussans's avatar David Cussans

Making a copy of IPBus into local respository

parent b5df7685
Copy of IPBus taken from
http://svn.cern.ch/guest/cactus/tags/ipbus_fw/ipbus_2_0_v1/firmware
modules = { "local" : ["./ethernet/cfg" , "ipbus_core/cfg", "slaves/cfg" ] }
# Xilinx ISE setup fragment for gig_eth_pcs_pma_v11_4
core ipbus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4.xco
core ipbus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4.xco
ghdl gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_block.vhd
ghdl gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_transceiver_A.vhd
ghdl gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.vhd
ghdl gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard_tile.vhd
# Xilinx ISE setup fragment for gig_eth_pcs_pma_v11_5
files = [
"../../ethernet/coregen/tri_mode_eth_mac_v5_4.xco",
"../../ethernet/coregen/gig_eth_pcs_pma_v11_4.xco",
"../hdl/eth_s6_1000basex.vhd",
"../hdl/emac_hostbus_decl.vhd",
"../../../../work/ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_block.vhd" ,
"../../../../work/ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_transceiver_A.vhd",
"../../../../work/ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.vhd",
"../../../../work/ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard_tile.vhd"
]
# "../../ethernet/coregen/coregen/tri_mode_eth_mac_v5_4.xco",
# "../../ethernet/coregen/coregen/gig_eth_pcs_pma_v11_4.xco",
# Xilinx ISE setup fragment for gig_eth_pcs_pma_v11_5
hdl ipbus/firmware/ethernet/hdl/eth_s6_1000basex.vhd
hdl ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
include ipbus/firmware/ethernet/cfg/file_list_gig_eth_pcs_pma_v11_4
# Xilinx ISE setup fragment for gig_eth_pcs_pma_v11_4
core ipbus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4.xco
core ipbus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4.xco
ghdl gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_block.vhd
ghdl gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_transceiver_A.vhd
ghdl gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.vhd
ghdl gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard_tile.vhd
# Xilinx ISE setup fragment for gig_eth_pcs_pma_v11_5
core ipbus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_5.xco
wcore ipbus/firmware/ethernet/coregen/gtwizard_v2_5_gbe_gtx.xco
core ipbus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_5.xco
hdl ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
hdl ipbus/firmware/ethernet/hdl/eth_7s_1000basex_new.vhd
ghdl gig_eth_pcs_pma_v11_5/example_design/gig_eth_pcs_pma_v11_5_block.vhd
hdl ipbus/firmware/ethernet/gen_hdl/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5_transceiver_kc705.vhd
ghdl gig_eth_pcs_pma_v11_5/example_design/gig_eth_pcs_pma_v11_5_sync_block.vhd
ghdl gig_eth_pcs_pma_v11_5/example_design/gig_eth_pcs_pma_v11_5_reset_sync.vhd
ghdl gtwizard_v2_5_gbe_gtx/example_design/gtwizard_v2_5_gbe_gtx_init.vhd
ghdl gtwizard_v2_5_gbe_gtx/example_design/gtwizard_v2_5_gbe_gtx_tx_startup_fsm.vhd
ghdl gtwizard_v2_5_gbe_gtx/example_design/gtwizard_v2_5_gbe_gtx_rx_startup_fsm.vhd
ghdl gtwizard_v2_5_gbe_gtx/example_design/gtwizard_v2_5_gbe_gtx_sync_block.vhd
ghdl gtwizard_v2_5_gbe_gtx.vhd
ghdl gtwizard_v2_5_gbe_gtx_gt.vhd
# Ethernet setup for minit_240_ipb
core ipbus/firmware/ethernet/coregen/v5_emac_v1_8_serdes.xco
hdl ipbus/firmware/ethernet/hdl/eth_v5_1000basex.vhd
hdl ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
hdl ipbus/firmware/ethernet/gen_hdl/v5_emac_v1_8_serdes/v5_emac_v1_8_serdes_block.vhd
hdl ipbus/firmware/ethernet/gen_hdl/v5_emac_v1_8_serdes/v5_emac_v1_8_serdes.vhd
hdl ipbus/firmware/ethernet/gen_hdl/v5_emac_v1_8_serdes/gtx_dual_1000X_ch1.vhd
hdl ipbus/firmware/ethernet/gen_hdl/v5_emac_v1_8_serdes/rocketio_wrapper_gtx.vhd
hdl ipbus/firmware/ethernet/gen_hdl/v5_emac_v1_8_serdes/rocketio_wrapper_gtx_tile.vhd
# Xilinx ISE setup fragment for gig_eth_pcs_pma_v11_5
hdl ipbus/firmware/ethernet/hdl/eth_s6_1000basex.vhd
hdl ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
include ipbus/firmware/ethernet/cfg/file_list_gig_eth_pcs_pma_v11_4
# Xilinx ISE setup fragment for gig_eth_pcs_pma_v11_5
hdl ipbus/firmware/ethernet/hdl/eth_s6_gmii.vhd
hdl ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
core ipbus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4.xco
core ipbus/firmware/ethernet/coregen/mac_fifo_axi4.xco
# Xilinx ISE setup fragment for v5_emac_v1_8
# This is the ISE 14.3 version
hdl ipbus/firmware/ethernet/hdl/eth_v5_gmii.vhd
hdl ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
hdl ipbus/firmware/ethernet/gen_hdl/v5_emac_v1_8/v5_emac_v1_8.vhd
core ipbus/firmware/ethernet/coregen/mac_fifo.xco
# Virtex-6 1000basex setup
hdl ipbus/firmware/ethernet/hdl/eth_v6_basex.vhd
core ipbus/firmware/ethernet/coregen/v6_emac_v2_3_basex.xco
hdl ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
#hdl ipbus/firmware/ethernet/gen_hdl/v6_emac_v2_3_basex/v6_emac_v2_3_basex_block.vhd
ghdl v6_emac_v2_3_basex/example_design/v6_emac_v2_3_basex_block.vhd
ghdl v6_emac_v2_3_basex/example_design/common/reset_sync.vhd
ghdl v6_emac_v2_3_basex/example_design/common/sync_block.vhd
ghdl v6_emac_v2_3_basex/example_design/physical/v6_gtxwizard_top.vhd
ghdl v6_emac_v2_3_basex/example_design/physical/v6_gtxwizard.vhd
ghdl v6_emac_v2_3_basex/example_design/physical/v6_gtxwizard_gtx.vhd
ghdl v6_emac_v2_3_basex/example_design/physical/double_reset.vhd
hdl ipbus/firmware/ethernet/hdl/eth_v6_sgmii.vhd
core ipbus/firmware/ethernet/coregen/v6_emac_v2_3_sgmii.xco
hdl ipbus/firmware/ethernet/gen_hdl/v6_emac_v2_3_sgmii/v6_emac_v2_3_sgmii_block.vhd
ghdl v6_emac_v2_3_sgmii/example_design/common/reset_sync.vhd
ghdl v6_emac_v2_3_sgmii/example_design/common/sync_block.vhd
ghdl v6_emac_v2_3_sgmii/example_design/physical/v6_gtxwizard_top.vhd
ghdl v6_emac_v2_3_sgmii/example_design/physical/v6_gtxwizard.vhd
ghdl v6_emac_v2_3_sgmii/example_design/physical/v6_gtxwizard_gtx.vhd
ghdl v6_emac_v2_3_sgmii/example_design/physical/double_reset.vhd
# Xilinx ISE setup fragment for gig_eth_pcs_pma_v11_4
# This is the ISE 14.3 version modified for a v7 '490 production part
core ipbus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4.xco
core ipbus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_5.xco
hdl ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
hdl ipbus/firmware/ethernet/hdl/eth_7s_1000basex.vhd
ghdl gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_block.vhd
hdl ipbus/firmware/ethernet/gen_hdl/gig_eth_pcs_pma_v11_4/gig_eth_pcs_pma_v11_4_transceiver.vhd
ghdl gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_reset_sync.vhd
hdl ipbus/firmware/ethernet/gen_hdl/gtwizard_v2_3_gbe/gtwizard_v2_3_gbe_init.vhd
hdl ipbus/firmware/ethernet/gen_hdl/gtwizard_v2_3_gbe/gtwizard_v2_3_gbe.vhd
hdl ipbus/firmware/ethernet/gen_hdl/gtwizard_v2_3_gbe/gtwizard_v2_3_gbe_gt.vhd
hdl ipbus/firmware/ethernet/gen_hdl/gtwizard_v2_3_gbe/gtwizard_v2_3_gbe_tx_startup_fsm.vhd
hdl ipbus/firmware/ethernet/gen_hdl/gtwizard_v2_3_gbe/gtwizard_v2_3_gbe_rx_startup_fsm.vhd
hdl ipbus/firmware/ethernet/gen_hdl/gtwizard_v2_3_gbe/gtwizard_v2_3_gbe_recclk_monitor.vhd
ghdl gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_sync_block.vhd
# Xilinx ISE setup fragment for gig_eth_pcs_pma_v11_5
# This is the ISE 14.3 version modified for a v7 '490 production part
core ipbus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_5.xco
wcore ipbus/firmware/ethernet/coregen/gtwizard_v2_5_gbe_gth.xco
core ipbus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_5.xco
hdl ipbus/firmware/ethernet/hdl/eth_7s_1000basex_gth.vhd
hdl ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
ghdl gig_eth_pcs_pma_v11_5/example_design/gig_eth_pcs_pma_v11_5_block.vhd
hdl ipbus/firmware/ethernet/gen_hdl/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5_transceiver_gth.vhd
ghdl gig_eth_pcs_pma_v11_5/example_design/gig_eth_pcs_pma_v11_5_reset_sync.vhd
ghdl gig_eth_pcs_pma_v11_5/example_design/gig_eth_pcs_pma_v11_5_sync_block.vhd
ghdl gtwizard_v2_5_gbe_gth/example_design/gtwizard_v2_5_gbe_gth_init.vhd
ghdl gtwizard_v2_5_gbe_gth/example_design/gtwizard_v2_5_gbe_gth_tx_startup_fsm.vhd
ghdl gtwizard_v2_5_gbe_gth/example_design/gtwizard_v2_5_gbe_gth_rx_startup_fsm.vhd
ghdl gtwizard_v2_5_gbe_gth/example_design/gtwizard_v2_5_gbe_gth_sync_block.vhd
ghdl gtwizard_v2_5_gbe_gth.vhd
ghdl gtwizard_v2_5_gbe_gth_gt.vhd
ghdl gtwizard_v2_5_gbe_gth/example_design/gtwizard_v2_5_gbe_gth_gtrxreset_seq.vhd
# Xilinx ISE setup fragment for v5_emac_v1_8
# This is the ISE 14.3 version
xfile add firmware/ipbus/firmware/ethernet/gen_hdl/v5_emac_v1_8_serdes/v5_emac_v1_8_serdes_block.vhd
xfile add firmware/ipbus/firmware/ethernet/gen_hdl/v5_emac_v1_8_serdes/v5_emac_v1_8_serdes.vhd
xfile add firmware/ipbus/firmware/ethernet/gen_hdl/v5_emac_v1_8_serdes/gtx_dual_1000X.vhd
xfile add firmware/ipbus/firmware/ethernet/gen_hdl/v5_emac_v1_8_serdes/rocketio_wrapper_gtx.vhd
xfile add firmware/ipbus/firmware/ethernet/gen_hdl/v5_emac_v1_8_serdes/rocketio_wrapper_gtx_tile.vhd
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="sim" num="172" delta="old" >Generating IP...
</msg>
<msg type="warning" file="sim" num="100" delta="old" >The Simulation File Type &lt;<arg fmt="%s" index="1">Behavioral</arg>&gt; is not valid for this core. Overriding with File Type &lt;<arg fmt="%s" index="2">Structural</arg>&gt;.
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">VHDL simulation file type &apos;Behavioral&apos; is not valid for this core. Overriding with simulation file type &apos;Structural&apos;.</arg>
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;gig_eth_pcs_pma_v11_4&apos; already exists in the project. Output products for this core may be overwritten.</arg>
</msg>
<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for &apos;gig_eth_pcs_pma_v11_4&apos;...</arg>
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">BlackBox generator run option &apos;-iobuf&apos; found multiple times. Only the first occurence is considered.</arg>
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">BlackBox generator run option &apos;-p&apos; found multiple times. Only the first occurence is considered.</arg>
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">VHDL simulation file type &apos;Behavioral&apos; is not valid for this core. Overriding with simulation file type &apos;Structural&apos;.</arg>
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Overwriting existing file /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4/doc/pg047-gig-eth-pcs-pma.pdf with file from view xilinx_documentation</arg>
</msg>
<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
</msg>
<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
</msg>
</messages>
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4.vhd&quot; into library work</arg>
</msg>
</messages>
INFO:sim:172 - Generating IP...
WARNING:sim:100 - The Simulation File Type <Behavioral> is not valid for this
core. Overriding with File Type <Structural>.
Applying current project options...
Finished applying current project options.
Resolving generics for 'gig_eth_pcs_pma_v11_4'...
WARNING:sim - VHDL simulation file type 'Behavioral' is not valid for this core.
Overriding with simulation file type 'Structural'.
WARNING:sim - A core named 'gig_eth_pcs_pma_v11_4' already exists in the
project. Output products for this core may be overwritten.
Applying external generics to 'gig_eth_pcs_pma_v11_4'...
Delivering associated files for 'gig_eth_pcs_pma_v11_4'...
Delivering EJava files for 'gig_eth_pcs_pma_v11_4'...
Generating implementation netlist for 'gig_eth_pcs_pma_v11_4'...
INFO:sim - Pre-processing HDL files for 'gig_eth_pcs_pma_v11_4'...
WARNING:sim - BlackBox generator run option '-iobuf' found multiple times. Only
the first occurence is considered.
WARNING:sim - BlackBox generator run option '-p' found multiple times. Only the
first occurence is considered.
Running synthesis for 'gig_eth_pcs_pma_v11_4'
Running ngcbuild...
Writing VHO instantiation template for 'gig_eth_pcs_pma_v11_4'...
WARNING:sim - VHDL simulation file type 'Behavioral' is not valid for this core.
Overriding with simulation file type 'Structural'.
Writing VHDL structural simulation model for 'gig_eth_pcs_pma_v11_4'...
WARNING:sim - Overwriting existing file
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus
/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4/doc/pg047-gig-eth-pc
s-pma.pdf with file from view xilinx_documentation
Delivered 2 files into directory
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/fi
rmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4
Generating ASY schematic symbol...
INFO:sim:949 - Finished generation of ASY schematic symbol.
Generating SYM schematic symbol for 'gig_eth_pcs_pma_v11_4'...
Generating metadata file...
Generating ISE project...
XCO file found: gig_eth_pcs_pma_v11_4.xco
XMDF file found: gig_eth_pcs_pma_v11_4_xmdf.tcl
Adding
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/fi
rmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.asy -view all -origin_type
imported
Adding
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/fi
rmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.ngc -view all -origin_type
created
Checking file
"/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/f
irmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.ngc" for project device
match ...
File
"/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/f
irmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.ngc" device information
matches project device.
Adding
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/fi
rmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.sym -view all -origin_type
imported
Adding
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/fi
rmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.vhd -view all -origin_type
created
INFO:HDLCompiler:1061 - Parsing VHDL file
"/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBu
s/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.vhd" into library
work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/fi
rmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.vho -view all -origin_type
imported
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
Please set the new top explicitly by running the "project set top" command.
To re-calculate the new top automatically, set the "Auto Implementation Top"
property to true.
Top level has been set to "/gig_eth_pcs_pma_v11_4"
Generating README file...
Generating FLIST file...
INFO:sim:948 - Finished FLIST file generation.
Moving files to output directory...
Finished moving files to output directory
Wrote CGP file for project 'gig_eth_pcs_pma_v11_4'.
##############################################################
#
# Xilinx Core Generator version 14.3
# Date: Fri Feb 1 20:38:42 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:tri_mode_eth_mac:5.4
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7vx485t
SET devicefamily = virtex7
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg1927
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Tri_Mode_Ethernet_MAC xilinx.com:ip:tri_mode_eth_mac:5.4
# END Select
# BEGIN Parameters
CSET component_name=emac_serdes_5_4
CSET enable_avb=false
CSET frame_filter=false
CSET half_duplex=false
CSET mac_speed=1000_Mbps
CSET management_interface=false
CSET number_of_table_entries=0
CSET physical_interface=Internal
CSET statistics_counters=false
CSET statistics_reset=true
CSET statistics_width=64bit
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-06-05T21:10:47Z
# END Extra information
GENERATE
# CRC: 842dc3da
##############################################################
#
# Xilinx Core Generator version 13.4
# Date: Sat Aug 4 10:37:18 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:gig_eth_pcs_pma:11.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7vx485t
SET devicefamily = virtex7
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg1927
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Ethernet_1000BASE-X_PCS/PMA_or_SGMII xilinx.com:ip:gig_eth_pcs_pma:11.2
# END Select
# BEGIN Parameters
CSET auto_negotiation=false
CSET component_name=eth_pcspma_basex_11_2
CSET management_interface=false
CSET physical_interface=Transceiver
CSET sgmii_mode=10_100_1000
CSET sgmii_phy_mode=false
CSET standard=1000BASEX
CSET timing_sim=false
CSET transceiver_tile=A
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-03-30T08:06:39Z
# END Extra information
GENERATE
# CRC: 4f9939d3
##
## Core Generator Run Script, generator for Project Navigator regen command
##
proc findRtfPath { relativePath } {
set xilenv ""
if { [info exists ::env(XILINX) ] } {
if { [info exists ::env(MYXILINX)] } {
set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
} else {
set xilenv $::env(XILINX)
}
}
foreach path [ split $xilenv $::xilinx::path_sep ] {
set fullPath [ file join $path $relativePath ]
if { [ file exists $fullPath ] } {
return $fullPath
}
}
return ""
}
source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
set result [ run_cg_regen "gig_eth_pcs_pma_v11_4" xc6slx100t-3fgg484 VHDL CURRENT ]
if { $result == 0 } {
puts "Core Generator regen command completed successfully."
} elseif { $result == 1 } {
puts "Core Generator regen command failed."
} elseif { $result == 3 || $result == 4 } {
# convert 'version check' result to real return range, bypassing any messages.
set result [ expr $result - 3 ]
} else {
puts "Core Generator regen cancelled."
}
exit $result
##
## Core Generator Run Script, generator for Project Navigator regen command
##
proc findRtfPath { relativePath } {
set xilenv ""
if { [info exists ::env(XILINX) ] } {
if { [info exists ::env(MYXILINX)] } {
set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
} else {
set xilenv $::env(XILINX)
}
}
foreach path [ split $xilenv $::xilinx::path_sep ] {
set fullPath [ file join $path $relativePath ]
if { [ file exists $fullPath ] } {
return $fullPath
}
}
return ""
}
source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
set result [ run_cg_regen "tri_mode_eth_mac_v5_4" xc6slx100t-3fgg484 VHDL CURRENT ]
if { $result == 0 } {
puts "Core Generator regen command completed successfully."
} elseif { $result == 1 } {
puts "Core Generator regen command failed."
} elseif { $result == 3 || $result == 4 } {
# convert 'version check' result to real return range, bypassing any messages.
set result [ expr $result - 3 ]
} else {
puts "Core Generator regen cancelled."
}
exit $result
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 gig_eth_pcs_pma_v11_4
RECTANGLE Normal 32 32 544 1152
LINE Normal 0 80 32 80
PIN 0 80 LEFT 36
PINATTR PinName reset
PINATTR Polarity IN
LINE Normal 0 176 32 176
PIN 0 176 LEFT 36
PINATTR PinName userclk
PINATTR Polarity IN
LINE Normal 0 208 32 208
PIN 0 208 LEFT 36
PINATTR PinName userclk2
PINATTR Polarity IN
LINE Wide 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName gmii_txd[7:0]
PINATTR Polarity IN
LINE Normal 0 304 32 304
PIN 0 304 LEFT 36
PINATTR PinName gmii_tx_en
PINATTR Polarity IN
LINE Normal 0 336 32 336
PIN 0 336 LEFT 36
PINATTR PinName gmii_tx_er
PINATTR Polarity IN
LINE Wide 0 368 32 368
PIN 0 368 LEFT 36
PINATTR PinName gmii_rxd[7:0]
PINATTR Polarity OUT
LINE Normal 0 400 32 400
PIN 0 400 LEFT 36
PINATTR PinName gmii_rx_dv
PINATTR Polarity OUT
LINE Normal 0 432 32 432
PIN 0 432 LEFT 36
PINATTR PinName gmii_rx_er
PINATTR Polarity OUT
LINE Normal 0 464 32 464
PIN 0 464 LEFT 36
PINATTR PinName gmii_isolate
PINATTR Polarity OUT
LINE Wide 0 720 32 720
PIN 0 720 LEFT 36
PINATTR PinName configuration_vector[4:0]
PINATTR Polarity IN
LINE Wide 0 784 32 784
PIN 0 784 LEFT 36
PINATTR PinName status_vector[15:0]
PINATTR Polarity OUT
LINE Normal 576 80 544 80
PIN 576 80 RIGHT 36
PINATTR PinName mgt_rx_reset
PINATTR Polarity OUT
LINE Normal 576 112 544 112
PIN 576 112 RIGHT 36
PINATTR PinName mgt_tx_reset
PINATTR Polarity OUT
LINE Normal 576 144 544 144
PIN 576 144 RIGHT 36
PINATTR PinName dcm_locked
PINATTR Polarity IN
LINE Wide 576 176 544 176
PIN 576 176 RIGHT 36
PINATTR PinName rxbufstatus[1:0]
PINATTR Polarity IN
LINE Normal 576 208 544 208
PIN 576 208 RIGHT 36
PINATTR PinName rxchariscomma
PINATTR Polarity IN
LINE Normal 576 240 544 240
PIN 576 240 RIGHT 36
PINATTR PinName rxcharisk
PINATTR Polarity IN
LINE Wide 576 272 544 272
PIN 576 272 RIGHT 36
PINATTR PinName rxclkcorcnt[2:0]
PINATTR Polarity IN
LINE Wide 576 304 544 304
PIN 576 304 RIGHT 36
PINATTR PinName rxdata[7:0]
PINATTR Polarity IN
LINE Normal 576 336 544 336
PIN 576 336 RIGHT 36
PINATTR PinName rxdisperr
PINATTR Polarity IN
LINE Normal 576 368 544 368
PIN 576 368 RIGHT 36
PINATTR PinName rxnotintable
PINATTR Polarity IN
LINE Normal 576 400 544 400
PIN 576 400 RIGHT 36
PINATTR PinName rxrundisp
PINATTR Polarity IN
LINE Normal 576 432 544 432
PIN 576 432 RIGHT 36
PINATTR PinName txbuferr
PINATTR Polarity IN
LINE Normal 576 464 544 464
PIN 576 464 RIGHT 36
PINATTR PinName powerdown
PINATTR Polarity OUT
LINE Normal 576 496 544 496
PIN 576 496 RIGHT 36
PINATTR PinName txchardispmode
PINATTR Polarity OUT
LINE Normal 576 528 544 528
PIN 576 528 RIGHT 36
PINATTR PinName txchardispval
PINATTR Polarity OUT
LINE Normal 576 560 544 560
PIN 576 560 RIGHT 36
PINATTR PinName txcharisk
PINATTR Polarity OUT
LINE Wide 576 592 544 592
PIN 576 592 RIGHT 36
PINATTR PinName txdata[7:0]
PINATTR Polarity OUT
LINE Normal 576 624 544 624
PIN 576 624 RIGHT 36
PINATTR PinName enablealign
PINATTR Polarity OUT
LINE Normal 576 976 544 976
PIN 576 976 RIGHT 36
PINATTR PinName signal_detect
PINATTR Polarity IN
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="gig_eth_pcs_pma_v11_4.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="gig_eth_pcs_pma_v11_4.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="gig_eth_pcs_pma_v11_4.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="gig_eth_pcs_pma_v11_4.vho" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1427472752" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1427472752">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1427795305" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="2565638209758617048" xil_pn:start_ts="1427795305">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1427795305" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1786354330241842045" xil_pn:start_ts="1427795305">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1427795305" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1427795305">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1427795305" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-1258706226706025702" xil_pn:start_ts="1427795305">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="gig_eth_pcs_pma_v11_4">
<symboltype>BLOCK</symboltype>
<timestamp>2015-3-23T15:7:50</timestamp>
<pin polarity="Input" x="0" y="80" name="reset" />
<pin polarity="Input" x="0" y="176" name="userclk" />
<pin polarity="Input" x="0" y="208" name="userclk2" />
<pin polarity="Input" x="0" y="272" name="gmii_txd[7:0]" />
<pin polarity="Input" x="0" y="304" name="gmii_tx_en" />
<pin polarity="Input" x="0" y="336" name="gmii_tx_er" />
<pin polarity="Output" x="0" y="368" name="gmii_rxd[7:0]" />
<pin polarity="Output" x="0" y="400" name="gmii_rx_dv" />
<pin polarity="Output" x="0" y="432" name="gmii_rx_er" />
<pin polarity="Output" x="0" y="464" name="gmii_isolate" />
<pin polarity="Input" x="0" y="720" name="configuration_vector[4:0]" />
<pin polarity="Output" x="0" y="784" name="status_vector[15:0]" />
<pin polarity="Output" x="576" y="80" name="mgt_rx_reset" />
<pin polarity="Output" x="576" y="112" name="mgt_tx_reset" />
<pin polarity="Input" x="576" y="144" name="dcm_locked" />
<pin polarity="Input" x="576" y="176" name="rxbufstatus[1:0]" />
<pin polarity="Input" x="576" y="208" name="rxchariscomma" />
<pin polarity="Input" x="576" y="240" name="rxcharisk" />
<pin polarity="Input" x="576" y="272" name="rxclkcorcnt[2:0]" />
<pin polarity="Input" x="576" y="304" name="rxdata[7:0]" />
<pin polarity="Input" x="576" y="336" name="rxdisperr" />
<pin polarity="Input" x="576" y="368" name="rxnotintable" />
<pin polarity="Input" x="576" y="400" name="rxrundisp" />
<pin polarity="Input" x="576" y="432" name="txbuferr" />
<pin polarity="Output" x="576" y="464" name="powerdown" />
<pin polarity="Output" x="576" y="496" name="txchardispmode" />
<pin polarity="Output" x="576" y="528" name="txchardispval" />
<pin polarity="Output" x="576" y="560" name="txcharisk" />
<pin polarity="Output" x="576" y="592" name="txdata[7:0]" />
<pin polarity="Output" x="576" y="624" name="enablealign" />
<pin polarity="Input" x="576" y="976" name="signal_detect" />
<graph>
<text style="fontsize:40;fontname:Arial" x="32" y="32">gig_eth_pcs_pma_v11_4</text>
<rect width="512" x="32" y="32" height="1120" />
<line x2="32" y1="80" y2="80" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin reset" />
<line x2="32" y1="176" y2="176" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="176" type="pin userclk" />
<line x2="32" y1="208" y2="208" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="208" type="pin userclk2" />
<line x2="32" y1="272" y2="272" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="272" type="pin gmii_txd[7:0]" />
<line x2="32" y1="304" y2="304" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="304" type="pin gmii_tx_en" />
<line x2="32" y1="336" y2="336" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="336" type="pin gmii_tx_er" />
<line x2="32" y1="368" y2="368" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="368" type="pin gmii_rxd[7:0]" />
<line x2="32" y1="400" y2="400" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="400" type="pin gmii_rx_dv" />
<line x2="32" y1="432" y2="432" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="432" type="pin gmii_rx_er" />
<line x2="32" y1="464" y2="464" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="464" type="pin gmii_isolate" />
<line x2="32" y1="720" y2="720" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="720" type="pin configuration_vector[4:0]" />
<line x2="32" y1="784" y2="784" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="784" type="pin status_vector[15:0]" />
<line x2="544" y1="80" y2="80" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin mgt_rx_reset" />
<line x2="544" y1="112" y2="112" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="112" type="pin mgt_tx_reset" />
<line x2="544" y1="144" y2="144" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="144" type="pin dcm_locked" />
<line x2="544" y1="176" y2="176" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="176" type="pin rxbufstatus[1:0]" />
<line x2="544" y1="208" y2="208" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="208" type="pin rxchariscomma" />
<line x2="544" y1="240" y2="240" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="240" type="pin rxcharisk" />
<line x2="544" y1="272" y2="272" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="272" type="pin rxclkcorcnt[2:0]" />
<line x2="544" y1="304" y2="304" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="304" type="pin rxdata[7:0]" />
<line x2="544" y1="336" y2="336" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="336" type="pin rxdisperr" />
<line x2="544" y1="368" y2="368" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="368" type="pin rxnotintable" />
<line x2="544" y1="400" y2="400" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="400" type="pin rxrundisp" />
<line x2="544" y1="432" y2="432" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="432" type="pin txbuferr" />
<line x2="544" y1="464" y2="464" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="464" type="pin powerdown" />
<line x2="544" y1="496" y2="496" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="496" type="pin txchardispmode" />
<line x2="544" y1="528" y2="528" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="528" type="pin txchardispval" />
<line x2="544" y1="560" y2="560" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="560" type="pin txcharisk" />
<line x2="544" y1="592" y2="592" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="592" type="pin txdata[7:0]" />
<line x2="544" y1="624" y2="624" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="624" type="pin enablealign" />
<line x2="544" y1="976" y2="976" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="976" type="pin signal_detect" />
</graph>
</symbol>
This source diff could not be displayed because it is too large. You can view the blob instead.
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Generated from core with identifier: --
-- xilinx.com:ip:gig_eth_pcs_pma:11.4 --
-- --
-- The Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE(TM) provides the --
-- functionality to implement one of two different specifications: --
-- firstly the IEEE 802.3 1000BASE-X specification; secondly the --
-- Serial-GMII (SGMII) specification which is closely based on --
-- 1000BASE-X. The core provides a choice of physical interface --
-- options: a Ten-Bit-Interface (TBI) for connection to an external --
-- SERDES; high speed serial functionality using the device specific --
-- transceivers in Virtex-7, Kintex-7, Artix-7, Virtex-4, Virtex-5, --
-- Virtex-6 and Spartan-6; SGMII standard only - LVDS using SelectIO in --
-- Virtex-6 devices -2 speed grade and faster. All options provide up --
-- to 1 gigabit per second total bandwidth. When perfoming the SGMII --
-- standard, the core can carry Ethernet traffic up to 1 gigabit per --
-- second total bandwidth; this is inclusive of 10Mbps, 100Mbps and --
-- 1Gbps Ethernet speeds. The core is designed to interface to the --
-- LogiCORE Tri-Mode Ethernet MAC from Xilinx to provide a complete --
-- solution. --
--------------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT gig_eth_pcs_pma_v11_4
PORT (
reset : IN STD_LOGIC;
signal_detect : IN STD_LOGIC;
mgt_rx_reset : OUT STD_LOGIC;
mgt_tx_reset : OUT STD_LOGIC;
userclk : IN STD_LOGIC;
userclk2 : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
rxbufstatus : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
rxchariscomma : IN STD_LOGIC;
rxcharisk : IN STD_LOGIC;
rxclkcorcnt : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
rxdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rxdisperr : IN STD_LOGIC;
rxnotintable : IN STD_LOGIC;
rxrundisp : IN STD_LOGIC;
txbuferr : IN STD_LOGIC;
powerdown : OUT STD_LOGIC;
txchardispmode : OUT STD_LOGIC;
txchardispval : OUT STD_LOGIC;
txcharisk : OUT STD_LOGIC;
txdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
enablealign : OUT STD_LOGIC;
gmii_txd : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gmii_tx_en : IN STD_LOGIC;
gmii_tx_er : IN STD_LOGIC;
gmii_rxd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gmii_rx_dv : OUT STD_LOGIC;
gmii_rx_er : OUT STD_LOGIC;
gmii_isolate : OUT STD_LOGIC;
configuration_vector : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
status_vector : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : gig_eth_pcs_pma_v11_4
PORT MAP (
reset => reset,
signal_detect => signal_detect,
mgt_rx_reset => mgt_rx_reset,
mgt_tx_reset => mgt_tx_reset,
userclk => userclk,
userclk2 => userclk2,
dcm_locked => dcm_locked,
rxbufstatus => rxbufstatus,
rxchariscomma => rxchariscomma,
rxcharisk => rxcharisk,
rxclkcorcnt => rxclkcorcnt,
rxdata => rxdata,
rxdisperr => rxdisperr,
rxnotintable => rxnotintable,
rxrundisp => rxrundisp,
txbuferr => txbuferr,
powerdown => powerdown,
txchardispmode => txchardispmode,
txchardispval => txchardispval,
txcharisk => txcharisk,
txdata => txdata,
enablealign => enablealign,
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
gmii_isolate => gmii_isolate,
configuration_vector => configuration_vector,
status_vector => status_vector
);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file gig_eth_pcs_pma_v11_4.vhd when simulating
-- the core, gig_eth_pcs_pma_v11_4. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
##############################################################
#
# Xilinx Core Generator version 14.7
# Date: Mon Mar 23 15:07:18 2015
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:gig_eth_pcs_pma:11.4
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx100t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Ethernet_1000BASE-X_PCS/PMA_or_SGMII xilinx.com:ip:gig_eth_pcs_pma:11.4
# END Select
# BEGIN Parameters
CSET auto_negotiation=false
CSET component_name=gig_eth_pcs_pma_v11_4
CSET management_interface=false
CSET physical_interface=Transceiver
CSET sgmii_mode=10_100_1000
CSET sgmii_phy_mode=false
CSET standard=1000BASEX
CSET timing_sim=false
CSET transceiver_tile=A
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-06-05T17:19:16Z
# END Extra information
GENERATE
# CRC: f804edf0
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="gig_eth_pcs_pma_v11_4.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="gig_eth_pcs_pma_v11_4.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx100t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|gig_eth_pcs_pma_v11_4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="gig_eth_pcs_pma_v11_4.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/gig_eth_pcs_pma_v11_4" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="gig_eth_pcs_pma_v11_4" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-03-23T15:07:54" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="764184409318772D6D4DE6B130630AAA" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
<HTML>
<HEAD>
<TITLE>gig_eth_pcs_pma_v11_4_vinfo</TITLE>
<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
</HEAD>
<BODY>
<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
CHANGE LOG for Xilinx LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v11.4
Release Date: July 25, 2012
--------------------------------------------------------------------------------
Table of Contents
1. INTRODUCTION
2. DEVICE SUPPORT
3. NEW FEATURE HISTORY
4. RESOLVED ISSUES
5. KNOWN ISSUES & LIMITATIONS
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY
8. LEGAL DISCLAIMER
--------------------------------------------------------------------------------
1. INTRODUCTION
This file contains the change log for all released versions of the Xilinx
LogiCORE IP core Ethernet 1000BASE-X PCS/PMA or SGMII.
For the latest core updates, see the product page at:
<A HREF="http://www.xilinx.com/products/ipcenter/DO-DI-GMIITO1GBSXPCS.htm">www.xilinx.com/products/ipcenter/DO-DI-GMIITO1GBSXPCS.htm</A>
For installation instructions for this release, please go to:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
For system requirements, see:
<A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
2. DEVICE SUPPORT
2.1. ISE
The following device families are supported by the core for this release:
Virtex-7 devices
Virtex-7
Virtex-7 HT/XT
Kintex-7 devices
Kintex-7
Artix-7 devices
Artix-7
Zynq-7000 devices
Zynq-7000
Virtex-6 devices
Virtex-6 CXT/LXT/SXT/HXT
Virtex-6 Lower Power (-1L) LXT/SXT
Defense Grade Virtex-6Q (XQ) LXT/SXT
Spartan-6 devices
Spartan-6 LX/LXT
Defense Grade Spartan-6Q LX/LXT
All Virtex-5 devices
Virtex-4 devices
Virtex-4 LX/SX/FX
Spartan-3 device families
Spartan-3
Spartan-3A and Spartan-3AN
Spartan-3A DSP
Spartan-3E
2.2. VIVADO
The following device families are supported by the core for this release:
Virtex-7 devices
Virtex-7
Virtex-7 HT/XT
Kintex-7 devices
Kintex-7
Artix-7 devices
Artix-7
Zynq-7000 devices
Zynq-7000
3. NEW FEATURE HISTORY
3.1 ISE
v11.4
- ISE 14.2 software support
- Support for Zynq Devices
v11.3
- ISE 14.1 software support
- Support for Artix7 Devices
- Support for Virtex-7 HT Devices
v11.2
- ISE 13.4 software support
- Added programability through configuration vector
v11.1
- ISE 13.1 software support
- Updated status vector
- SGMII PHY mode
- Support for Kintex7 Devices
- Support for Virtex7 Devices
3.2 Vivado
v11.4
- Vivado 2012.2 software support
- Initial public release
- Block level user editable logic delivered as part of the core
4. RESOLVED ISSUES
4.1 ISE
The following issues are resolved in the indicated IP versions:
v11.4
- None
v11.3
- AR: 45676
- AR: 46123
v11.2
- AR: 42672
- AR: 36961
- AR: 42842
- AR: 43421
- AR: 43482
v11.1
- AR: 36957
- AR: 36961
- AR: 35681
4.2 Vivado
v11.4
- None
5. KNOWN ISSUES & LIMITATIONS
- For a comprehensive listing of Known Issues for this core, please see the IP
Release Notes Guide,
<A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
6. TECHNICAL SUPPORT & FEEDBACK
To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
Questions are routed to a team with expertise using this product.
Feedback on this IP core may also be submitted under the "Leave Feedback"
menu item in Vivado/PlanAhead.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
07/25/2012 Xilinx, Inc. 11.4 ISE 14.2 and Vivado 2012.2.
Support for Zynq Devices. Sync LVDS Solution
04/24/2012 Xilinx, Inc. 11.3 ISE 14.1, Artix-7 and Vivado 2012.1 support
01/18/2012 Xilinx, Inc. 11.2 ISE 13.4 Support
09/06/2011 Xilinx, Inc. 11.1 Rev 1 Patch release for ISE 13.1
03/01/2011 Xilinx, Inc. 11.1 ISE 13.1 and Virtex-7 / Kintex-7 support
07/30/2010 Xilinx, Inc. 10.5 Rev 1 Patch release for ISE 12.2
07/23/2010 Xilinx, Inc. 10.5 ISE 12.2 support and Virtex-6 LVDS I/O
04/19/2010 Xilinx, Inc. 10.4 Release for ISE 12.1
03/09/2010 Xilinx, Inc. 10.3 Rev 1 Patch release for ISE 11.5
09/16/2009 Xilinx, Inc. 10.3 11.3, Virtex-6 HXT and Lower Power support
06/24/2009 Xilinx, Inc. 10.2 Release for ISE 11.2 and Spartan-6 support
04/27/2009 Xilinx, Inc. 10.1 Release for ISE 11.1
03/24/2008 Xilinx, Inc. 9.1 Release for ISE 10.1
08/15/2007 Xilinx, Inc. 9.0 Release for 9.2i
04/02/2007 Xilinx, Inc. 8.1 Rev 1 Spartan-3A DSP support
03/05/2007 Xilinx, Inc. 8.1 Release for ISE 9.1i
10/26/2006 Xilinx, Inc. 8.0 Release for Virtex-5 and Spartan-3A
07/19/2006 Xilinx, Inc. 7.1 Release for ISE 8.2i
05/22/2006 Xilinx, Inc. 7.0 Rev 1 Virtex-4 FX CES4 update
01/18/2006 Xilinx, Inc. 7.0 Release for ISE 8.1i
06/24/2005 Xilinx, Inc. 6.0 patch1 Patch release
05/12/2005 Xilinx, Inc. 6.0 Release for ISE 7.1i
09/30/2004 Xilinx, Inc. 5.0 Release for ISE 6.3i
================================================================================
8. LEGAL DISCLAIMER
(c) Copyright 2004 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
</FONT>
</PRE>
</BODY>
</HTML>
CONFIG PART = xc6slx45tfgg484-2;
#***********************************************************
# PCS/PMA Clock period Constraints: please do not relax *
#***********************************************************
NET "clkin" TNM_NET = "clkin";
TIMESPEC "TS_clkin" = PERIOD "clkin" 8 ns HIGH 50 %;
NET "gtpclkout" TNM_NET = "gtpclkout";
TIMESPEC "TS_gtpclkout" = PERIOD "gtpclkout" 8 ns HIGH 50 %;
#***********************************************************
# GTP placement constraints *
#***********************************************************
# GTPA1_DUAL_X0Y0 is used as an example.
INST "core_wrapper/transceiver_inst/GTP_1000X/tile0_s6_gtpwizard_i/gtpa1_dual_i" LOC = "GTPA1_DUAL_X0Y0";
# The Reference clock pins are located next to the GTP
INST "brefclk_n" LOC = "B10";
INST "brefclk_p" LOC = "A10";
#***********************************************************
# GMII constraints for the core attached to GTP 0 *
#***********************************************************
# If the GMII is intended to be an internal interface, *
# the GMII signals can be connected directly to user *
# logic and all of the following constraints in this file *
# should be removed. *
# *
# If the GMII is intended to be an external interface, *
# all of the following constraints in this file should be *
# maintained. *
#***********************************************************
#-----------------------------------------------------------
# Lock down the GMII Tx signals to the same bank for low -
# skew. This is an example placement only. -
#-----------------------------------------------------------
INST "gmii_tx_clk0" LOC = "AA12 ";
INST "gmii_tx_en0" LOC = "T15";
INST "gmii_tx_er0" LOC = "T11";
INST "gmii_txd0<0>" LOC = "AB13";
INST "gmii_txd0<1>" LOC = "T12";
INST "gmii_txd0<2>" LOC = "U12";
INST "gmii_txd0<3>" LOC = "W14";
INST "gmii_txd0<4>" LOC = "Y14";
INST "gmii_txd0<5>" LOC = Y15"";
INST "gmii_txd0<6>" LOC = "U15";
INST "gmii_txd0<7>" LOC = "R11";
#-----------------------------------------------------------
# To Adjust GMII Tx Input Setup/Hold Timing -
#-----------------------------------------------------------
INST "delay_gmii_tx_en0" IDELAY_VALUE = 5;
INST "delay_gmii_tx_er0" IDELAY_VALUE = 5;
INST "gmii_data_bus0*7*.delay_gmii_txd0" IDELAY_VALUE = 5;
INST "gmii_data_bus0*6*.delay_gmii_txd0" IDELAY_VALUE = 5;
INST "gmii_data_bus0*5*.delay_gmii_txd0" IDELAY_VALUE = 5;
INST "gmii_data_bus0*4*.delay_gmii_txd0" IDELAY_VALUE = 5;
INST "gmii_data_bus0*3*.delay_gmii_txd0" IDELAY_VALUE = 5;
INST "gmii_data_bus0*2*.delay_gmii_txd0" IDELAY_VALUE = 5;
INST "gmii_data_bus0*1*.delay_gmii_txd0" IDELAY_VALUE = 5;
INST "gmii_data_bus0*0*.delay_gmii_txd0" IDELAY_VALUE = 5;
#-----------------------------------------------------------
# To check (analyze) GMII Tx Input Setup/Hold Timing -
#-----------------------------------------------------------
INST "gmii_txd0*" TNM = IN_GMII0;
INST "gmii_tx_en0" TNM = IN_GMII0;
INST "gmii_tx_er0" TNM = IN_GMII0;
TIMEGRP "IN_GMII0" OFFSET = IN 2.5 ns VALID 3 ns BEFORE "gmii_tx_clk0";
#-----------------------------------------------------------
# GMII IOSTANDARD Constraints: please select an I/O -
# Standard (LVTTL is suggested). -
#-----------------------------------------------------------
INST "gmii_txd0<?>" IOSTANDARD = LVTTL;
INST "gmii_tx_en0" IOSTANDARD = LVTTL;
INST "gmii_tx_er0" IOSTANDARD = LVTTL;
INST "gmii_rxd0<?>" IOSTANDARD = LVTTL;
INST "gmii_rx_dv0" IOSTANDARD = LVTTL;
INST "gmii_rx_er0" IOSTANDARD = LVTTL;
INST "gmii_tx_clk0" IOSTANDARD = LVTTL;
INST "gmii_rx_clk0" IOSTANDARD = LVTTL;
#-----------------------------------------------------------
# Fast Skew maximises output setup and hold timing -
#-----------------------------------------------------------
INST "gmii_rxd0<?>" SLEW = FAST;
INST "gmii_rx_dv0" SLEW = FAST;
INST "gmii_rx_er0" SLEW = FAST;
INST "gmii_rx_clk0" SLEW = FAST;
#-----------------------------------------------------------
# GMII Transmitter Constraints: place flip-flops in IOB -
#-----------------------------------------------------------
INST "gmii_txd_iff0*" IOB = true;
INST "gmii_tx_en_iff0" IOB = true;
INST "gmii_tx_er_iff0" IOB = true;
#-----------------------------------------------------------
# GMII Receiver Constraints: place flip-flops in IOB -
#-----------------------------------------------------------
INST "gmii_rxd_obuf0*" IOB = true;
INST "gmii_rx_dv_obuf0" IOB = true;
INST "gmii_rx_er_obuf0" IOB = true;
#-----------------------------------------------------------
# GMII Clock period Constraints: please do not relax -
#-----------------------------------------------------------
# Describe the GMII Tx clock at the input pads
NET "gmii_tx_clk0" TNM_NET = "gmii_tx_clk0";
TIMESPEC "ts_gmii_tx_clk0" = PERIOD "gmii_tx_clk0" 8000 ps HIGH 50 %;
#-----------------------------------------------------------
# GMII Tx Elastic Buffer Constraints -
#-----------------------------------------------------------
# Identify clock domain crossing registers
INST "tx_elastic_buffer_inst0/rd_addrgray*" TNM = "rd_graycode0";
INST "tx_elastic_buffer_inst0/wr_addrgray*" TNM = "wr_graycode0";
# Control Gray Code delay and skew across clock boundary
TIMESPEC "ts_tx0_skew_control1" = FROM "rd_graycode0" TO "FFS" 6 ns DATAPATHONLY;
TIMESPEC "ts_tx0_skew_control2" = FROM "wr_graycode0" TO "FFS" 6 ns DATAPATHONLY;
# Constrain between Distributed Memory (output data) and the 1st set of flip-flops
INST "tx_elastic_buffer_inst0/txd_fifo_reg1*" TNM = "TX_FIFO_SAMPLE0";
INST "tx_elastic_buffer_inst0/tx_en_fifo_reg1" TNM = "TX_FIFO_SAMPLE0";
INST "tx_elastic_buffer_inst0/tx_er_fifo_reg1" TNM = "TX_FIFO_SAMPLE0";
TIMESPEC "ts_tx_rams_to_ffs0" = FROM "RAMS" TO "TX_FIFO_SAMPLE0" 6 ns DATAPATHONLY;
#-----------------------------------------------------------
# For the purposes of this example design, set all other -
# I/O to also use LVTTL. -
# -
# This prevents PAR experiencing IOB banking issues due to -
# different Voltage standards. -
# -
#-----------------------------------------------------------
INST "configuration_vector0<?>" IOSTANDARD = LVTTL;
INST "reset0" IOSTANDARD = LVTTL;
INST "signal_detect0" IOSTANDARD = LVTTL;
INST "status_vector0*" IOSTANDARD = LVTTL;
--------------------------------------------------------------------------------
-- File : gig_eth_pcs_pma_v11_4_reset_sync.vhd
-- Author : Xilinx Inc.
--------------------------------------------------------------------------------
-- Description: Both flip-flops have the same asynchronous reset signal.
-- Together the flops create a minimum of a 1 clock period
-- duration pulse which is used for synchronous reset.
--
-- The flops are placed, using RLOCs, into the same slice.
--------------------------------------------------------------------------------
-- (c) Copyright 2006-2008 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity gig_eth_pcs_pma_v11_4_reset_sync is
generic (INITIALISE : bit_vector(1 downto 0) := "11");
port (
reset_in : in std_logic; -- Active high asynchronous reset
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
end gig_eth_pcs_pma_v11_4_reset_sync;
architecture rtl of gig_eth_pcs_pma_v11_4_RESET_SYNC is
signal reset_sync_reg : std_logic;
-- These attributes will stop timing errors being reported in back annotated
-- SDF simulation.
attribute ASYNC_REG : string;
attribute ASYNC_REG of reset_sync_reg : signal is "TRUE";
attribute ASYNC_REG of reset_out : signal is "TRUE";
-- These attributes will stop XST translating the desired flip-flops into an
-- SRL based shift register.
attribute shreg_extract : string;
attribute shreg_extract of reset_sync_reg : signal is "no";
attribute shreg_extract of reset_out : signal is "no";
begin
reset_sync1 : FDP
generic map (
INIT => INITIALISE(0)
)
port map (
C => clk,
PRE => reset_in,
D => '0',
Q => reset_sync_reg
);
reset_sync2 : FDP
generic map (
INIT => INITIALISE(1)
)
port map (
C => clk,
PRE => reset_in,
D => reset_sync_reg,
Q => reset_out
);
end rtl;
--------------------------------------------------------------------------------
-- File : gig_eth_pcs_pma_v11_4_sync_block.vhd
-- Author : Xilinx Inc.
--------------------------------------------------------------------------------
-- Description: Used on signals crossing from one clock domain to
-- another, this is a flip-flop pair, with both flops
-- placed together with RLOCs into the same slice. Thus
-- the routing delay between the two is minimum to safe-
-- guard against metastability issues.
--------------------------------------------------------------------------------
-- (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity gig_eth_pcs_pma_v11_4_sync_block is
generic (
INITIALISE : bit_vector(1 downto 0) := "00"
);
port (
clk : in std_logic; -- clock to be sync'ed to
data_in : in std_logic; -- Data to be 'synced'
data_out : out std_logic -- synced data
);
end gig_eth_pcs_pma_v11_4_sync_block;
architecture structural of gig_eth_pcs_pma_v11_4_sync_block is
-- Internal Signals
signal data_sync1 : std_logic;
-- These attributes will stop timing errors being reported in back annotated
-- SDF simulation.
attribute ASYNC_REG : string;
attribute ASYNC_REG of data_sync1 : signal is "TRUE";
-- These attributes will stop XST translating the desired flip-flops into an
-- SRL based shift register.
attribute shreg_extract : string;
attribute shreg_extract of data_sync1 : signal is "no";
attribute shreg_extract of data_out : signal is "no";
begin
data_sync : FD
generic map (
INIT => INITIALISE(0)
)
port map (
C => clk,
D => data_in,
Q => data_sync1
);
data_sync_reg : FD
generic map (
INIT => INITIALISE(1)
)
port map (
C => clk,
D => data_sync1,
Q => data_out
);
end structural;
# RLOCs for reset_sync / sync_block logic
#------------------------------------------------------
# To keep the FF pairs in the same slice to minimise routing delay between them
BEGIN MODEL sync_block
INST "data_sync" rloc = X0Y0;
INST "data_sync_reg" rloc = X0Y0;
END;
BEGIN MODEL reset_sync
INST "reset_sync1" rloc = X0Y0;
INST "reset_sync2" rloc = X0Y0;
END;
REM Clean up the results directory
rmdir /S /Q results
mkdir results
REM Synthesize the Example Design
rem Synthesize the VHDL Wrapper Files
echo 'Synthesizing the example design with XST';
xst -ifn xst.scr
copy gig_eth_pcs_pma_v11_4_example_design.ngc .\results\
REM Copy the netlist generated by Coregen
echo 'Copy files from the netlist directory to the results directory'
copy ..\..\gig_eth_pcs_pma_v11_4.ngc results
REM Copy the constraints files generated by Coregen
echo 'Copy files from constraints directory to results directory'
copy ..\example_design\gig_eth_pcs_pma_v11_4_example_design.ucf results\
cd results
echo 'Running ngdbuild'
ngdbuild gig_eth_pcs_pma_v11_4_example_design
echo 'Running map'
map -ol high -timing gig_eth_pcs_pma_v11_4_example_design -o mapped.ncd
echo 'Running par'
par -ol high -w mapped.ncd routed.ncd mapped.pcf
echo 'Running trce'
trce -u -e 10 routed -o routed mapped.pcf
echo 'Running design through bitgen'
bitgen -w routed.ncd routed mapped.pcf
echo 'Running netgen to create gate level VHDL model'
netgen -ofmt vhdl -pcf mapped.pcf -sim -dir . -tm gig_eth_pcs_pma_v11_4_example_design -w routed.ncd routed.vhd
#!/bin/sh
# Clean up the results directory
rm -rf results
mkdir results
# Synthesize the Example Design
echo 'Synthesizing the example design with XST';
xst -ifn xst.scr
cp gig_eth_pcs_pma_v11_4_example_design.ngc ./results/
# Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
cp ../../gig_eth_pcs_pma_v11_4.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/gig_eth_pcs_pma_v11_4_example_design.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild gig_eth_pcs_pma_v11_4_example_design
echo 'Running map'
map -ol high -timing gig_eth_pcs_pma_v11_4_example_design -o mapped.ncd
echo 'Running par'
par -ol high -w mapped.ncd routed.ncd mapped.pcf
echo 'Running trce'
trce -u -e 10 routed -o routed mapped.pcf
echo 'Running design through bitgen'
bitgen -w routed.ncd routed mapped.pcf
echo 'Running netgen to create gate level VHDL model'
netgen -ofmt vhdl -pcf mapped.pcf -sim -dir . -tm gig_eth_pcs_pma_v11_4_example_design -w routed.ncd routed.vhd
vhdl work ../example_design/gig_eth_pcs_pma_v11_4_sync_block.vhd
vhdl work ../example_design/gig_eth_pcs_pma_v11_4_reset_sync.vhd
vhdl work ../example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard_tile.vhd
vhdl work ../example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.vhd
vhdl work ../example_design/transceiver/gig_eth_pcs_pma_v11_4_transceiver_A.vhd
vhdl work ../example_design/gig_eth_pcs_pma_v11_4_tx_elastic_buffer.vhd
vhdl work ../example_design/gig_eth_pcs_pma_v11_4_block.vhd
vhdl work ../example_design/gig_eth_pcs_pma_v11_4_example_design.vhd
# XST synthesis script for GPCS_PMA core.
set -tmpdir .
set -xsthdpdir ./xst
run
-ifmt mixed
-top gig_eth_pcs_pma_v11_4_example_design
-ofn gig_eth_pcs_pma_v11_4_example_design
-p spartan6
-uc example_design_xst.xcf
-ifn xst.prj
-iobuf YES
vlib work
vmap work work
echo "Compiling Core Simulation Models"
vcom -work work ../../../gig_eth_pcs_pma_v11_4.vhd
echo "Compiling Example Design"
vcom -2008 -work work \
../../example_design/gig_eth_pcs_pma_v11_4_sync_block.vhd \
../../example_design/gig_eth_pcs_pma_v11_4_reset_sync.vhd \
../../example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard_tile.vhd \
../../example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.vhd \
../../example_design/transceiver/gig_eth_pcs_pma_v11_4_transceiver_A.vhd \
../../example_design/gig_eth_pcs_pma_v11_4_tx_elastic_buffer.vhd \
../../example_design/gig_eth_pcs_pma_v11_4_block.vhd \
../../example_design/gig_eth_pcs_pma_v11_4_example_design.vhd
echo "Compiling Test Bench"
vcom -work work -novopt ../stimulus_tb.vhd ../demo_tb.vhd
echo "Starting simulation"
vsim -voptargs="+acc" -t ps work.demo_tb
do wave_mti.do
run -all
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="NetListWriters" num="635" delta="old" >The generated VHDL netlist contains Xilinx <arg fmt="%s" index="1">UNISIM</arg> simulation primitives and has to be used with <arg fmt="%s" index="2">UNISIM</arg> library for correct compilation and simulation.
</msg>
</messages>
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment