Commit b31f50a2 authored by David Cussans's avatar David Cussans

Comissioning boards.

* Took pictures of assembled boards.

* Exported netlist from Circuit schematic.

* Changed clocks to be 31.25MHz IPBus clock.

* General tidying. Unfortunately, latest design doesn't respond to "ping"....



git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@29 e1591323-3689-4d5a-aa31-d1a7cbdc5706
parent dfeb5646
{ Machine generated file created by SPI } { Machine generated file created by SPI }
{ Last modified was 12:29:39 Monday, February 23, 2015 } { Last modified was 15:08:38 Monday, March 23, 2015 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by } { NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. } { SPI, your modifications will be overwritten. }
......
...@@ -8,7 +8,7 @@ C2 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL ...@@ -8,7 +8,7 @@ C2 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
C2_1 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL C2_1 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
2 VDDD2_1 2 VDDD2_1
C3 CAPCERSMDCL2_0402-1UF,16V 1 GND_SIGNAL C3 CAPCERSMDCL2_0402-1UF,16V 1 GND_SIGNAL
2 AVDD 2 P3V3
C3_1 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL C3_1 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
2 VDD_DAC_1 2 VDD_DAC_1
C4 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL C4 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
...@@ -312,25 +312,25 @@ C103 CAPCERSMDCL2_0603-100NF,16V 1 P2V5 ...@@ -312,25 +312,25 @@ C103 CAPCERSMDCL2_0603-100NF,16V 1 P2V5
C104 CAPCERSMDCL2_0805-22UF,6.3V 1 GND_SIGNAL C104 CAPCERSMDCL2_0805-22UF,6.3V 1 GND_SIGNAL
2 MGT_AVCC_A 2 MGT_AVCC_A
C105 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL C105 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
2 UNNAMED_7_CAPCERSMDCL2_I74_B 2 MGT_AVCC_A
C106 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL C106 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
2 UNNAMED_7_CAPCERSMDCL2_I70_B 2 MGT_AVCC_A
C107 CAPCERSMDCL2_0402-1UF,16V 1 GND_SIGNAL C107 CAPCERSMDCL2_0402-1UF,16V 1 GND_SIGNAL
2 MGT_AVCC_A 2 MGT_AVCC_A
C108 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL C108 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
2 UNNAMED_7_CAPCERSMDCL2_I74_B 2 MGT_AVCC_A
C109 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL C109 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
2 UNNAMED_7_CAPCERSMDCL2_I70_B 2 MGT_AVCC_A
C110 CAPCERSMDCL2_0402-1UF,16V 1 GND_SIGNAL C110 CAPCERSMDCL2_0402-1UF,16V 1 GND_SIGNAL
2 MGT_AVCC_A 2 MGT_AVCC_A
C111 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL C111 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
2 UNNAMED_7_CAPCERSMDCL2_I74_B 2 MGT_AVCC_A
C112 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL C112 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
2 UNNAMED_7_CAPCERSMDCL2_I70_B 2 MGT_AVCC_A
C113 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL C113 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
2 UNNAMED_7_CAPCERSMDCL2_I74_B 2 MGT_AVCC_A
C114 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL C114 CAPCERSMDCL2_0402-100NF,16V_GEN 1 GND_SIGNAL
2 UNNAMED_7_CAPCERSMDCL2_I70_B 2 MGT_AVCC_A
C115 CAPCERSMDCL2_1206-100UF_X5R,6.A 1 GND_SIGNAL C115 CAPCERSMDCL2_1206-100UF_X5R,6.A 1 GND_SIGNAL
2 P1V2 2 P1V2
C116 CAPCERSMDCL2_1206-100UF_X5R,6.A 1 GND_SIGNAL C116 CAPCERSMDCL2_1206-100UF_X5R,6.A 1 GND_SIGNAL
...@@ -879,7 +879,7 @@ IC15 24AA64T-I/MC 1 GND_SIGNAL ...@@ -879,7 +879,7 @@ IC15 24AA64T-I/MC 1 GND_SIGNAL
6 FPGA_SCL 6 FPGA_SCL
7 GND_SIGNAL 7 GND_SIGNAL
8 P3V3 8 P3V3
IC16 SN74LVC1G06DBVT 2 FPGA_DONE IC16 SN74LVC1G06DBVT-GND=GND_SIGNALA 2 FPGA_DONE
4 UNNAMED_13_LED_I46_K 4 UNNAMED_13_LED_I46_K
IC20 TPS71701DCKRG4_SC70-TEXAS INSTA 1 P2V5 IC20 TPS71701DCKRG4_SC70-TEXAS INSTA 1 P2V5
2 GND_SIGNAL 2 GND_SIGNAL
...@@ -1726,22 +1726,22 @@ RG1_1 LM2937IMP_SOT223-2.5V,TI 1 AVDD ...@@ -1726,22 +1726,22 @@ RG1_1 LM2937IMP_SOT223-2.5V,TI 1 AVDD
2 GND_SIGNAL 2 GND_SIGNAL
3 VH_1 3 VH_1
4 GND_SIGNAL 4 GND_SIGNAL
RN1 R4ISMD_1206-150 1 FPGA_GPIO<3> RN1 R4ISMD_1206-150 1 UNNAMED_8_CON12P_I51_A_1
2 FPGA_GPIO<2> 2 UNNAMED_8_CON12P_I51_A_2
3 FPGA_GPIO<1> 3 UNNAMED_8_CON12P_I51_A_3
4 FPGA_GPIO<0> 4 UNNAMED_8_CON12P_I51_A_4
5 UNNAMED_8_CON12P_I51_A_4 5 FPGA_GPIO<0>
6 UNNAMED_8_CON12P_I51_A_3 6 FPGA_GPIO<1>
7 UNNAMED_8_CON12P_I51_A_2 7 FPGA_GPIO<2>
8 UNNAMED_8_CON12P_I51_A_1 8 FPGA_GPIO<3>
RN2 R4ISMD_1206-150 1 UNNAMED_8_CON12P_I51_A RN2 R4ISMD_1206-150 1 FPGA_GPIO<7>
2 UNNAMED_8_CON12P_I51_A_7 2 FPGA_GPIO<6>
3 UNNAMED_8_CON12P_I51_A_5 3 FPGA_GPIO<5>
4 UNNAMED_8_CON12P_I51_A_6 4 FPGA_GPIO<4>
5 FPGA_GPIO<4> 5 UNNAMED_8_CON12P_I51_A_6
6 FPGA_GPIO<5> 6 UNNAMED_8_CON12P_I51_A_5
7 FPGA_GPIO<6> 7 UNNAMED_8_CON12P_I51_A_7
8 FPGA_GPIO<7> 8 UNNAMED_8_CON12P_I51_A
RZ1 R4ISMD_1206-150 1 GND_SIGNAL RZ1 R4ISMD_1206-150 1 GND_SIGNAL
2 GND_SIGNAL 2 GND_SIGNAL
3 GND_SIGNAL 3 GND_SIGNAL
...@@ -1750,14 +1750,14 @@ RZ1 R4ISMD_1206-150 1 GND_SIGNAL ...@@ -1750,14 +1750,14 @@ RZ1 R4ISMD_1206-150 1 GND_SIGNAL
6 UNNAMED_8_LED_I108_K 6 UNNAMED_8_LED_I108_K
7 UNNAMED_8_LED_I107_K 7 UNNAMED_8_LED_I107_K
8 UNNAMED_8_LED_I105_K 8 UNNAMED_8_LED_I105_K
RZ2 R4ISMD_1206-4.7K 1 GND_SIGNAL RZ2 R4ISMD_1206-4.7K 1 DIP_SWITCH<3>
2 GND_SIGNAL 2 DIP_SWITCH<2>
3 GND_SIGNAL 3 DIP_SWITCH<1>
4 GND_SIGNAL 4 DIP_SWITCH<0>
5 DIP_SWITCH<0> 5 GND_SIGNAL
6 DIP_SWITCH<1> 6 GND_SIGNAL
7 DIP_SWITCH<2> 7 GND_SIGNAL
8 DIP_SWITCH<3> 8 GND_SIGNAL
SW1 SW_PUSHBUTTON_1SPSTA_4P_1-OMROA 1 UNNAMED_8_RSMD0603_I92_B SW1 SW_PUSHBUTTON_1SPSTA_4P_1-OMROA 1 UNNAMED_8_RSMD0603_I92_B
2 P3V3 2 P3V3
3 UNNAMED_8_RSMD0603_I92_B 3 UNNAMED_8_RSMD0603_I92_B
...@@ -2017,7 +2017,7 @@ U2 AD8031_SOT23-5-AD 1 UNNAMED_8_AD8031_I70_IN ...@@ -2017,7 +2017,7 @@ U2 AD8031_SOT23-5-AD 1 UNNAMED_8_AD8031_I70_IN
2 GND_SIGNAL 2 GND_SIGNAL
3 UNBUF_CTEST 3 UNBUF_CTEST
4 UNNAMED_8_AD8031_I70_IN 4 UNNAMED_8_AD8031_I70_IN
5 AVDD 5 P3V3
U3 PC049A_FPGA A1 GND_SIGNAL U3 PC049A_FPGA A1 GND_SIGNAL
A2 LVDS_DLEFT_N<15> A2 LVDS_DLEFT_N<15>
A3 LVDS_DLEFT_N<14> A3 LVDS_DLEFT_N<14>
...@@ -2207,8 +2207,8 @@ U3 PC049A_FPGA A1 GND_SIGNAL ...@@ -2207,8 +2207,8 @@ U3 PC049A_FPGA A1 GND_SIGNAL
H2 FPGA_LEDS<2> H2 FPGA_LEDS<2>
H3 FPGA_LEDS<1> H3 FPGA_LEDS<1>
H4 FPGA_LEDS<0> H4 FPGA_LEDS<0>
H5 P3V3 H5 UNNAMED_8_RSMD0603_I92_B
H6 P3V3 H6 UNNAMED_8_RSMD0603_I97_B
H7 GND_SIGNAL H7 GND_SIGNAL
H9 P2V5 H9 P2V5
H15 P2V5 H15 P2V5
......
...@@ -131,7 +131,6 @@ ANALOG_TO_MAROC<62> U1_1 61 MAROC3_PQFP-IN2P3 ...@@ -131,7 +131,6 @@ ANALOG_TO_MAROC<62> U1_1 61 MAROC3_PQFP-IN2P3
ANALOG_TO_MAROC<63> J1 127 CON150P-QTS75_03FDA-P1=GND_SIGA ANALOG_TO_MAROC<63> J1 127 CON150P-QTS75_03FDA-P1=GND_SIGA
ANALOG_TO_MAROC<63> U1_1 62 MAROC3_PQFP-IN2P3 ANALOG_TO_MAROC<63> U1_1 62 MAROC3_PQFP-IN2P3
AVDD C29_1 2 CAPCERSMDCL2_0402-100NF,16V_GEN AVDD C29_1 2 CAPCERSMDCL2_0402-100NF,16V_GEN
AVDD C3 2 CAPCERSMDCL2_0402-1UF,16V
AVDD C54_1 2 CAPCERSMDCL2_0603-10UF,6.3V AVDD C54_1 2 CAPCERSMDCL2_0603-10UF,6.3V
AVDD C98 2 CAPCERSMDCL2_0805-22UF,6.3V AVDD C98 2 CAPCERSMDCL2_0805-22UF,6.3V
AVDD IC21 3 LP38692_SOT223-ADJ,TEXAS INSTRA AVDD IC21 3 LP38692_SOT223-ADJ,TEXAS INSTRA
...@@ -168,7 +167,6 @@ AVDD R7_1 2 RSMD0402_1/16W-10R,5% ...@@ -168,7 +167,6 @@ AVDD R7_1 2 RSMD0402_1/16W-10R,5%
AVDD R8_1 2 RSMD0402_1/16W-10R,5% AVDD R8_1 2 RSMD0402_1/16W-10R,5%
AVDD R9_1 2 RSMD0402_1/16W-10R,5% AVDD R9_1 2 RSMD0402_1/16W-10R,5%
AVDD RG1_1 1 LM2937IMP_SOT223-2.5V,TI AVDD RG1_1 1 LM2937IMP_SOT223-2.5V,TI
AVDD U2 5 AD8031_SOT23-5-AD
CKB_40M J3_1 3 CON3P-SIL254D CKB_40M J3_1 3 CON3P-SIL254D
CKB_40M R24_1 2 RSMD0402_1/16W-100,1% CKB_40M R24_1 2 RSMD0402_1/16W-100,1%
CKB_40M U1_1 186 MAROC3_PQFP-IN2P3 CKB_40M U1_1 186 MAROC3_PQFP-IN2P3
...@@ -393,16 +391,16 @@ DIG_CTEST<4> R33 2 RSMD0603_1/16W-2.4K,1% ...@@ -393,16 +391,16 @@ DIG_CTEST<4> R33 2 RSMD0603_1/16W-2.4K,1%
DIG_CTEST<4> U3 C1 PC049A_FPGA DIG_CTEST<4> U3 C1 PC049A_FPGA
DIG_CTEST<5> R35 2 RSMD0603_1/16W-2.4K,1% DIG_CTEST<5> R35 2 RSMD0603_1/16W-2.4K,1%
DIG_CTEST<5> U3 E4 PC049A_FPGA DIG_CTEST<5> U3 E4 PC049A_FPGA
DIP_SWITCH<0> RZ2 5 R4ISMD_1206-4.7K DIP_SWITCH<0> RZ2 4 R4ISMD_1206-4.7K
DIP_SWITCH<0> SW3 8 SW4INT-1571983-4 DIP_SWITCH<0> SW3 8 SW4INT-1571983-4
DIP_SWITCH<0> U3 J6 PC049A_FPGA DIP_SWITCH<0> U3 J6 PC049A_FPGA
DIP_SWITCH<1> RZ2 6 R4ISMD_1206-4.7K DIP_SWITCH<1> RZ2 3 R4ISMD_1206-4.7K
DIP_SWITCH<1> SW3 6 SW4INT-1571983-4 DIP_SWITCH<1> SW3 6 SW4INT-1571983-4
DIP_SWITCH<1> U3 J4 PC049A_FPGA DIP_SWITCH<1> U3 J4 PC049A_FPGA
DIP_SWITCH<2> RZ2 7 R4ISMD_1206-4.7K DIP_SWITCH<2> RZ2 2 R4ISMD_1206-4.7K
DIP_SWITCH<2> SW3 4 SW4INT-1571983-4 DIP_SWITCH<2> SW3 4 SW4INT-1571983-4
DIP_SWITCH<2> U3 J3 PC049A_FPGA DIP_SWITCH<2> U3 J3 PC049A_FPGA
DIP_SWITCH<3> RZ2 8 R4ISMD_1206-4.7K DIP_SWITCH<3> RZ2 1 R4ISMD_1206-4.7K
DIP_SWITCH<3> SW3 2 SW4INT-1571983-4 DIP_SWITCH<3> SW3 2 SW4INT-1571983-4
DIP_SWITCH<3> U3 K1 PC049A_FPGA DIP_SWITCH<3> U3 K1 PC049A_FPGA
D_R LK67_1 1 1-HOLE_0-8-BASE D_R LK67_1 1 1-HOLE_0-8-BASE
...@@ -418,24 +416,24 @@ ENABLE_GLOBALTRIG_DRIVE U3 T2 PC049A_FPGA ...@@ -418,24 +416,24 @@ ENABLE_GLOBALTRIG_DRIVE U3 T2 PC049A_FPGA
EN_OTAG LK58_1 1 1-HOLE_0-8-BASE EN_OTAG LK58_1 1 1-HOLE_0-8-BASE
EN_OTAG U1_1 213 MAROC3_PQFP-IN2P3 EN_OTAG U1_1 213 MAROC3_PQFP-IN2P3
EN_OTAG U3 V5 PC049A_FPGA EN_OTAG U3 V5 PC049A_FPGA
FPGA_DONE IC16 2 SN74LVC1G06DBVT FPGA_DONE IC16 2 SN74LVC1G06DBVT-GND=GND_SIGNALA
FPGA_DONE R61 1 RSMD0603_1/10W-330,1% FPGA_DONE R61 1 RSMD0603_1/10W-330,1%
FPGA_DONE U3 AB21 PC049A_FPGA FPGA_DONE U3 AB21 PC049A_FPGA
FPGA_GPIO<0> RN1 4 R4ISMD_1206-150 FPGA_GPIO<0> RN1 5 R4ISMD_1206-150
FPGA_GPIO<0> U3 G4 PC049A_FPGA FPGA_GPIO<0> U3 G4 PC049A_FPGA
FPGA_GPIO<1> RN1 3 R4ISMD_1206-150 FPGA_GPIO<1> RN1 6 R4ISMD_1206-150
FPGA_GPIO<1> U3 G3 PC049A_FPGA FPGA_GPIO<1> U3 G3 PC049A_FPGA
FPGA_GPIO<2> RN1 2 R4ISMD_1206-150 FPGA_GPIO<2> RN1 7 R4ISMD_1206-150
FPGA_GPIO<2> U3 G1 PC049A_FPGA FPGA_GPIO<2> U3 G1 PC049A_FPGA
FPGA_GPIO<3> RN1 1 R4ISMD_1206-150 FPGA_GPIO<3> RN1 8 R4ISMD_1206-150
FPGA_GPIO<3> U3 G6 PC049A_FPGA FPGA_GPIO<3> U3 G6 PC049A_FPGA
FPGA_GPIO<4> RN2 5 R4ISMD_1206-150 FPGA_GPIO<4> RN2 4 R4ISMD_1206-150
FPGA_GPIO<4> U3 F3 PC049A_FPGA FPGA_GPIO<4> U3 F3 PC049A_FPGA
FPGA_GPIO<5> RN2 6 R4ISMD_1206-150 FPGA_GPIO<5> RN2 3 R4ISMD_1206-150
FPGA_GPIO<5> U3 F2 PC049A_FPGA FPGA_GPIO<5> U3 F2 PC049A_FPGA
FPGA_GPIO<6> RN2 7 R4ISMD_1206-150 FPGA_GPIO<6> RN2 2 R4ISMD_1206-150
FPGA_GPIO<6> U3 F1 PC049A_FPGA FPGA_GPIO<6> U3 F1 PC049A_FPGA
FPGA_GPIO<7> RN2 8 R4ISMD_1206-150 FPGA_GPIO<7> RN2 1 R4ISMD_1206-150
FPGA_GPIO<7> U3 F5 PC049A_FPGA FPGA_GPIO<7> U3 F5 PC049A_FPGA
FPGA_LEDS<0> LD5 1 LED-HSMH-C150 FPGA_LEDS<0> LD5 1 LED-HSMH-C150
FPGA_LEDS<0> U3 H4 PC049A_FPGA FPGA_LEDS<0> U3 H4 PC049A_FPGA
...@@ -905,10 +903,10 @@ GND_SIGNAL RZ1 1 R4ISMD_1206-150 ...@@ -905,10 +903,10 @@ GND_SIGNAL RZ1 1 R4ISMD_1206-150
GND_SIGNAL RZ1 2 R4ISMD_1206-150 GND_SIGNAL RZ1 2 R4ISMD_1206-150
GND_SIGNAL RZ1 3 R4ISMD_1206-150 GND_SIGNAL RZ1 3 R4ISMD_1206-150
GND_SIGNAL RZ1 4 R4ISMD_1206-150 GND_SIGNAL RZ1 4 R4ISMD_1206-150
GND_SIGNAL RZ2 1 R4ISMD_1206-4.7K GND_SIGNAL RZ2 5 R4ISMD_1206-4.7K
GND_SIGNAL RZ2 2 R4ISMD_1206-4.7K GND_SIGNAL RZ2 6 R4ISMD_1206-4.7K
GND_SIGNAL RZ2 3 R4ISMD_1206-4.7K GND_SIGNAL RZ2 7 R4ISMD_1206-4.7K
GND_SIGNAL RZ2 4 R4ISMD_1206-4.7K GND_SIGNAL RZ2 8 R4ISMD_1206-4.7K
GND_SIGNAL SW4 1 SW_PUSHBUTTON_1SPSTA_4P_1-OMROA GND_SIGNAL SW4 1 SW_PUSHBUTTON_1SPSTA_4P_1-OMROA
GND_SIGNAL SW4 3 SW_PUSHBUTTON_1SPSTA_4P_1-OMROA GND_SIGNAL SW4 3 SW_PUSHBUTTON_1SPSTA_4P_1-OMROA
GND_SIGNAL U1 2 OSC_VCXO_4P_OSC_4PIN_53S-25MHZA GND_SIGNAL U1 2 OSC_VCXO_4P_OSC_4PIN_53S-25MHZA
...@@ -1230,8 +1228,16 @@ LVPECL_OTRIG_OUT_N U4 7 MC100LVEL05_SOIC-ON SEMICONDU ...@@ -1230,8 +1228,16 @@ LVPECL_OTRIG_OUT_N U4 7 MC100LVEL05_SOIC-ON SEMICONDU
LVPECL_OTRIG_OUT_P J3 A8 CONABC96-09 73 296 6801 LVPECL_OTRIG_OUT_P J3 A8 CONABC96-09 73 296 6801
LVPECL_OTRIG_OUT_P U4 6 MC100LVEL05_SOIC-ON SEMICONDUCA LVPECL_OTRIG_OUT_P U4 6 MC100LVEL05_SOIC-ON SEMICONDUCA
MGT_AVCC_A C104 2 CAPCERSMDCL2_0805-22UF,6.3V MGT_AVCC_A C104 2 CAPCERSMDCL2_0805-22UF,6.3V
MGT_AVCC_A C105 2 CAPCERSMDCL2_0402-100NF,16V_GEN
MGT_AVCC_A C106 2 CAPCERSMDCL2_0402-100NF,16V_GEN
MGT_AVCC_A C107 2 CAPCERSMDCL2_0402-1UF,16V MGT_AVCC_A C107 2 CAPCERSMDCL2_0402-1UF,16V
MGT_AVCC_A C108 2 CAPCERSMDCL2_0402-100NF,16V_GEN
MGT_AVCC_A C109 2 CAPCERSMDCL2_0402-100NF,16V_GEN
MGT_AVCC_A C110 2 CAPCERSMDCL2_0402-1UF,16V MGT_AVCC_A C110 2 CAPCERSMDCL2_0402-1UF,16V
MGT_AVCC_A C111 2 CAPCERSMDCL2_0402-100NF,16V_GEN
MGT_AVCC_A C112 2 CAPCERSMDCL2_0402-100NF,16V_GEN
MGT_AVCC_A C113 2 CAPCERSMDCL2_0402-100NF,16V_GEN
MGT_AVCC_A C114 2 CAPCERSMDCL2_0402-100NF,16V_GEN
MGT_AVCC_A L9 1 FERRITE_C0805-LI0805H121R-10,LA MGT_AVCC_A L9 1 FERRITE_C0805-LI0805H121R-10,LA
MGT_AVCC_A R53 2 RSMD0603_1/10W-51,1% MGT_AVCC_A R53 2 RSMD0603_1/10W-51,1%
MGT_AVCC_A U3 A7 PC049A_FPGA MGT_AVCC_A U3 A7 PC049A_FPGA
...@@ -1533,6 +1539,7 @@ P2V5 U3 W5 PC049A_FPGA ...@@ -1533,6 +1539,7 @@ P2V5 U3 W5 PC049A_FPGA
P2V5 U3 W21 PC049A_FPGA P2V5 U3 W21 PC049A_FPGA
P3V3 C1 2 CAPCERSMDCL2_0402-100NF,16V_GEN P3V3 C1 2 CAPCERSMDCL2_0402-100NF,16V_GEN
P3V3 C2 2 CAPCERSMDCL2_0402-100NF,16V_GEN P3V3 C2 2 CAPCERSMDCL2_0402-100NF,16V_GEN
P3V3 C3 2 CAPCERSMDCL2_0402-1UF,16V
P3V3 C4 2 CAPCERSMDCL2_0402-100NF,16V_GEN P3V3 C4 2 CAPCERSMDCL2_0402-100NF,16V_GEN
P3V3 C5 2 CAPCERSMDCL2_0402-100NF,16V_GEN P3V3 C5 2 CAPCERSMDCL2_0402-100NF,16V_GEN
P3V3 C6 2 CAPCERSMDCL2_0402-100NF,16V_GEN P3V3 C6 2 CAPCERSMDCL2_0402-100NF,16V_GEN
...@@ -1586,11 +1593,10 @@ P3V3 SW3 1 SW4INT-1571983-4 ...@@ -1586,11 +1593,10 @@ P3V3 SW3 1 SW4INT-1571983-4
P3V3 SW3 3 SW4INT-1571983-4 P3V3 SW3 3 SW4INT-1571983-4
P3V3 SW3 5 SW4INT-1571983-4 P3V3 SW3 5 SW4INT-1571983-4
P3V3 SW3 7 SW4INT-1571983-4 P3V3 SW3 7 SW4INT-1571983-4
P3V3 U2 5 AD8031_SOT23-5-AD
P3V3 U3 C2 PC049A_FPGA P3V3 U3 C2 PC049A_FPGA
P3V3 U3 F4 PC049A_FPGA P3V3 U3 F4 PC049A_FPGA
P3V3 U3 G2 PC049A_FPGA P3V3 U3 G2 PC049A_FPGA
P3V3 U3 H5 PC049A_FPGA
P3V3 U3 H6 PC049A_FPGA
P3V3 U3 J5 PC049A_FPGA P3V3 U3 J5 PC049A_FPGA
P3V3 U3 L2 PC049A_FPGA P3V3 U3 L2 PC049A_FPGA
P3V3 U3 L7 PC049A_FPGA P3V3 U3 L7 PC049A_FPGA
...@@ -2023,7 +2029,7 @@ UNNAMED_11_LTM4606_I72_VFB IC10 F12 LTM4606EV#PBF ...@@ -2023,7 +2029,7 @@ UNNAMED_11_LTM4606_I72_VFB IC10 F12 LTM4606EV#PBF
UNNAMED_11_LTM4606_I72_VFB R11 2 RSMD0603_1/16W-9K,1% UNNAMED_11_LTM4606_I72_VFB R11 2 RSMD0603_1/16W-9K,1%
UNNAMED_13_LED_I46_A LD1 1 LED-HSMH-C150 UNNAMED_13_LED_I46_A LD1 1 LED-HSMH-C150
UNNAMED_13_LED_I46_A R52 1 RSMD0603_1/10W-150,1% UNNAMED_13_LED_I46_A R52 1 RSMD0603_1/10W-150,1%
UNNAMED_13_LED_I46_K IC16 4 SN74LVC1G06DBVT UNNAMED_13_LED_I46_K IC16 4 SN74LVC1G06DBVT-GND=GND_SIGNALA
UNNAMED_13_LED_I46_K LD1 2 LED-HSMH-C150 UNNAMED_13_LED_I46_K LD1 2 LED-HSMH-C150
UNNAMED_13_PC049AFPGA_I56_INITB R62 1 RSMD0603_1/10W-4.7K,1% UNNAMED_13_PC049AFPGA_I56_INITB R62 1 RSMD0603_1/10W-4.7K,1%
UNNAMED_13_PC049AFPGA_I56_INITB U3 Y4 PC049A_FPGA UNNAMED_13_PC049AFPGA_I56_INITB U3 Y4 PC049A_FPGA
...@@ -2142,35 +2148,27 @@ UNNAMED_7_CAPCERSMDCL2_I3_A C17 1 CAPCERSMDCL2_0402-100NF,16 ...@@ -2142,35 +2148,27 @@ UNNAMED_7_CAPCERSMDCL2_I3_A C17 1 CAPCERSMDCL2_0402-100NF,16
UNNAMED_7_CAPCERSMDCL2_I3_A J5 6 SK_SATA_SMD_STR-MOLEX UNNAMED_7_CAPCERSMDCL2_I3_A J5 6 SK_SATA_SMD_STR-MOLEX
UNNAMED_7_CAPCERSMDCL2_I5_A C20 1 CAPCERSMDCL2_0402-100NF,16V_GEN UNNAMED_7_CAPCERSMDCL2_I5_A C20 1 CAPCERSMDCL2_0402-100NF,16V_GEN
UNNAMED_7_CAPCERSMDCL2_I5_A J5 5 SK_SATA_SMD_STR-MOLEX UNNAMED_7_CAPCERSMDCL2_I5_A J5 5 SK_SATA_SMD_STR-MOLEX
UNNAMED_7_CAPCERSMDCL2_I70_B C106 2 CAPCERSMDCL2_0402-100NF,16V_GEN
UNNAMED_7_CAPCERSMDCL2_I70_B C109 2 CAPCERSMDCL2_0402-100NF,16V_GEN
UNNAMED_7_CAPCERSMDCL2_I70_B C112 2 CAPCERSMDCL2_0402-100NF,16V_GEN
UNNAMED_7_CAPCERSMDCL2_I70_B C114 2 CAPCERSMDCL2_0402-100NF,16V_GEN
UNNAMED_7_CAPCERSMDCL2_I74_B C105 2 CAPCERSMDCL2_0402-100NF,16V_GEN
UNNAMED_7_CAPCERSMDCL2_I74_B C108 2 CAPCERSMDCL2_0402-100NF,16V_GEN
UNNAMED_7_CAPCERSMDCL2_I74_B C111 2 CAPCERSMDCL2_0402-100NF,16V_GEN
UNNAMED_7_CAPCERSMDCL2_I74_B C113 2 CAPCERSMDCL2_0402-100NF,16V_GEN
UNNAMED_7_PC049AFPGA_I38_MGTRRE R53 1 RSMD0603_1/10W-51,1% UNNAMED_7_PC049AFPGA_I38_MGTRRE R53 1 RSMD0603_1/10W-51,1%
UNNAMED_7_PC049AFPGA_I38_MGTRRE U3 E9 PC049A_FPGA UNNAMED_7_PC049AFPGA_I38_MGTRRE U3 E9 PC049A_FPGA
UNNAMED_8_AD8031_I70_IN R50 2 RSMD0603_1/10W-180,1% UNNAMED_8_AD8031_I70_IN R50 2 RSMD0603_1/10W-180,1%
UNNAMED_8_AD8031_I70_IN U2 1 AD8031_SOT23-5-AD UNNAMED_8_AD8031_I70_IN U2 1 AD8031_SOT23-5-AD
UNNAMED_8_AD8031_I70_IN U2 4 AD8031_SOT23-5-AD UNNAMED_8_AD8031_I70_IN U2 4 AD8031_SOT23-5-AD
UNNAMED_8_CON12P_I51_A J10 8 CON12P-TSM-106-01-S-DV UNNAMED_8_CON12P_I51_A J10 8 CON12P-TSM-106-01-S-DV
UNNAMED_8_CON12P_I51_A RN2 1 R4ISMD_1206-150 UNNAMED_8_CON12P_I51_A RN2 8 R4ISMD_1206-150
UNNAMED_8_CON12P_I51_A_1 J10 7 CON12P-TSM-106-01-S-DV UNNAMED_8_CON12P_I51_A_1 J10 7 CON12P-TSM-106-01-S-DV
UNNAMED_8_CON12P_I51_A_1 RN1 8 R4ISMD_1206-150 UNNAMED_8_CON12P_I51_A_1 RN1 1 R4ISMD_1206-150
UNNAMED_8_CON12P_I51_A_2 J10 5 CON12P-TSM-106-01-S-DV UNNAMED_8_CON12P_I51_A_2 J10 5 CON12P-TSM-106-01-S-DV
UNNAMED_8_CON12P_I51_A_2 RN1 7 R4ISMD_1206-150 UNNAMED_8_CON12P_I51_A_2 RN1 2 R4ISMD_1206-150
UNNAMED_8_CON12P_I51_A_3 J10 3 CON12P-TSM-106-01-S-DV UNNAMED_8_CON12P_I51_A_3 J10 3 CON12P-TSM-106-01-S-DV
UNNAMED_8_CON12P_I51_A_3 RN1 6 R4ISMD_1206-150 UNNAMED_8_CON12P_I51_A_3 RN1 3 R4ISMD_1206-150
UNNAMED_8_CON12P_I51_A_4 J10 1 CON12P-TSM-106-01-S-DV UNNAMED_8_CON12P_I51_A_4 J10 1 CON12P-TSM-106-01-S-DV
UNNAMED_8_CON12P_I51_A_4 RN1 5 R4ISMD_1206-150 UNNAMED_8_CON12P_I51_A_4 RN1 4 R4ISMD_1206-150
UNNAMED_8_CON12P_I51_A_5 J10 4 CON12P-TSM-106-01-S-DV UNNAMED_8_CON12P_I51_A_5 J10 4 CON12P-TSM-106-01-S-DV
UNNAMED_8_CON12P_I51_A_5 RN2 3 R4ISMD_1206-150 UNNAMED_8_CON12P_I51_A_5 RN2 6 R4ISMD_1206-150
UNNAMED_8_CON12P_I51_A_6 J10 2 CON12P-TSM-106-01-S-DV UNNAMED_8_CON12P_I51_A_6 J10 2 CON12P-TSM-106-01-S-DV
UNNAMED_8_CON12P_I51_A_6 RN2 4 R4ISMD_1206-150 UNNAMED_8_CON12P_I51_A_6 RN2 5 R4ISMD_1206-150
UNNAMED_8_CON12P_I51_A_7 J10 6 CON12P-TSM-106-01-S-DV UNNAMED_8_CON12P_I51_A_7 J10 6 CON12P-TSM-106-01-S-DV
UNNAMED_8_CON12P_I51_A_7 RN2 2 R4ISMD_1206-150 UNNAMED_8_CON12P_I51_A_7 RN2 7 R4ISMD_1206-150
UNNAMED_8_LED_I105_K LD5 2 LED-HSMH-C150 UNNAMED_8_LED_I105_K LD5 2 LED-HSMH-C150
UNNAMED_8_LED_I105_K RZ1 8 R4ISMD_1206-150 UNNAMED_8_LED_I105_K RZ1 8 R4ISMD_1206-150
UNNAMED_8_LED_I106_K LD2 2 LED-HSMH-C150 UNNAMED_8_LED_I106_K LD2 2 LED-HSMH-C150
...@@ -2199,9 +2197,11 @@ UNNAMED_8_RSMD0603_I82_A R26 1 RSMD0603_1/16W-1.2K,1% ...@@ -2199,9 +2197,11 @@ UNNAMED_8_RSMD0603_I82_A R26 1 RSMD0603_1/16W-1.2K,1%
UNNAMED_8_RSMD0603_I92_B R57 2 RSMD0603_1/10W-4.7K,1% UNNAMED_8_RSMD0603_I92_B R57 2 RSMD0603_1/10W-4.7K,1%
UNNAMED_8_RSMD0603_I92_B SW1 1 SW_PUSHBUTTON_1SPSTA_4P_1-OMROA UNNAMED_8_RSMD0603_I92_B SW1 1 SW_PUSHBUTTON_1SPSTA_4P_1-OMROA
UNNAMED_8_RSMD0603_I92_B SW1 3 SW_PUSHBUTTON_1SPSTA_4P_1-OMROA UNNAMED_8_RSMD0603_I92_B SW1 3 SW_PUSHBUTTON_1SPSTA_4P_1-OMROA
UNNAMED_8_RSMD0603_I92_B U3 H5 PC049A_FPGA
UNNAMED_8_RSMD0603_I97_B R58 2 RSMD0603_1/10W-4.7K,1% UNNAMED_8_RSMD0603_I97_B R58 2 RSMD0603_1/10W-4.7K,1%
UNNAMED_8_RSMD0603_I97_B SW2 1 SW_PUSHBUTTON_1SPSTA_4P_1-OMROA UNNAMED_8_RSMD0603_I97_B SW2 1 SW_PUSHBUTTON_1SPSTA_4P_1-OMROA
UNNAMED_8_RSMD0603_I97_B SW2 3 SW_PUSHBUTTON_1SPSTA_4P_1-OMROA UNNAMED_8_RSMD0603_I97_B SW2 3 SW_PUSHBUTTON_1SPSTA_4P_1-OMROA
UNNAMED_8_RSMD0603_I97_B U3 H6 PC049A_FPGA
UNNAMED_9_CAPCERSMDCL2_I30_B<0> C79 2 CAPCERSMDCL2_1210-10UF,50V UNNAMED_9_CAPCERSMDCL2_I30_B<0> C79 2 CAPCERSMDCL2_1210-10UF,50V
UNNAMED_9_CAPCERSMDCL2_I30_B<0> C80 2 CAPCERSMDCL2_1210-10UF,50V UNNAMED_9_CAPCERSMDCL2_I30_B<0> C80 2 CAPCERSMDCL2_1210-10UF,50V
UNNAMED_9_CAPCERSMDCL2_I30_B<0> IC4 B7 LTM4606EV#PBF UNNAMED_9_CAPCERSMDCL2_I30_B<0> IC4 B7 LTM4606EV#PBF
......
...@@ -92,11 +92,11 @@ RSMD0603_1/16W-40.2K,1% R0603_40K2_1%_0.063W_100PPM 1 ...@@ -92,11 +92,11 @@ RSMD0603_1/16W-40.2K,1% R0603_40K2_1%_0.063W_100PPM 1
RSMD0603_1/16W-9K,1% R0603_9K_1%_0.063W_100PPM 1 RSMD0603_1/16W-9K,1% R0603_9K_1%_0.063W_100PPM 1
RSMD0805_-00, R0805_00_JUMPER 2 RSMD0805_-00, R0805_00_JUMPER 2
S25FL128SAGMFIR01-VCC=P3V3,VSSA S25FL128SAGMFIR01 1 S25FL128SAGMFIR01-VCC=P3V3,VSSA S25FL128SAGMFIR01 1
SFP_CAGE-6367034-1 6367034-1 2 SFP_CAGE-6367034-1-GND=GND_SIGA 6367034-1 2
SFP_CAGE-6367035-1 6367035-1 2 SFP_CAGE-6367035-1-GND=GND_SIGA 6367035-1 2
SK_SATA_SMD_STR-MOLEX Molex 67800-5025 2 SK_SATA_SMD_STR-MOLEX Molex 67800-5025 2
SN65LVDS1_SOT23-5-TEXAS INSTRUA snlvds1dbv 1 SN65LVDS1_SOT23-5-TEXAS INSTRUA snlvds1dbv 1
SN74LVC1G06DBVT SN74LVC1G06DBVT 1 SN74LVC1G06DBVT-GND=GND_SIGNALA SN74LVC1G06DBVT 1
SW4INT-1571983-4 1571983-4 1 SW4INT-1571983-4 1571983-4 1
SW_PUSHBUTTON_1SPSTA_4P_1-OMROA b3sn-3012 3 SW_PUSHBUTTON_1SPSTA_4P_1-OMROA b3sn-3012 3
TPS71701DCKRG4_SC70-TEXAS INSTA TI tps71701dckrg4 1 TPS71701DCKRG4_SC70-TEXAS INSTA TI tps71701dckrg4 1
......
POWER AND GROUND LIST - 1 POWER AND GROUND LIST - 1
DESIGNATOR PART TYPE GND GND_SIGNAL P3V3 P3V3A VCC VDD_SI57X DESIGNATOR PART TYPE GND_SIGNAL P3V3 P3V3A VDD_SI57X
IC1 AD5662BRMZ-1-GND=GND_SIGNAL,VDA 8 1 IC1 AD5662BRMZ-1-GND=GND_SIGNAL,VDA 8 1
IC2 DS92001TMA-GND=GND_SIGNAL,VCC=A 1 5 IC2 DS92001TMA-GND=GND_SIGNAL,VCC=A 1 5
IC3 DS92001TMA-GND=GND_SIGNAL,VCC=A 1 5 IC3 DS92001TMA-GND=GND_SIGNAL,VCC=A 1 5
IC5 DS90LV001TM-GND=GND_SIGNAL,VCCA 1 5 IC5 DS90LV001TM-GND=GND_SIGNAL,VCCA 1 5
IC6 DS90LV001TM-GND=GND_SIGNAL,VCCA 1 5 IC6 DS90LV001TM-GND=GND_SIGNAL,VCCA 1 5
IC7 DS90LV001TM-GND=GND_SIGNAL,VCCA 1 5 IC7 DS90LV001TM-GND=GND_SIGNAL,VCCA 1 5
IC9 AD5662BRMZ-1-GND=GND_SIGNAL,VDA 8 1 IC9 AD5662BRMZ-1-GND=GND_SIGNAL,VDA 8 1
IC16 SN74LVC1G06DBVT 3 5 IC16 SN74LVC1G06DBVT-GND=GND_SIGNALA 3 5
IC22 S25FL128SAGMFIR01-VCC=P3V3,VSSA 10 2 IC22 S25FL128SAGMFIR01-VCC=P3V3,VSSA 10 2
J1 CON150P-QTS75_03FDA-P1=GND_SIGA 151 J1 CON150P-QTS75_03FDA-P1=GND_SIGA 151
152 152
153 153
154 154
155 155
156 156
157 157
158 158
159 159
160 160
161 161
162 162
QZ1 570CAC000121DG-GND=GND_SIGNAL,A 3 6 QZ1 570CAC000121DG-GND=GND_SIGNAL,A 3 6
QZ2 OSC_6P_VCTRL_ENDIS_OUT_124-CFPB 3 6 QZ2 OSC_6P_VCTRL_ENDIS_OUT_124-CFPB 3 6
RG1 LT3070EUFD#PBF-GND=GND_SIGNAL 4 RG1 LT3070EUFD#PBF-GND=GND_SIGNAL 4
9 9
10 10
11 11
12 12
13 13
14 14
20 20
26 26
29 29
SFP1 SFP_CAGE-6367034-1 1 SFP1 SFP_CAGE-6367034-1-GND=GND_SIGA 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
11 11
12 12
13 13
14 14
15 15
16 16
17 17
SFP2 SFP_CAGE-6367035-1 1 SFP2 SFP_CAGE-6367035-1-GND=GND_SIGA 1
2 2
3 3
SFP3 SFP_CAGE-6367034-1 1 SFP3 SFP_CAGE-6367034-1-GND=GND_SIGA 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
11 11
12 12
13 13
14 14
15 15
16 16
17 17
SFP4 SFP_CAGE-6367035-1 1 SFP4 SFP_CAGE-6367035-1-GND=GND_SIGA 1
2 2
3 3
END POWER AND GROUND LIST END POWER AND GROUND LIST
...@@ -21,8 +21,8 @@ IC7 DS90LV001TM-GND=GND_SIGNAL,VCCA ...@@ -21,8 +21,8 @@ IC7 DS90LV001TM-GND=GND_SIGNAL,VCCA
IC9 AD5662BRMZ-1-GND=GND_SIGNAL,VDA IC9 AD5662BRMZ-1-GND=GND_SIGNAL,VDA
GND_SIGNAL P3V3A GND_SIGNAL P3V3A
8 1 8 1
IC16 SN74LVC1G06DBVT IC16 SN74LVC1G06DBVT-GND=GND_SIGNALA
GND VCC GND_SIGNAL P3V3
3 5 3 5
IC22 S25FL128SAGMFIR01-VCC=P3V3,VSSA IC22 S25FL128SAGMFIR01-VCC=P3V3,VSSA
GND_SIGNAL P3V3 GND_SIGNAL P3V3
...@@ -59,8 +59,8 @@ RG1 LT3070EUFD#PBF-GND=GND_SIGNAL ...@@ -59,8 +59,8 @@ RG1 LT3070EUFD#PBF-GND=GND_SIGNAL
20 20
26 26
29 29
SFP1 SFP_CAGE-6367034-1 SFP1 SFP_CAGE-6367034-1-GND=GND_SIGA
GND GND_SIGNAL
1 1
2 2
3 3
...@@ -78,13 +78,13 @@ SFP1 SFP_CAGE-6367034-1 ...@@ -78,13 +78,13 @@ SFP1 SFP_CAGE-6367034-1
15 15
16 16
17 17
SFP2 SFP_CAGE-6367035-1 SFP2 SFP_CAGE-6367035-1-GND=GND_SIGA
GND GND_SIGNAL
1 1
2 2
3 3
SFP3 SFP_CAGE-6367034-1 SFP3 SFP_CAGE-6367034-1-GND=GND_SIGA
GND GND_SIGNAL
1 1
2 2
3 3
...@@ -102,8 +102,8 @@ SFP3 SFP_CAGE-6367034-1 ...@@ -102,8 +102,8 @@ SFP3 SFP_CAGE-6367034-1
15 15
16 16
17 17
SFP4 SFP_CAGE-6367035-1 SFP4 SFP_CAGE-6367035-1-GND=GND_SIGA
GND GND_SIGNAL
1 1
2 2
3 3
......
...@@ -751,13 +751,13 @@ S25FL128SAGMFIR01-VCC=P3V3,VSSA S25FL128SAGMFIR01 IC22 ...@@ -751,13 +751,13 @@ S25FL128SAGMFIR01-VCC=P3V3,VSSA S25FL128SAGMFIR01 IC22
---------------- ----------------
SFP_CAGE-6367034-1 6367034-1 SFP1 SFP_CAGE-6367034-1-GND=GND_SIGA 6367034-1 SFP1
SFP_CAGE-6367034-1 6367034-1 SFP3 SFP_CAGE-6367034-1-GND=GND_SIGA 6367034-1 SFP3
---------------- ----------------
SFP_CAGE-6367035-1 6367035-1 SFP2 SFP_CAGE-6367035-1-GND=GND_SIGA 6367035-1 SFP2
SFP_CAGE-6367035-1 6367035-1 SFP4 SFP_CAGE-6367035-1-GND=GND_SIGA 6367035-1 SFP4
---------------- ----------------
...@@ -770,7 +770,7 @@ SN65LVDS1_SOT23-5-TEXAS INSTRUA snlvds1dbv U5 ...@@ -770,7 +770,7 @@ SN65LVDS1_SOT23-5-TEXAS INSTRUA snlvds1dbv U5
---------------- ----------------
SN74LVC1G06DBVT SN74LVC1G06DBVT IC16 SN74LVC1G06DBVT-GND=GND_SIGNALA SN74LVC1G06DBVT IC16
---------------- ----------------
......
Starting to read /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/pstchip.dat Starting to read /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/pstchip.dat
Finished reading /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/pstchip.dat (00:00:00.11) Finished reading /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/pstchip.dat (00:00:00.10)
Starting to read /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/pstxprt.dat Starting to read /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/pstxprt.dat
Finished reading /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/pstxprt.dat (00:00:00.02) Finished reading /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/pstxprt.dat (00:00:00.02)
Starting to read /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/pstxnet.dat Starting to read /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/pstxnet.dat
...@@ -13,15 +13,15 @@ Starting to generate /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/tr ...@@ -13,15 +13,15 @@ Starting to generate /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/tr
Starting to generate /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialstf.dat Starting to generate /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialstf.dat
Finished generating /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialstf.dat (00:00:00.04) Finished generating /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialstf.dat (00:00:00.04)
Starting to generate /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialpgnd.dat Starting to generate /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialpgnd.dat
Finished generating /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialpgnd.dat (00:00:00.03) Finished generating /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialpgnd.dat (00:00:00.04)
Starting to generate /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialpgnd_new.dat Starting to generate /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialpgnd_new.dat
Finished generating /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialpgnd_new.dat (00:00:00.04) Finished generating /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/dialpgnd_new.dat (00:00:00.04)
Starting to generate /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/scald.xref Starting to generate /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/scald.xref
Finished generating /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/scald.xref (00:00:00.05) Finished generating /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_toplevel/packaged/scald.xref (00:00:00.05)
SCALD Lists Interface run on Jul 29 17:21:32 2014 SCALD Lists Interface run on Mar 23 15:08:32 2015
DESIGN NAME : 'PC049A_TOPLEVEL' DESIGN NAME : 'PC049A_TOPLEVEL'
PACKAGING ON 29-Jul-2014 AT 17:05:48 PACKAGING ON 06-Oct-2014 AT 12:40:31
DIRECTORIES <none> DIRECTORIES <none>
LIBRARIES 'uob_hep_pc049a_lib' 'bris_cds_analogue' 'bris_cds_connectors' LIBRARIES 'uob_hep_pc049a_lib' 'bris_cds_analogue' 'bris_cds_connectors'
......
FILE_TYPE=CROSS_REFERENCE; FILE_TYPE=CROSS_REFERENCE;
ROOT_DRAWING='PC049A_TOPLEVEL'; ROOT_DRAWING='PC049A_TOPLEVEL';
RUN_TIME='Jul 29 17:21:32 2014'; RUN_TIME='Mar 23 15:08:32 2015';
PROGRAM_VERSION='15.50-p001'; PROGRAM_VERSION='15.50-p001';
**** Part Type '1-HOLE_0-8' ('1-HOLE_0-8-BASE') **** **** Part Type '1-HOLE_0-8' ('1-HOLE_0-8-BASE') ****
**** Part Type '24AA64_DFN' ('24AA64T-I/MC') **** **** Part Type '24AA64_DFN' ('24AA64T-I/MC') ****
...@@ -78,8 +78,8 @@ CAPCERSMDCL2_0402 I71 C2_1 [CAPCERSMDCL2_0402-100NF,16V_GEN] ...@@ -78,8 +78,8 @@ CAPCERSMDCL2_0402 I71 C2_1 [CAPCERSMDCL2_0402-100NF,16V_GEN]
1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL 1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL
CAPCERSMDCL2_0402 I59 C3 [CAPCERSMDCL2_0402-1UF,16V] CAPCERSMDCL2_0402 I59 C3 [CAPCERSMDCL2_0402-1UF,16V]
2 P3V3 B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):P3V3
1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL 1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL
2 AVDD B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):AVDD
CAPCERSMDCL2_0402 I34 C3_1 [CAPCERSMDCL2_0402-100NF,16V_GEN] CAPCERSMDCL2_0402 I34 C3_1 [CAPCERSMDCL2_0402-100NF,16V_GEN]
2 VDD_DAC_1 B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):PAGE1_I3@UOB_HEP_PC049A_LIB.PC043C_SINGLE_MAROC(SCH_1):VDD_DAC 2 VDD_DAC_1 B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):PAGE1_I3@UOB_HEP_PC049A_LIB.PC043C_SINGLE_MAROC(SCH_1):VDD_DAC
...@@ -686,11 +686,11 @@ CAPCERSMDCL2_0805 I81 C104 [CAPCERSMDCL2_0805-22UF,6.3V] ...@@ -686,11 +686,11 @@ CAPCERSMDCL2_0805 I81 C104 [CAPCERSMDCL2_0805-22UF,6.3V]
1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL 1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL
CAPCERSMDCL2_0402 I77 C105 [CAPCERSMDCL2_0402-100NF,16V_GEN] CAPCERSMDCL2_0402 I77 C105 [CAPCERSMDCL2_0402-100NF,16V_GEN]
2 UNNAMED_7_CAPCERSMDCL2_I74_B B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_7_CAPCERSMDCL2_I74_B 2 MGT_AVCC_A B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):MGT_AVCC_A
1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL 1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL
CAPCERSMDCL2_0402 I70 C106 [CAPCERSMDCL2_0402-100NF,16V_GEN] CAPCERSMDCL2_0402 I70 C106 [CAPCERSMDCL2_0402-100NF,16V_GEN]
2 UNNAMED_7_CAPCERSMDCL2_I70_B B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_7_CAPCERSMDCL2_I70_B 2 MGT_AVCC_A B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):MGT_AVCC_A
1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL 1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL
CAPCERSMDCL2_0402 I80 C107 [CAPCERSMDCL2_0402-1UF,16V] CAPCERSMDCL2_0402 I80 C107 [CAPCERSMDCL2_0402-1UF,16V]
...@@ -698,11 +698,11 @@ CAPCERSMDCL2_0402 I80 C107 [CAPCERSMDCL2_0402-1UF,16V] ...@@ -698,11 +698,11 @@ CAPCERSMDCL2_0402 I80 C107 [CAPCERSMDCL2_0402-1UF,16V]
1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL 1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL
CAPCERSMDCL2_0402 I76 C108 [CAPCERSMDCL2_0402-100NF,16V_GEN] CAPCERSMDCL2_0402 I76 C108 [CAPCERSMDCL2_0402-100NF,16V_GEN]
2 UNNAMED_7_CAPCERSMDCL2_I74_B B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_7_CAPCERSMDCL2_I74_B 2 MGT_AVCC_A B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):MGT_AVCC_A
1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL 1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL
CAPCERSMDCL2_0402 I73 C109 [CAPCERSMDCL2_0402-100NF,16V_GEN] CAPCERSMDCL2_0402 I73 C109 [CAPCERSMDCL2_0402-100NF,16V_GEN]
2 UNNAMED_7_CAPCERSMDCL2_I70_B B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_7_CAPCERSMDCL2_I70_B 2 MGT_AVCC_A B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):MGT_AVCC_A
1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL 1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL
CAPCERSMDCL2_0402 I79 C110 [CAPCERSMDCL2_0402-1UF,16V] CAPCERSMDCL2_0402 I79 C110 [CAPCERSMDCL2_0402-1UF,16V]
...@@ -710,19 +710,19 @@ CAPCERSMDCL2_0402 I79 C110 [CAPCERSMDCL2_0402-1UF,16V] ...@@ -710,19 +710,19 @@ CAPCERSMDCL2_0402 I79 C110 [CAPCERSMDCL2_0402-1UF,16V]
1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL 1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL
CAPCERSMDCL2_0402 I75 C111 [CAPCERSMDCL2_0402-100NF,16V_GEN] CAPCERSMDCL2_0402 I75 C111 [CAPCERSMDCL2_0402-100NF,16V_GEN]
2 UNNAMED_7_CAPCERSMDCL2_I74_B B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_7_CAPCERSMDCL2_I74_B 2 MGT_AVCC_A B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):MGT_AVCC_A
1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL 1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL
CAPCERSMDCL2_0402 I72 C112 [CAPCERSMDCL2_0402-100NF,16V_GEN] CAPCERSMDCL2_0402 I72 C112 [CAPCERSMDCL2_0402-100NF,16V_GEN]
2 UNNAMED_7_CAPCERSMDCL2_I70_B B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_7_CAPCERSMDCL2_I70_B 2 MGT_AVCC_A B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):MGT_AVCC_A
1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL 1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL
CAPCERSMDCL2_0402 I74 C113 [CAPCERSMDCL2_0402-100NF,16V_GEN] CAPCERSMDCL2_0402 I74 C113 [CAPCERSMDCL2_0402-100NF,16V_GEN]
2 UNNAMED_7_CAPCERSMDCL2_I74_B B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_7_CAPCERSMDCL2_I74_B 2 MGT_AVCC_A B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):MGT_AVCC_A
1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL 1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL
CAPCERSMDCL2_0402 I71 C114 [CAPCERSMDCL2_0402-100NF,16V_GEN] CAPCERSMDCL2_0402 I71 C114 [CAPCERSMDCL2_0402-100NF,16V_GEN]
2 UNNAMED_7_CAPCERSMDCL2_I70_B B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_7_CAPCERSMDCL2_I70_B 2 MGT_AVCC_A B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):MGT_AVCC_A
1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL 1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL
CAPCERSMDCL2_1206 I20 C115 [CAPCERSMDCL2_1206-100UF_X5R,6.A] CAPCERSMDCL2_1206 I20 C115 [CAPCERSMDCL2_1206-100UF_X5R,6.A]
...@@ -1416,7 +1416,7 @@ LTM4606_LGA I72 IC14 [LTM4606EV#PBF] ...@@ -1416,7 +1416,7 @@ LTM4606_LGA I72 IC14 [LTM4606EV#PBF]
5 FPGA_SDA SDA @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_SDA 5 FPGA_SDA SDA @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_SDA
6 FPGA_SCL SCL @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_SCL 6 FPGA_SCL SCL @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_SCL
74LVC1G06_SOT23 I92 IC16 [SN74LVC1G06DBVT] 74LVC1G06_SOT23 I92 IC16 [SN74LVC1G06DBVT-GND=GND_SIGNALA]
4 UNNAMED_13_LED_I46_K Y @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_13_LED_I46_K 4 UNNAMED_13_LED_I46_K Y @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_13_LED_I46_K
2 FPGA_DONE A @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_DONE 2 FPGA_DONE A @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_DONE
...@@ -2757,36 +2757,36 @@ LM2937IMP_SOT223 I253 RG1_1 [LM2937IMP_SOT223-2.5V,TI] ...@@ -2757,36 +2757,36 @@ LM2937IMP_SOT223 I253 RG1_1 [LM2937IMP_SOT223-2.5V,TI]
1 AVDD PINPUT @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):AVDD 1 AVDD PINPUT @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):AVDD
R4ISMD_1206 I49 RN1 [R4ISMD_1206-150] R4ISMD_1206 I49 RN1 [R4ISMD_1206-150]
8 UNNAMED_8_CON12P_I51_A_1 B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_1 1 UNNAMED_8_CON12P_I51_A_1 A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_1
1 FPGA_GPIO<3> A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<3> 8 FPGA_GPIO<3> B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<3>
R4ISMD_1206 I49 RN1 [R4ISMD_1206-150] R4ISMD_1206 I49 RN1 [R4ISMD_1206-150]
7 UNNAMED_8_CON12P_I51_A_2 B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_2 2 UNNAMED_8_CON12P_I51_A_2 A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_2
2 FPGA_GPIO<2> A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<2> 7 FPGA_GPIO<2> B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<2>
R4ISMD_1206 I49 RN1 [R4ISMD_1206-150] R4ISMD_1206 I49 RN1 [R4ISMD_1206-150]
6 UNNAMED_8_CON12P_I51_A_3 B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_3 3 UNNAMED_8_CON12P_I51_A_3 A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_3
3 FPGA_GPIO<1> A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<1> 6 FPGA_GPIO<1> B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<1>
R4ISMD_1206 I49 RN1 [R4ISMD_1206-150] R4ISMD_1206 I49 RN1 [R4ISMD_1206-150]
5 UNNAMED_8_CON12P_I51_A_4 B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_4 4 UNNAMED_8_CON12P_I51_A_4 A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_4
4 FPGA_GPIO<0> A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<0> 5 FPGA_GPIO<0> B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<0>
R4ISMD_1206 I50 RN2 [R4ISMD_1206-150] R4ISMD_1206 I50 RN2 [R4ISMD_1206-150]
1 UNNAMED_8_CON12P_I51_A A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A 8 UNNAMED_8_CON12P_I51_A B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A
8 FPGA_GPIO<7> B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<7> 1 FPGA_GPIO<7> A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<7>
R4ISMD_1206 I50 RN2 [R4ISMD_1206-150] R4ISMD_1206 I50 RN2 [R4ISMD_1206-150]
2 UNNAMED_8_CON12P_I51_A_7 A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_7 7 UNNAMED_8_CON12P_I51_A_7 B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_7
7 FPGA_GPIO<6> B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<6> 2 FPGA_GPIO<6> A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<6>
R4ISMD_1206 I50 RN2 [R4ISMD_1206-150] R4ISMD_1206 I50 RN2 [R4ISMD_1206-150]
3 UNNAMED_8_CON12P_I51_A_5 A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_5 6 UNNAMED_8_CON12P_I51_A_5 B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_5
6 FPGA_GPIO<5> B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<5> 3 FPGA_GPIO<5> A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<5>
R4ISMD_1206 I50 RN2 [R4ISMD_1206-150] R4ISMD_1206 I50 RN2 [R4ISMD_1206-150]
4 UNNAMED_8_CON12P_I51_A_6 A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_6 5 UNNAMED_8_CON12P_I51_A_6 B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_6
5 FPGA_GPIO<4> B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<4> 4 FPGA_GPIO<4> A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<4>
R4ISMD_1206 I91 RZ1 [R4ISMD_1206-150] R4ISMD_1206 I91 RZ1 [R4ISMD_1206-150]
8 UNNAMED_8_LED_I105_K B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_LED_I105_K 8 UNNAMED_8_LED_I105_K B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_LED_I105_K
...@@ -2805,31 +2805,31 @@ R4ISMD_1206 I91 RZ1 [R4ISMD_1206-150] ...@@ -2805,31 +2805,31 @@ R4ISMD_1206 I91 RZ1 [R4ISMD_1206-150]
4 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL 4 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL
R4ISMD_1206 I90 RZ2 [R4ISMD_1206-4.7K] R4ISMD_1206 I90 RZ2 [R4ISMD_1206-4.7K]
1 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL 8 GND_SIGNAL B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL
8 DIP_SWITCH<3> B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):DIP_SWITCH<3> 1 DIP_SWITCH<3> A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):DIP_SWITCH<3>
R4ISMD_1206 I90 RZ2 [R4ISMD_1206-4.7K] R4ISMD_1206 I90 RZ2 [R4ISMD_1206-4.7K]
2 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL 7 GND_SIGNAL B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL
7 DIP_SWITCH<2> B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):DIP_SWITCH<2> 2 DIP_SWITCH<2> A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):DIP_SWITCH<2>
R4ISMD_1206 I90 RZ2 [R4ISMD_1206-4.7K] R4ISMD_1206 I90 RZ2 [R4ISMD_1206-4.7K]
3 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL 6 GND_SIGNAL B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL
6 DIP_SWITCH<1> B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):DIP_SWITCH<1> 3 DIP_SWITCH<1> A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):DIP_SWITCH<1>
R4ISMD_1206 I90 RZ2 [R4ISMD_1206-4.7K] R4ISMD_1206 I90 RZ2 [R4ISMD_1206-4.7K]
4 GND_SIGNAL A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL 5 GND_SIGNAL B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL
5 DIP_SWITCH<0> B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):DIP_SWITCH<0> 4 DIP_SWITCH<0> A<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):DIP_SWITCH<0>
SFP_CAGE I85 SFP1 [SFP_CAGE-6367034-1] SFP_CAGE I85 SFP1 [SFP_CAGE-6367034-1-GND=GND_SIGA]
NC NC NC NC NC NC NC NC
SFP_CAGE I86 SFP2 [SFP_CAGE-6367035-1] SFP_CAGE I86 SFP2 [SFP_CAGE-6367035-1-GND=GND_SIGA]
NC NC NC NC NC NC NC NC
SFP_CAGE I87 SFP3 [SFP_CAGE-6367034-1] SFP_CAGE I87 SFP3 [SFP_CAGE-6367034-1-GND=GND_SIGA]
NC NC NC NC NC NC NC NC
SFP_CAGE I88 SFP4 [SFP_CAGE-6367035-1] SFP_CAGE I88 SFP4 [SFP_CAGE-6367035-1-GND=GND_SIGA]
NC NC NC NC NC NC NC NC
SW_PUSHBUTTON_1SPSTA_4P_1 I86 SW1 [SW_PUSHBUTTON_1SPSTA_4P_1-OMROA] SW_PUSHBUTTON_1SPSTA_4P_1 I86 SW1 [SW_PUSHBUTTON_1SPSTA_4P_1-OMROA]
...@@ -3122,8 +3122,8 @@ AD8031_SOT23-5 I70 U2 [AD8031_SOT23-5-AD] ...@@ -3122,8 +3122,8 @@ AD8031_SOT23-5 I70 U2 [AD8031_SOT23-5-AD]
1 UNNAMED_8_AD8031_I70_IN OUT @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_AD8031_I70_IN 1 UNNAMED_8_AD8031_I70_IN OUT @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_AD8031_I70_IN
4 UNNAMED_8_AD8031_I70_IN IN* @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_AD8031_I70_IN 4 UNNAMED_8_AD8031_I70_IN IN* @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_AD8031_I70_IN
3 UNBUF_CTEST IN @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNBUF_CTEST 3 UNBUF_CTEST IN @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNBUF_CTEST
5 P3V3 VSPLUS @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):P3V3
2 GND_SIGNAL VSMIN @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL 2 GND_SIGNAL VSMIN @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL
5 AVDD VSPLUS @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):AVDD
PC049A_FPGA I50 U3 [] PC049A_FPGA I50 U3 []
W17 LVDS_OTRIG_TO_FPGA_P LVDS_OTRIG_TO_FPGA_P_I @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):LVDS_OTRIG_TO_FPGA_P W17 LVDS_OTRIG_TO_FPGA_P LVDS_OTRIG_TO_FPGA_P_I @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):LVDS_OTRIG_TO_FPGA_P
...@@ -3142,8 +3142,8 @@ PC049A_FPGA I50 U3 [] ...@@ -3142,8 +3142,8 @@ PC049A_FPGA I50 U3 []
T1 ENABLE_GCLK_DRIVE ENABLE_GCLK_DRIVE_O @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):ENABLE_GCLK_DRIVE T1 ENABLE_GCLK_DRIVE ENABLE_GCLK_DRIVE_O @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):ENABLE_GCLK_DRIVE
PC049A_FPGA I55 U3 [] PC049A_FPGA I55 U3 []
H6 P3V3 BUTTON2_I @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):P3V3 H6 UNNAMED_8_RSMD0603_I97_B BUTTON2_I @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_RSMD0603_I97_B
H5 P3V3 BUTTON1_I @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):P3V3 H5 UNNAMED_8_RSMD0603_I92_B BUTTON1_I @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_RSMD0603_I92_B
T5 ONE_WIRE ONE_WIRE_B @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):ONE_WIRE T5 ONE_WIRE ONE_WIRE_B @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):ONE_WIRE
T4 FPGA_SDA FPGA_SDA_B @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_SDA T4 FPGA_SDA FPGA_SDA_B @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_SDA
T3 FPGA_SCL FPGA_SCL_B @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_SCL T3 FPGA_SCL FPGA_SCL_B @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_SCL
...@@ -3843,7 +3843,6 @@ ANALOG_TO_MAROC<63> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):ANALOG_TO_MAROC ...@@ -3843,7 +3843,6 @@ ANALOG_TO_MAROC<63> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):ANALOG_TO_MAROC
AVDD @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):AVDD AVDD @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):AVDD
C29_1 2 B<0> CAPCERSMDCL2_0402 I140 C29_1 2 B<0> CAPCERSMDCL2_0402 I140
C3 2 B<0> CAPCERSMDCL2_0402 I59
C54_1 2 B<0> CAPCERSMDCL2_0603 I242 C54_1 2 B<0> CAPCERSMDCL2_0603 I242
C98 2 B<0> CAPCERSMDCL2_0805 I85 C98 2 B<0> CAPCERSMDCL2_0805 I85
IC21 3 OUT LP38692_SOT223 I115 IC21 3 OUT LP38692_SOT223 I115
...@@ -3880,7 +3879,6 @@ AVDD @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):AVDD ...@@ -3880,7 +3879,6 @@ AVDD @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):AVDD
R8_1 2 B<0> RSMD0402_1/16W I25 R8_1 2 B<0> RSMD0402_1/16W I25
R9_1 2 B<0> RSMD0402_1/16W I51 R9_1 2 B<0> RSMD0402_1/16W I51
RG1_1 1 PINPUT LM2937IMP_SOT223 I253 RG1_1 1 PINPUT LM2937IMP_SOT223 I253
U2 5 VSPLUS AD8031_SOT23-5 I70
CKB_40M @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):CKB_40M CKB_40M @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):CKB_40M
J3_1 3 A<2> CON3P I228 J3_1 3 A<2> CON3P I228
...@@ -4135,22 +4133,22 @@ DIG_CTEST<5> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):DIG_CTEST<5> ...@@ -4135,22 +4133,22 @@ DIG_CTEST<5> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):DIG_CTEST<5>
U3 E4 CTEST_O<5> PC049A_FPGA I55 U3 E4 CTEST_O<5> PC049A_FPGA I55
DIP_SWITCH<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):DIP_SWITCH<0> DIP_SWITCH<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):DIP_SWITCH<0>
RZ2 5 B<0> R4ISMD_1206 I90 RZ2 4 A<0> R4ISMD_1206 I90
SW3 8 B<0> SW4INT I88 SW3 8 B<0> SW4INT I88
U3 J6 DIP_SWITCH_I<0> PC049A_FPGA I55 U3 J6 DIP_SWITCH_I<0> PC049A_FPGA I55
DIP_SWITCH<1> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):DIP_SWITCH<1> DIP_SWITCH<1> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):DIP_SWITCH<1>
RZ2 6 B<0> R4ISMD_1206 I90 RZ2 3 A<0> R4ISMD_1206 I90
SW3 6 B<0> SW4INT I88 SW3 6 B<0> SW4INT I88
U3 J4 DIP_SWITCH_I<1> PC049A_FPGA I55 U3 J4 DIP_SWITCH_I<1> PC049A_FPGA I55
DIP_SWITCH<2> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):DIP_SWITCH<2> DIP_SWITCH<2> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):DIP_SWITCH<2>
RZ2 7 B<0> R4ISMD_1206 I90 RZ2 2 A<0> R4ISMD_1206 I90
SW3 4 B<0> SW4INT I88 SW3 4 B<0> SW4INT I88
U3 J3 DIP_SWITCH_I<2> PC049A_FPGA I55 U3 J3 DIP_SWITCH_I<2> PC049A_FPGA I55
DIP_SWITCH<3> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):DIP_SWITCH<3> DIP_SWITCH<3> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):DIP_SWITCH<3>
RZ2 8 B<0> R4ISMD_1206 I90 RZ2 1 A<0> R4ISMD_1206 I90
SW3 2 B<0> SW4INT I88 SW3 2 B<0> SW4INT I88
U3 K1 DIP_SWITCH_I<3> PC049A_FPGA I55 U3 K1 DIP_SWITCH_I<3> PC049A_FPGA I55
...@@ -4183,35 +4181,35 @@ FPGA_DONE @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_DONE ...@@ -4183,35 +4181,35 @@ FPGA_DONE @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_DONE
U3 AB21 DONE_2 PC049A_FPGA I56 U3 AB21 DONE_2 PC049A_FPGA I56
FPGA_GPIO<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<0> FPGA_GPIO<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<0>
RN1 4 A<0> R4ISMD_1206 I49 RN1 5 B<0> R4ISMD_1206 I49
U3 G4 GPIO<0> PC049A_FPGA I55 U3 G4 GPIO<0> PC049A_FPGA I55
FPGA_GPIO<1> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<1> FPGA_GPIO<1> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<1>
RN1 3 A<0> R4ISMD_1206 I49 RN1 6 B<0> R4ISMD_1206 I49
U3 G3 GPIO<1> PC049A_FPGA I55 U3 G3 GPIO<1> PC049A_FPGA I55
FPGA_GPIO<2> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<2> FPGA_GPIO<2> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<2>
RN1 2 A<0> R4ISMD_1206 I49 RN1 7 B<0> R4ISMD_1206 I49
U3 G1 GPIO<2> PC049A_FPGA I55 U3 G1 GPIO<2> PC049A_FPGA I55
FPGA_GPIO<3> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<3> FPGA_GPIO<3> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<3>
RN1 1 A<0> R4ISMD_1206 I49 RN1 8 B<0> R4ISMD_1206 I49
U3 G6 GPIO<3> PC049A_FPGA I55 U3 G6 GPIO<3> PC049A_FPGA I55
FPGA_GPIO<4> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<4> FPGA_GPIO<4> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<4>
RN2 5 B<0> R4ISMD_1206 I50 RN2 4 A<0> R4ISMD_1206 I50
U3 F3 GPIO<4> PC049A_FPGA I55 U3 F3 GPIO<4> PC049A_FPGA I55
FPGA_GPIO<5> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<5> FPGA_GPIO<5> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<5>
RN2 6 B<0> R4ISMD_1206 I50 RN2 3 A<0> R4ISMD_1206 I50
U3 F2 GPIO<5> PC049A_FPGA I55 U3 F2 GPIO<5> PC049A_FPGA I55
FPGA_GPIO<6> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<6> FPGA_GPIO<6> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<6>
RN2 7 B<0> R4ISMD_1206 I50 RN2 2 A<0> R4ISMD_1206 I50
U3 F1 GPIO<6> PC049A_FPGA I55 U3 F1 GPIO<6> PC049A_FPGA I55
FPGA_GPIO<7> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<7> FPGA_GPIO<7> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_GPIO<7>
RN2 8 B<0> R4ISMD_1206 I50 RN2 1 A<0> R4ISMD_1206 I50
U3 F5 GPIO<7> PC049A_FPGA I55 U3 F5 GPIO<7> PC049A_FPGA I55
FPGA_LEDS<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_LEDS<0> FPGA_LEDS<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):FPGA_LEDS<0>
...@@ -4713,10 +4711,10 @@ GND_SIGNAL @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL ...@@ -4713,10 +4711,10 @@ GND_SIGNAL @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):GND_SIGNAL
RZ1 2 A<0> R4ISMD_1206 I91 RZ1 2 A<0> R4ISMD_1206 I91
RZ1 3 A<0> R4ISMD_1206 I91 RZ1 3 A<0> R4ISMD_1206 I91
RZ1 4 A<0> R4ISMD_1206 I91 RZ1 4 A<0> R4ISMD_1206 I91
RZ2 1 A<0> R4ISMD_1206 I90 RZ2 5 B<0> R4ISMD_1206 I90
RZ2 2 A<0> R4ISMD_1206 I90 RZ2 6 B<0> R4ISMD_1206 I90
RZ2 3 A<0> R4ISMD_1206 I90 RZ2 7 B<0> R4ISMD_1206 I90
RZ2 4 A<0> R4ISMD_1206 I90 RZ2 8 B<0> R4ISMD_1206 I90
SW4 1 A SW_PUSHBUTTON_1SPSTA_4P_1 I80 SW4 1 A SW_PUSHBUTTON_1SPSTA_4P_1 I80
SW4 3 C SW_PUSHBUTTON_1SPSTA_4P_1 I80 SW4 3 C SW_PUSHBUTTON_1SPSTA_4P_1 I80
U1 2 GND OSC_VCXO_4P_OSC_4PIN_53S I61 U1 2 GND OSC_VCXO_4P_OSC_4PIN_53S I61
...@@ -5230,8 +5228,16 @@ LVPECL_OTRIG_OUT_P @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):LVPECL_OTRIG_OUT ...@@ -5230,8 +5228,16 @@ LVPECL_OTRIG_OUT_P @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):LVPECL_OTRIG_OUT
MGT_AVCC_A @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):MGT_AVCC_A MGT_AVCC_A @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):MGT_AVCC_A
C104 2 B<0> CAPCERSMDCL2_0805 I81 C104 2 B<0> CAPCERSMDCL2_0805 I81
C105 2 B<0> CAPCERSMDCL2_0402 I77
C106 2 B<0> CAPCERSMDCL2_0402 I70
C107 2 B<0> CAPCERSMDCL2_0402 I80 C107 2 B<0> CAPCERSMDCL2_0402 I80
C108 2 B<0> CAPCERSMDCL2_0402 I76
C109 2 B<0> CAPCERSMDCL2_0402 I73
C110 2 B<0> CAPCERSMDCL2_0402 I79 C110 2 B<0> CAPCERSMDCL2_0402 I79
C111 2 B<0> CAPCERSMDCL2_0402 I75
C112 2 B<0> CAPCERSMDCL2_0402 I72
C113 2 B<0> CAPCERSMDCL2_0402 I74
C114 2 B<0> CAPCERSMDCL2_0402 I71
L9 1 A<0> FERRITE I84 L9 1 A<0> FERRITE I84
R53 2 B<0> RSMD0603_1/10W I55 R53 2 B<0> RSMD0603_1/10W I55
U3 A7 MGTAVTTTX_101 PC049A_FPGA I38 U3 A7 MGTAVTTTX_101 PC049A_FPGA I38
...@@ -5614,6 +5620,7 @@ P2V5 @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):P2V5 ...@@ -5614,6 +5620,7 @@ P2V5 @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):P2V5
P3V3 @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):P3V3 P3V3 @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):P3V3
C1 2 B<0> CAPCERSMDCL2_0402 I15 C1 2 B<0> CAPCERSMDCL2_0402 I15
C2 2 B<0> CAPCERSMDCL2_0402 I25 C2 2 B<0> CAPCERSMDCL2_0402 I25
C3 2 B<0> CAPCERSMDCL2_0402 I59
C4 2 B<0> CAPCERSMDCL2_0402 I18 C4 2 B<0> CAPCERSMDCL2_0402 I18
C5 2 B<0> CAPCERSMDCL2_0402 I28 C5 2 B<0> CAPCERSMDCL2_0402 I28
C6 2 B<0> CAPCERSMDCL2_0402 I48 C6 2 B<0> CAPCERSMDCL2_0402 I48
...@@ -5667,11 +5674,10 @@ P3V3 @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):P3V3 ...@@ -5667,11 +5674,10 @@ P3V3 @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):P3V3
SW3 3 A<0> SW4INT I88 SW3 3 A<0> SW4INT I88
SW3 5 A<0> SW4INT I88 SW3 5 A<0> SW4INT I88
SW3 7 A<0> SW4INT I88 SW3 7 A<0> SW4INT I88
U2 5 VSPLUS AD8031_SOT23-5 I70
U3 C2 VCCO_3<0> PC049A_FPGA I1 U3 C2 VCCO_3<0> PC049A_FPGA I1
U3 F4 VCCO_3<1> PC049A_FPGA I1 U3 F4 VCCO_3<1> PC049A_FPGA I1
U3 G2 VCCO_3<2> PC049A_FPGA I1 U3 G2 VCCO_3<2> PC049A_FPGA I1
U3 H5 BUTTON1_I PC049A_FPGA I55
U3 H6 BUTTON2_I PC049A_FPGA I55
U3 J5 VCCO_3<3> PC049A_FPGA I1 U3 J5 VCCO_3<3> PC049A_FPGA I1
U3 L2 VCCO_3<4> PC049A_FPGA I1 U3 L2 VCCO_3<4> PC049A_FPGA I1
U3 L7 VCCO_3<5> PC049A_FPGA I1 U3 L7 VCCO_3<5> PC049A_FPGA I1
...@@ -6590,18 +6596,6 @@ UNNAMED_7_CAPCERSMDCL2_I5_A @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED ...@@ -6590,18 +6596,6 @@ UNNAMED_7_CAPCERSMDCL2_I5_A @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED
C20 1 A<0> CAPCERSMDCL2_0402 I5 C20 1 A<0> CAPCERSMDCL2_0402 I5
J5 5 A<4> SK_SATA_SMD_STR I4 J5 5 A<4> SK_SATA_SMD_STR I4
UNNAMED_7_CAPCERSMDCL2_I70_B @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_7_CAPCERSMDCL2_I70_B
C106 2 B<0> CAPCERSMDCL2_0402 I70
C109 2 B<0> CAPCERSMDCL2_0402 I73
C112 2 B<0> CAPCERSMDCL2_0402 I72
C114 2 B<0> CAPCERSMDCL2_0402 I71
UNNAMED_7_CAPCERSMDCL2_I74_B @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_7_CAPCERSMDCL2_I74_B
C105 2 B<0> CAPCERSMDCL2_0402 I77
C108 2 B<0> CAPCERSMDCL2_0402 I76
C111 2 B<0> CAPCERSMDCL2_0402 I75
C113 2 B<0> CAPCERSMDCL2_0402 I74
UNNAMED_7_PC049AFPGA_I38_MGTRRE @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_7_PC049AFPGA_I38_MGTRREF101 UNNAMED_7_PC049AFPGA_I38_MGTRRE @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_7_PC049AFPGA_I38_MGTRREF101
R53 1 A<0> RSMD0603_1/10W I55 R53 1 A<0> RSMD0603_1/10W I55
U3 E9 MGTRREF_101 PC049A_FPGA I38 U3 E9 MGTRREF_101 PC049A_FPGA I38
...@@ -6613,35 +6607,35 @@ UNNAMED_8_AD8031_I70_IN @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_A ...@@ -6613,35 +6607,35 @@ UNNAMED_8_AD8031_I70_IN @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_A
UNNAMED_8_CON12P_I51_A @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A UNNAMED_8_CON12P_I51_A @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A
J10 8 A<7> CON12P I51 J10 8 A<7> CON12P I51
RN2 1 A<0> R4ISMD_1206 I50 RN2 8 B<0> R4ISMD_1206 I50
UNNAMED_8_CON12P_I51_A_1 @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_1 UNNAMED_8_CON12P_I51_A_1 @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_1
J10 7 A<6> CON12P I51 J10 7 A<6> CON12P I51
RN1 8 B<0> R4ISMD_1206 I49 RN1 1 A<0> R4ISMD_1206 I49
UNNAMED_8_CON12P_I51_A_2 @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_2 UNNAMED_8_CON12P_I51_A_2 @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_2
J10 5 A<4> CON12P I51 J10 5 A<4> CON12P I51
RN1 7 B<0> R4ISMD_1206 I49 RN1 2 A<0> R4ISMD_1206 I49
UNNAMED_8_CON12P_I51_A_3 @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_3 UNNAMED_8_CON12P_I51_A_3 @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_3
J10 3 A<2> CON12P I51 J10 3 A<2> CON12P I51
RN1 6 B<0> R4ISMD_1206 I49 RN1 3 A<0> R4ISMD_1206 I49
UNNAMED_8_CON12P_I51_A_4 @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_4 UNNAMED_8_CON12P_I51_A_4 @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_4
J10 1 A<0> CON12P I51 J10 1 A<0> CON12P I51
RN1 5 B<0> R4ISMD_1206 I49 RN1 4 A<0> R4ISMD_1206 I49
UNNAMED_8_CON12P_I51_A_5 @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_5 UNNAMED_8_CON12P_I51_A_5 @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_5
J10 4 A<3> CON12P I51 J10 4 A<3> CON12P I51
RN2 3 A<0> R4ISMD_1206 I50 RN2 6 B<0> R4ISMD_1206 I50
UNNAMED_8_CON12P_I51_A_6 @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_6 UNNAMED_8_CON12P_I51_A_6 @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_6
J10 2 A<1> CON12P I51 J10 2 A<1> CON12P I51
RN2 4 A<0> R4ISMD_1206 I50 RN2 5 B<0> R4ISMD_1206 I50
UNNAMED_8_CON12P_I51_A_7 @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_7 UNNAMED_8_CON12P_I51_A_7 @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_CON12P_I51_A_7
J10 6 A<5> CON12P I51 J10 6 A<5> CON12P I51
RN2 2 A<0> R4ISMD_1206 I50 RN2 7 B<0> R4ISMD_1206 I50
UNNAMED_8_LED_I105_K @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_LED_I105_K UNNAMED_8_LED_I105_K @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_LED_I105_K
LD5 2 K LED I105 LD5 2 K LED I105
...@@ -6692,11 +6686,13 @@ UNNAMED_8_RSMD0603_I92_B @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_ ...@@ -6692,11 +6686,13 @@ UNNAMED_8_RSMD0603_I92_B @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_
R57 2 B<0> RSMD0603_1/10W I92 R57 2 B<0> RSMD0603_1/10W I92
SW1 1 A SW_PUSHBUTTON_1SPSTA_4P_1 I86 SW1 1 A SW_PUSHBUTTON_1SPSTA_4P_1 I86
SW1 3 C SW_PUSHBUTTON_1SPSTA_4P_1 I86 SW1 3 C SW_PUSHBUTTON_1SPSTA_4P_1 I86
U3 H5 BUTTON1_I PC049A_FPGA I55
UNNAMED_8_RSMD0603_I97_B @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_RSMD0603_I97_B UNNAMED_8_RSMD0603_I97_B @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_8_RSMD0603_I97_B
R58 2 B<0> RSMD0603_1/10W I97 R58 2 B<0> RSMD0603_1/10W I97
SW2 1 A SW_PUSHBUTTON_1SPSTA_4P_1 I96 SW2 1 A SW_PUSHBUTTON_1SPSTA_4P_1 I96
SW2 3 C SW_PUSHBUTTON_1SPSTA_4P_1 I96 SW2 3 C SW_PUSHBUTTON_1SPSTA_4P_1 I96
U3 H6 BUTTON2_I PC049A_FPGA I55
UNNAMED_9_CAPCERSMDCL2_I30_B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_9_CAPCERSMDCL2_I30_B<0> UNNAMED_9_CAPCERSMDCL2_I30_B<0> @UOB_HEP_PC049A_LIB.PC049A_TOPLEVEL(SCH_1):UNNAMED_9_CAPCERSMDCL2_I30_B<0>
C79 2 B<0> CAPCERSMDCL2_1210 I31 C79 2 B<0> CAPCERSMDCL2_1210 I31
...@@ -7110,11 +7106,11 @@ END OF SIGNAL CROSS REFERENCE ...@@ -7110,11 +7106,11 @@ END OF SIGNAL CROSS REFERENCE
**** Part Type 'RSMD0603_1/16W' ('RSMD0603_1/16W-9K,1%') **** **** Part Type 'RSMD0603_1/16W' ('RSMD0603_1/16W-9K,1%') ****
**** Part Type 'RSMD0805_' ('RSMD0805_-00,') **** **** Part Type 'RSMD0805_' ('RSMD0805_-00,') ****
**** Part Type 'S25FL128S_RESET_VIO_SOIC' ('S25FL128SAGMFIR01-VCC=P3V3,VSSA') **** **** Part Type 'S25FL128S_RESET_VIO_SOIC' ('S25FL128SAGMFIR01-VCC=P3V3,VSSA') ****
**** Part Type 'SFP_CAGE' ('SFP_CAGE-6367034-1') **** **** Part Type 'SFP_CAGE' ('SFP_CAGE-6367034-1-GND=GND_SIGA') ****
**** Part Type 'SFP_CAGE' ('SFP_CAGE-6367035-1') **** **** Part Type 'SFP_CAGE' ('SFP_CAGE-6367035-1-GND=GND_SIGA') ****
**** Part Type 'SK_SATA_SMD_STR' ('SK_SATA_SMD_STR-MOLEX') **** **** Part Type 'SK_SATA_SMD_STR' ('SK_SATA_SMD_STR-MOLEX') ****
**** Part Type 'SN65LVDS1_SOT23-5' ('SN65LVDS1_SOT23-5-TEXAS INSTRUA') **** **** Part Type 'SN65LVDS1_SOT23-5' ('SN65LVDS1_SOT23-5-TEXAS INSTRUA') ****
**** Part Type '74LVC1G06_SOT23' ('SN74LVC1G06DBVT') **** **** Part Type '74LVC1G06_SOT23' ('SN74LVC1G06DBVT-GND=GND_SIGNALA') ****
**** Part Type 'SW4INT' ('SW4INT-1571983-4') **** **** Part Type 'SW4INT' ('SW4INT-1571983-4') ****
**** Part Type 'SW_PUSHBUTTON_1SPSTA_4P_1' ('SW_PUSHBUTTON_1SPSTA_4P_1-OMROA') **** **** Part Type 'SW_PUSHBUTTON_1SPSTA_4P_1' ('SW_PUSHBUTTON_1SPSTA_4P_1-OMROA') ****
**** Part Type 'TPS71701DCKRG4_SC70' ('TPS71701DCKRG4_SC70-TEXAS INSTA') **** **** Part Type 'TPS71701DCKRG4_SC70' ('TPS71701DCKRG4_SC70-TEXAS INSTA') ****
......
...@@ -7,3 +7,12 @@ cd uob-hep-pc049a/trunk/firmware/syn/pc049a/demo ...@@ -7,3 +7,12 @@ cd uob-hep-pc049a/trunk/firmware/syn/pc049a/demo
hdlmake-v1.0 --make-ise --ise-proj hdlmake-v1.0 --make-ise --ise-proj
make make
..... for newer versions....
python /projects/HEP_Instrumentation/cad/designs/hdl-make/git-2.1/hdl-make/hdlmake ise-project
......... For HDLMake 2.x
...@@ -110,8 +110,8 @@ BEGIN ...@@ -110,8 +110,8 @@ BEGIN
-- FIXME - connect SFP control signals -- FIXME - connect SFP control signals
sfp_scl_o <= '0'; sfp_scl_o <= '1';
sfp_sda_o <= sfp_det_i; sfp_sda_o <= '1';
-- DCM clock generation for internal bus, ethernet -- DCM clock generation for internal bus, ethernet
clocks: entity work.clocks_s6_basex port map( clocks: entity work.clocks_s6_basex port map(
...@@ -129,8 +129,9 @@ BEGIN ...@@ -129,8 +129,9 @@ BEGIN
-- Connect IPBus clock and reset to output ports. -- Connect IPBus clock and reset to output ports.
ipb_clk_o <= s_ipb_clk; ipb_clk_o <= s_ipb_clk;
ipb_rst_o <= rst_ipb; ipb_rst_o <= rst_ipb;
-- leds <= ('0', '0', locked, onehz); -- connect up locked signal
clocks_locked_o <= locked;
-- Ethernet MAC core and PHY interface -- Ethernet MAC core and PHY interface
-- In this version, consists of hard MAC core + GTP transceiver -- In this version, consists of hard MAC core + GTP transceiver
......
-- clocks_s6_basex -- clocks_s6_basex
-- --
-- Generates a 25MHz ipbus clock from 200MHz xtal reference -- Generates a 31.25MHz ipbus clock from 125MHz xtal reference
-- Includes reset logic for ipbus -- Includes reset logic for ipbus
-- --
-- Dave Newbold, April 2011 -- Dave Newbold, April 2011
-- --
-- DGC , 26/March/2015 Modified original (which generated a 25MHz ipbus clock from 200MHz xtal reference)
-- $Id$ -- $Id$
library ieee; library ieee;
...@@ -43,11 +44,12 @@ begin ...@@ -43,11 +44,12 @@ begin
o => clk_ipb_b o => clk_ipb_b
); );
-- 125MHz input ( 8ns period ), 31.25MHz output ( 32ns )
dcm0: DCM_CLKGEN dcm0: DCM_CLKGEN
generic map( generic map(
CLKIN_PERIOD => 5.0, CLKIN_PERIOD => 8.0,
CLKFX_MULTIPLY => 2, CLKFX_MULTIPLY => 2,
CLKFX_DIVIDE => 16 CLKFX_DIVIDE => 8
) )
port map( port map(
clkin => sysclk_i, clkin => sysclk_i,
......
...@@ -27,53 +27,17 @@ package body ipbus_addr_decode is ...@@ -27,53 +27,17 @@ package body ipbus_addr_decode is
function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer is function ipbus_addr_sel(signal addr : in std_logic_vector(31 downto 0)) return integer is
variable sel : integer; variable sel : integer;
begin begin
if std_match(addr, "-----------------000--000----000") then
sel := 0; -- firmwareid / base 00000000 / mask 00000000
elsif std_match(addr, "-----------------000--000----001") then
sel := 1; -- gpio / base 00000001 / mask 00000000
elsif std_match(addr, "-----------------000--000----010") then
sel := 2; -- select / base 00000002 / mask 00000000
elsif std_match(addr, "-----------------000--000----011") then
sel := 3; -- mask / base 00000003 / mask 00000000
elsif std_match(addr, "-----------------000--000----100") then
sel := 4; -- reset / base 00000004 / mask 00000000
elsif std_match(addr, "-----------------000--001-------") then
sel := 5; -- scshiftreg / base 00000080 / mask 0000007f
elsif std_match(addr, "-----------------000--010-------") then
sel := 6; -- rshiftreg / base 00000100 / mask 0000007f
elsif std_match(addr, "-----------------111--0---------") then if std_match(addr, "-------------------0--001-------") then
sel := 7; -- triggerctrl / base 00007000 / mask 00000fff sel := 0; -- scshiftreg / base 00000080 / mask 0000007f
elsif std_match(addr, "-----------------111--1---------") then elsif std_match(addr, "-------------------0--010-------") then
sel := 8; -- triggerdata / base 00007200 / mask 00000fff sel := 1; -- rshiftreg / base 00000100 / mask 0000007f
elsif std_match(addr, "-------------------0--110-------") then
elsif std_match(addr, "-----------------001--1---------") then sel := 2; -- triggerctrl / base 00000300 / mask 000007f
sel := 10; -- adcctrl0 / base 00001200 / mask 00000fff elsif std_match(addr, "-------------------1--000-------") then
elsif std_match(addr, "-----------------001--0---------") then sel := 3; -- adc / base 00001000 / mask 00000fff
sel := 11; -- adcdata0 / base 00001000 / mask 00000fff elsif std_match(addr, "-------------------0--000-------") then
sel := 5; -- firmwareid / base 00000000 / mask 00000000
elsif std_match(addr, "-----------------010--1---------") then
sel := 12; -- adcctrl1 / base 00002200 / mask 00000fff
elsif std_match(addr, "-----------------010--0---------") then
sel := 13; -- adcdata1 / base 00002000 / mask 00000fff
elsif std_match(addr, "-----------------011--1---------") then
sel := 14; -- adcctrl2 / base 00003200 / mask 00000fff
elsif std_match(addr, "-----------------011--0---------") then
sel := 15; -- adcdata2 / base 00003000 / mask 00000fff
elsif std_match(addr, "-----------------100--1---------") then
sel := 16; -- adcctrl3 / base 00004200 / mask 00000fff
elsif std_match(addr, "-----------------100--0---------") then
sel := 17; -- adcdata3 / base 00004000 / mask 00000fff
elsif std_match(addr, "-----------------101--1---------") then
sel := 18; -- adcctrl4 / base 00005200 / mask 00000fff
elsif std_match(addr, "-----------------101--0---------") then
sel := 19; -- adcdata4 / base 00005000 / mask 00000fff
elsif std_match(addr, "-----------------110------------") then
sel := 9; -- hostemac / base 00006000 / mask 00000fff
else else
sel := 99; sel := 99;
end if; end if;
......
...@@ -20,7 +20,7 @@ architecture rtl of ipbus_ver is ...@@ -20,7 +20,7 @@ architecture rtl of ipbus_ver is
begin begin
ipbus_out.ipb_rdata <= X"a618" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement). ipbus_out.ipb_rdata <= X"a61f" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_ack <= ipbus_in.ipb_strobe; ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
ipbus_out.ipb_err <= '0'; ipbus_out.ipb_err <= '0';
......
...@@ -65,7 +65,9 @@ architecture rtl of marocInterface is ...@@ -65,7 +65,9 @@ architecture rtl of marocInterface is
signal s_timeStamp : std_logic_vector(c_BUSWIDTH-1 downto 0); signal s_timeStamp : std_logic_vector(c_BUSWIDTH-1 downto 0);
signal s_tree_or : std_logic_vector( maroc_trigger_i'left+1 downto 0); signal s_tree_or : std_logic_vector( maroc_trigger_i'left+1 downto 0);
signal ck_40m : std_logic := '0'; -- internal MAROC clock.
begin -- rtl begin -- rtl
...@@ -80,8 +82,8 @@ begin -- rtl ...@@ -80,8 +82,8 @@ begin -- rtl
-- q => register_data -- q => register_data
-- ); -- );
-- Slave 1: slow control shift register controller -- Slave 0: slow control shift register controller
slave1: entity work.ipbusMarocShiftReg slave0: entity work.ipbusMarocShiftReg
generic map( generic map(
g_NBITS => 829, --! Number of bits to shift out to MAROC g_NBITS => 829, --! Number of bits to shift out to MAROC
g_NWORDS => c_NWORDS, --! Number of words in IPBUS space to store data g_NWORDS => c_NWORDS, --! Number of words in IPBUS space to store data
...@@ -103,8 +105,8 @@ begin -- rtl ...@@ -103,8 +105,8 @@ begin -- rtl
rst_sr_n_o => rst_sc_n_o rst_sr_n_o => rst_sc_n_o
); );
-- Slave 2: "R" register shift register controller -- Slave 1: "R" register shift register controller
slave2: entity work.ipbusMarocShiftReg slave1: entity work.ipbusMarocShiftReg
generic map( generic map(
g_NBITS => 128, --! Number of bits to shift out to MAROC g_NBITS => 128, --! Number of bits to shift out to MAROC
g_NWORDS => c_NWORDS, --! Number of words in IPBUS space to store data g_NWORDS => c_NWORDS, --! Number of words in IPBUS space to store data
...@@ -126,8 +128,8 @@ begin -- rtl ...@@ -126,8 +128,8 @@ begin -- rtl
rst_sr_n_o => rst_r_n_o rst_sr_n_o => rst_r_n_o
); );
-- Slave 3: Simple ADC controller -- Slave 2: Simple ADC controller
slave3: entity work.ipbusMarocADC slave2: entity work.ipbusMarocADC
generic map( generic map(
g_ADDRWIDTH => 10 ) g_ADDRWIDTH => 10 )
port map( port map(
...@@ -163,8 +165,8 @@ begin -- rtl ...@@ -163,8 +165,8 @@ begin -- rtl
-- FIXME - clk fast -- FIXME - clk fast
-- Slave 4: Trigger generator -- Slave 3: Trigger generator
slave4: entity work.ipbusMarocTriggerGenerator slave3: entity work.ipbusMarocTriggerGenerator
port map ( port map (
-- signals to IPBus -- signals to IPBus
clk_i => ipb_clk_i, clk_i => ipb_clk_i,
...@@ -206,15 +208,28 @@ begin -- rtl ...@@ -206,15 +208,28 @@ begin -- rtl
s_tree_or(i+1) <= s_tree_or(i) or maroc_trigger_i(i); s_tree_or(i+1) <= s_tree_or(i) or maroc_trigger_i(i);
end generate gen_maroc_or; end generate gen_maroc_or;
-- FIXME - for now, just wire up any old signal to an OBUFDS
-- to get correct signal type for CK_40M -- For now use IPBus clock as MAROC clock
ck_40m_obuf : OBUFDS ck_40m_obuf : OBUFDS
port map ( port map (
I => s_externalTrigger_o or s_tree_or(s_tree_or'left), I => CK_40M,
O => CK_40M_P_O, O => CK_40M_P_O,
OB => CK_40M_N_O OB => CK_40M_N_O
); );
-- Use a DDR output register to get from clock net onto output.
maroc_clock_buf : ODDR2
port map (
Q => CK_40M, -- 1-bit output data
C0 => ipb_clk_i , -- 1-bit clock input
C1 => not ipb_clk_i , -- 1-bit clock input
CE => '1', -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
R => '0', -- 1-bit reset input
S => '0' -- 1-bit set input
);
EN_OTAQ_O <= '1'; EN_OTAQ_O <= '1';
......
files = ["pc049a_top.vhd", "pc049a_top.ucf", "spec_reset_gen.vhd", "ExpansionIO_rtl.vhd"] files = ["pc049a_top.vhd", "pc049a_top.ucf", "spec_reset_gen.vhd", "../../../hdl/ExpansionIO_rtl.vhd"]
modules = { "local" : ["../../../"] } modules = { "local" : ["../../../"] }
...@@ -16,7 +16,7 @@ CONFIG VCCAUX=2.5; ...@@ -16,7 +16,7 @@ CONFIG VCCAUX=2.5;
INST "cmp_gtp_dedicated_clk_buf0" LOC = BUFDS_X2Y5; INST "cmp_gtp_dedicated_clk_buf0" LOC = BUFDS_X2Y5;
INST "IPBusInterface_inst/eth/ibuf0" LOC = BUFDS_X1Y5; INST "IPBusInterface_inst/eth/ibuf0" LOC = BUFDS_X1Y5;
INST "IPBusInterface_inst/eth/phy/transceiver_inst/GTP_1000X/tile0_s6_gtpwizard_i/gtpa1_dual_i" LOC = GTPA1_DUAL_X0Y1; INST "IPBusInterface_inst/eth/phy/transceiver_inst/GTP_1000X/tile0_s6_gtpwizard_i/gtpa1_dual_i" LOC = GTPA1_DUAL_X0Y1;
INST "U_GTP/U_GTP_TILE_INST/gtpa1_dual_i" LOC = GTPA1_DUAL_X1Y1; # INST "U_GTP/U_GTP_TILE_INST/gtpa1_dual_i" LOC = GTPA1_DUAL_X1Y1;
NET "ADC_DAV_I" IOSTANDARD = SSTL2_I; NET "ADC_DAV_I" IOSTANDARD = SSTL2_I;
NET "ADC_DAV_I" LOC = W1; NET "ADC_DAV_I" LOC = W1;
...@@ -506,14 +506,16 @@ NET "RST_SC_N_O" IOSTANDARD = LVCMOS33; ...@@ -506,14 +506,16 @@ NET "RST_SC_N_O" IOSTANDARD = LVCMOS33;
NET "RST_SC_N_O" LOC = U4; NET "RST_SC_N_O" LOC = U4;
NET "RST_SC_N_O_OBUF" IOSTANDARD = LVCMOS33; NET "RST_SC_N_O_OBUF" IOSTANDARD = LVCMOS33;
NET "RST_SC_N_O" SLEW = SLOW; NET "RST_SC_N_O" SLEW = SLOW;
NET "sata_rxn_i[0]" LOC = D13; NET "sata_rxp_i[0]" LOC = D13;
NET "sata_rxn_i[1]" LOC = C9; NET "sata_rxn_i[1]" LOC = C9;
NET "sata_rxp_i[0]" LOC = C13; NET "sata_rxn_i[0]" LOC = C13;
NET "sata_rxp_i[1]" LOC = D9; NET "sata_rxp_i[1]" LOC = D9;
NET "sata_txn_o[0]" LOC = B14; NET "sata_txp_o[0]" LOC = B14;
NET "sata_txn_o[1]" LOC = A8; NET "sata_txn_o[1]" LOC = A8;
NET "sata_txp_o[0]" LOC = A14; NET "sata_txn_o[0]" LOC = A14;
NET "sata_txp_o[1]" LOC = B8; NET "sata_txp_o[1]" LOC = B8;
NET "sfp_mod_def*" PULLUP=true;
NET "sfp_rate_select_b*" PULLUP=true;
NET "sfp_los_i[0]" IOSTANDARD = LVCMOS33; NET "sfp_los_i[0]" IOSTANDARD = LVCMOS33;
NET "sfp_los_i[0]" LOC = P3; NET "sfp_los_i[0]" LOC = P3;
NET "sfp_los_i[1]" IOSTANDARD = LVCMOS33; NET "sfp_los_i[1]" IOSTANDARD = LVCMOS33;
......
--============================================================================= --=============================================================================
--! @file pc049a_top.vhd --! @file pc049a_top.vhd
--============================================================================= --=============================================================================
...@@ -21,6 +20,12 @@ ...@@ -21,6 +20,12 @@
-- --
--! @details --! @details
--! Includes white-rabbit core, and IPBus core. --! Includes white-rabbit core, and IPBus core.
--! LEDs:
--! LED(0) - White Rabbit link active
--! LED(1) - White Rabbit link present
--! LED(2) - IPBus clocks locked. ( should be on )
--! LED(3) - One Hz heart-beat ( should strobe at 1Hz)
--! LED(4) - LOS for IPBus SFP ( should be off )
--! --!
--! <b>Dependencies:</b>\n --! <b>Dependencies:</b>\n
--! --!
...@@ -62,7 +67,7 @@ use work.wishbone_pkg.all; ...@@ -62,7 +67,7 @@ use work.wishbone_pkg.all;
entity pc049a_top is entity pc049a_top is
generic generic
( (
TAR_ADDR_WDTH : integer := 13 -- not used for this project BUILD_WHITERABBIT : integer := 1 -- set to 1 to synthesize White Rabbit cores
); );
port port
( (
...@@ -91,11 +96,10 @@ entity pc049a_top is ...@@ -91,11 +96,10 @@ entity pc049a_top is
dip_switch_i : in std_logic_vector(3 downto 0); dip_switch_i : in std_logic_vector(3 downto 0);
-- SPI interface for DACs that tune VCXO frequencies -- SPI interface for DACs that tune VCXO frequencies
pll25dac_sclk_o : out std_logic; pll25dac_sclk_o : out std_logic := '0';
pll25dac_din_o : out std_logic; pll25dac_din_o : out std_logic := '0';
-- dac_clr_n_o : out std_logic; -- not used. pll25dac1_sync_n_o : out std_logic := '1';
pll25dac1_sync_n_o : out std_logic; pll25dac2_sync_n_o : out std_logic := '1';
pll25dac2_sync_n_o : out std_logic;
-- I2C bus -- I2C bus
fpga_scl_b : inout std_logic; fpga_scl_b : inout std_logic;
...@@ -192,17 +196,7 @@ entity pc049a_top is ...@@ -192,17 +196,7 @@ entity pc049a_top is
lvds_gclk_from_fpga_n_o: out std_logic; lvds_gclk_from_fpga_n_o: out std_logic;
enable_gclk_drive_o: out std_logic; enable_gclk_drive_o: out std_logic;
lvds_gclk_to_fpga_p_i: in std_logic; lvds_gclk_to_fpga_p_i: in std_logic;
lvds_gclk_to_fpga_n_i: in std_logic lvds_gclk_to_fpga_n_i: in std_logic
-- Daughter-board SPI lines
--dboard_miso_p_i : in std_logic;
--dboard_miso_n_i : in std_logic;
--dboard_sclk_p_o : out std_logic;
--dboard_sclk_n_o : out std_logic;
--dboard_mosi_p_o : out std_logic;
--dboard_mosi_n_o : out std_logic;
--dboard_ssn_p_o : out std_logic;
--dboard_ssn_n_o : out std_logic
); );
...@@ -238,9 +232,6 @@ architecture rtl of pc049a_top is ...@@ -238,9 +232,6 @@ architecture rtl of pc049a_top is
signal s_otrig_to_fpga , s_otrig_from_fpga : std_logic; signal s_otrig_to_fpga , s_otrig_from_fpga : std_logic;
signal s_gclk_to_fpga , s_gclk_from_fpga : std_logic; signal s_gclk_to_fpga , s_gclk_from_fpga : std_logic;
-- signals for daugher-board SPI over LVDS connections.
signal s_dboard_mosi, s_dboard_ssn,s_dboard_sclk, s_dboard_miso : std_logic;
-- Dedicated clock for GTP transceiver -- Dedicated clock for GTP transceiver
signal gtp_dedicated_clk : std_logic_vector(1 downto 0); signal gtp_dedicated_clk : std_logic_vector(1 downto 0);
...@@ -286,7 +277,7 @@ architecture rtl of pc049a_top is ...@@ -286,7 +277,7 @@ architecture rtl of pc049a_top is
signal wrc_sda_o : std_logic; signal wrc_sda_o : std_logic;
signal wrc_sda_i : std_logic; signal wrc_sda_i : std_logic;
signal sfp_scl_o : std_logic_vector(1 downto 0); signal sfp_scl_o : std_logic_vector(1 downto 0) := ( others => '0' );
signal sfp_scl_i : std_logic_vector(1 downto 0); signal sfp_scl_i : std_logic_vector(1 downto 0);
signal sfp_sda_o : std_logic_vector(1 downto 0); signal sfp_sda_o : std_logic_vector(1 downto 0);
signal sfp_sda_i : std_logic_vector(1 downto 0); signal sfp_sda_i : std_logic_vector(1 downto 0);
...@@ -356,15 +347,6 @@ architecture rtl of pc049a_top is ...@@ -356,15 +347,6 @@ architecture rtl of pc049a_top is
-- Signals that used to be connected at the top level... -- Signals that used to be connected at the top level...
signal uart_rxd , uart_txd : std_logic; signal uart_rxd , uart_txd : std_logic;
--signal dboard_miso_p_i : std_logic;
--signal dboard_miso_n_i : std_logic;
--signal dboard_sclk_p_o : std_logic;
--signal dboard_sclk_n_o : std_logic;
--signal dboard_mosi_p_o : std_logic;
--signal dboard_mosi_n_o : std_logic;
--signal dboard_ssn_p_o : std_logic;
--signal dboard_ssn_n_o : std_logic;
--
begin begin
...@@ -506,6 +488,10 @@ begin ...@@ -506,6 +488,10 @@ begin
one_wire_b <= '0' when owr_en(0) = '1' else 'Z'; one_wire_b <= '0' when owr_en(0) = '1' else 'Z';
owr_i(0) <= one_wire_b; owr_i(0) <= one_wire_b;
-- The White Rabbit cores use up space in the FPGA and consume power.
-- Don't build them unless we want them.
generate_whiterabbit: if ( BUILD_WHITERABBIT = 1 ) generate
U_WR_CORE : xwr_core U_WR_CORE : xwr_core
generic map ( generic map (
g_simulation => 0, g_simulation => 0,
...@@ -695,15 +681,17 @@ begin ...@@ -695,15 +681,17 @@ begin
dac_sclk_o => pll25dac_sclk_o, dac_sclk_o => pll25dac_sclk_o,
dac_din_o => pll25dac_din_o); dac_din_o => pll25dac_din_o);
end generate generate_whiterabbit;
U_Extend_PPS : gc_extend_pulse
generic map ( -- for now connect leds_o(4) to IPBus LOS
g_width => 10000000) --U_Extend_PPS : gc_extend_pulse
port map ( -- generic map (
clk_i => clk_125m_pllref, -- g_width => 10000000)
rst_n_i => local_reset_n, -- port map (
pulse_i => pps_led, -- clk_i => clk_125m_pllref,
extended_o => leds_o(4) ); -- rst_n_i => local_reset_n,
-- pulse_i => pps_led,
-- extended_o => leds_o(4) );
si57x_oe_o <= '1'; si57x_oe_o <= '1';
...@@ -827,43 +815,6 @@ begin ...@@ -827,43 +815,6 @@ begin
enable_gclk_drive_o <= '1'; enable_gclk_drive_o <= '1';
enable_globaltrig_drive_o <= '1'; enable_globaltrig_drive_o <= '1';
--
-- Differential buffers to Daughter-board SPI connection
--dboard_mosi_obuf : OBUFDS
-- port map (
-- I => s_dboard_mosi,
-- O => dboard_mosi_p_o,
-- OB => dboard_mosi_n_o
-- );
--dboard_ssn_obuf : OBUFDS
-- port map (
-- I => s_dboard_ssn,
-- O => dboard_ssn_p_o,
-- OB => dboard_ssn_n_o
-- );
--dboard_sclk_obuf : OBUFDS
-- port map (
-- I => s_dboard_sclk,
-- O => dboard_sclk_p_o,
-- OB => dboard_sclk_n_o
-- );
--dboard_miso_ibuf : IBUFDS
-- generic map (
-- DIFF_TERM => true)
-- port map (
-- O => s_dboard_miso,
-- I => dboard_miso_p_i,
-- IB => dboard_miso_n_i
-- );
-- FIXME dummy wiring to stop buffers being optimized away.
--s_dboard_mosi <= s_dboard_miso;
--s_dboard_ssn <= s_dboard_miso;
--s_dboard_sclk <= s_dboard_miso;
-- FIXME - loop dip_switches to gpio to stop GPIO being optimized away -- FIXME - loop dip_switches to gpio to stop GPIO being optimized away
gpio(3 downto 0) <= dip_switch_i; gpio(3 downto 0) <= dip_switch_i;
gpio(4) <= si57x_clk; gpio(4) <= si57x_clk;
...@@ -883,15 +834,17 @@ begin ...@@ -883,15 +834,17 @@ begin
IB => si57x_clk_n_i IB => si57x_clk_n_i
); );
-- FIXME - connnect input to output to avoid optimization. sfp_rate_select_b(0) <= '1'; --! Connect high for full rate.
sfp_rate_select_b <= sfp_los_i or sfp_tx_fault_i; sfp_rate_select_b(1) <= '1';
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- IPBus interface -- IPBus interface
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
IPBusInterface_inst : entity work.IPBusInterfaceGTP IPBusInterface_inst : entity work.IPBusInterfaceGTP
GENERIC MAP ( GENERIC MAP (
NUM_EXT_SLAVES => 6 NUM_EXT_SLAVES => c_NMAROC_SLAVES+1 --! Total number of IPBus slave
--busses = number in MAROC +1
) )
PORT MAP ( PORT MAP (
...@@ -932,6 +885,8 @@ begin ...@@ -932,6 +885,8 @@ begin
clk_logic_xtal_o => s_clk_logic_xtal clk_logic_xtal_o => s_clk_logic_xtal
); );
leds_o(4) <= sfp_los_i(1);
-- SFP control signals for IPBus SFP -- SFP control signals for IPBus SFP
sfp_mod_def1_b(1) <= '0' when sfp_scl_o(1) = '0' else 'Z'; sfp_mod_def1_b(1) <= '0' when sfp_scl_o(1) = '0' else 'Z';
sfp_mod_def2_b(1) <= '0' when sfp_sda_o(1) = '0' else 'Z'; sfp_mod_def2_b(1) <= '0' when sfp_sda_o(1) = '0' else 'Z';
...@@ -947,8 +902,8 @@ begin ...@@ -947,8 +902,8 @@ begin
-- IPBus -- IPBus
ipbus_clk_i => s_ipb_clk, ipbus_clk_i => s_ipb_clk,
ipbus_reset_i => s_ipb_rst, ipbus_reset_i => s_ipb_rst,
ipbus_wbus_i => s_ipb_wbus(5), ipbus_wbus_i => s_ipb_wbus(c_NMAROC_SLAVES),
ipbus_rbus_o => s_ipb_rbus(5), ipbus_rbus_o => s_ipb_rbus(c_NMAROC_SLAVES),
-- Data.... -- Data....
lvds_left_data_p_b => lvds_left_data_p_b, lvds_left_data_p_b => lvds_left_data_p_b,
......
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