Commit c879f7f8 authored by David Cussans's avatar David Cussans

Adding schematic files before implementing Erik S. suggestions

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@15 e1591323-3689-4d5a-aa31-d1a7cbdc5706
parent 4af5c931
{ Machine generated file created by SPI }
{ Last modified was 16:16:53 Thursday, March 13, 2014 }
{ Last modified was 09:20:48 Thursday, March 20, 2014 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
......@@ -48,12 +48,13 @@ END_CONCEPTHDL
START_PKGRXL
comp_def_prop 'ALT_SYMBOLS' 'JEDEC_TYPE' 'MERGE_NC_PINS' 'MERGE_POWER_PINS' 'NC_PINS' 'PINCOUNT' 'POWER_GROUP' 'POWER_PINS'
comp_inst_prop 'DEFAULT_SIGNAL_MODEL' 'GROUP' 'REUSE_ID' 'REUSE_INSTANCE' 'REUSE_NAME' 'ROOM' 'SIGNAL_MODEL' 'VOLT_TEMP_SIGNAL_MODEL'
feedback 'ALLEGRO'
regenerate_physical_net_name 'OFF'
electrical_constraints 'ON'
overwrite_constraints 'OFF'
USE_SUBDESIGN
FORCE_SUBDESIGN
GEN_SUBDESIGN
GEN_SUBDESIGN 'pc043c_single_maroc'
FILTER_PROPERTY
PASS_PROPERTY
FILTER_CONFLICTING_PROP
......@@ -67,7 +68,7 @@ create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'pc043c_single_maroc_27.brd'
last_board_file 'pc043c_single_maroc_29.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
......
{ Machine generated file created by SPI }
{ Last modified was 13:55:27 Thursday, March 13, 2014 }
{ Last modified was 16:44:58 Thursday, June 12, 2014 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
......@@ -8,7 +8,7 @@ START_GLOBAL
view_pcb './worklib/pc049a_toplevel/physical'
design_name 'pc049a_toplevel'
design_library 'uob_hep_pc049a_lib'
library 'uob_hep_pc049a_lib' 'bris_cds_analogue' 'bris_cds_connectors' 'bris_cds_discrete' 'bris_cds_logic' 'bris_cds_memory' 'bris_cds_pld' 'bris_cds_special' 'bris_cds_standard' 'bris_cds_switches' 'cn74lv' 'cn74tiac' 'cn75als' 'cncmos' 'cnconnector' 'cndiscrete' 'cnpassive' 'cnpld' 'cnpower' 'cnspecial' 'cnstandard' 'cnvlsi' 'standard' 'cnlinear'
library 'uob_hep_pc049a_lib' 'bris_cds_analogue' 'bris_cds_connectors' 'bris_cds_discrete' 'bris_cds_logic' 'bris_cds_memory' 'bris_cds_pld' 'bris_cds_special' 'bris_cds_standard' 'bris_cds_switches' 'cn74lv' 'cn74tiac' 'cn75als' 'cncmos' 'cnconnector' 'cndiscrete' 'cnpassive' 'cnpld' 'cnpower' 'cnspecial' 'cnstandard' 'cnvlsi' 'standard' 'cnlinear' 'cnmemory' 'cninterface' 'cnmech' 'cnmicro' 'help' 'cn100e' 'cn10e' 'cn10el' 'cn10k' 'cn10kh'
temp_dir 'temp'
cpm_version '16.5'
session_name 'ProjectMgr58303345'
......@@ -33,12 +33,12 @@ HPF_SPEC_PLOT_PAGESIZE 'YES'
HPF_BATCH 'YES'
HPF_PLOT_FILE_LOCATION '/home/phdgc'
HPF_PLOT_FILE_NAME 'pc049a_toplevel1.ps'
PLOTTER_FACILITY 'HPF'
PLOTTER_FACILITY 'DEVICE'
PLOT_EDGE_TO_EDGE 'ON'
PAPER_SIZE '9'
PAPER_ORIENTATION '1'
PAPER_ORIENTATION '2'
PAPER_SOURCE '15'
WPLOTTER_NAME ''
WPLOTTER_NAME 'Generic PostScript Printer'
HPF_PLOT_PAGESIZE 'A4'
HPF_PAGESCALETYPE 'PAGESIZE'
HPF_PAGESIZE 'A4'
......@@ -48,11 +48,12 @@ END_CONCEPTHDL
START_PKGRXL
comp_def_prop 'ALT_SYMBOLS' 'JEDEC_TYPE' 'MERGE_NC_PINS' 'MERGE_POWER_PINS' 'NC_PINS' 'PINCOUNT' 'POWER_GROUP' 'POWER_PINS'
comp_inst_prop 'DEFAULT_SIGNAL_MODEL' 'GROUP' 'REUSE_ID' 'REUSE_INSTANCE' 'REUSE_NAME' 'ROOM' 'SIGNAL_MODEL' 'VOLT_TEMP_SIGNAL_MODEL'
optimize 'ON'
regenerate_physical_net_name 'OFF'
electrical_constraints 'OFF'
electrical_constraints 'ON'
overwrite_constraints 'OFF'
USE_SUBDESIGN
FORCE_SUBDESIGN
FORCE_SUBDESIGN 'pc043c_single_maroc'
GEN_SUBDESIGN
FILTER_PROPERTY
PASS_PROPERTY
......@@ -67,15 +68,15 @@ create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'pc049a_toplevel_01.brd'
last_board_file 'pc049a_toplevel_23.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
END_DESIGNSYNC
START_BOMHDL
last_output_file '/projects/HEP_Instrumentation/cad/designs/uob_hep_pc049a/trunk/design_files/worklib/pc049a_toplevel/bom/pc049a_toplevel.csv'
last_template_file '/projects/HEP_Instrumentation/cad/tools/cadence_templates/spreadsheet-format.bom'
last_output_file './worklib/pc049a_toplevel/bom/pc049a_one_per_line.csv'
last_template_file '/projects/HEP_Instrumentation/cad/tools/cadence_templates/spreadsheet-format_1per_line.bom'
last_standard_option '1'
last_what_to_output '0'
last_variant_file ''
......@@ -85,6 +86,13 @@ last_callout_file ''
last_variant ''
END_BOMHDL
START_ERCDX
io_check 'OFF'
load_check 'OFF'
single_node_check 'OFF'
connect_check 'OFF'
END_ERCDX
START_VXL
run_directory './worklib/pc049a_toplevel/cfg_verilog/sim1'
END_VXL
......@@ -93,12 +101,6 @@ START_ECSET_MODELS
retain_existing_xnets_and_diffpairs 'NO'
END_ECSET_MODELS
START_ALLEGRO
hdl_padpath '.' 'symbols' '..' '../symbols' '$CADENCE_INST_DIR/share/pcb/pcb_lib/symbols' '$CADENCE_INST_DIR/share/pcb/allegrolib/symbols' '$RAL_CDSLIB_PSD15/pads' '$BRIS_CDSLIB/pads' '$CERN_CDS_PADS/padstack_smd' '$CERN_CDS_PADS/padstacks/padstack3'
hdl_psmpath '.' 'symbols' '..' '../symbols' '$CADENCE_INST_DIR/share/pcb/pcb_lib/symbols' '$CADENCE_INST_DIR/share/pcb/allegrolib/symbols' '$RAL_CDSLIB_PSD15/symbols' '$BRIS_CDSLIB/symbols' '$CERN_CDS_SYMBOLS/connector' '$CERN_CDS_SYMBOLS/discrete'
hdl_topology_template_path '.' 'templates' '..' '../templates' '$CADENCE_INST_DIR/share/pcb/pcb_lib/templates' '$CADENCE_INST_DIR/share/pcb/allegrolib/templates'
END_ALLEGRO
START_VARIANT
last_variant_file 'variant.dat'
last_edit_type '2'
......@@ -111,3 +113,9 @@ annotation_DNIproperty_value 'DNI'
columns 'REFDES' 'CDS_VAR_STATUS' 'PART_NAME' 'PART_NUMBER'
END_VARIANT
START_ALLEGRO
hdl_padpath '.' 'symbols' '..' '../symbols' '$CADENCE_INST_DIR/share/pcb/pcb_lib/symbols' '$CADENCE_INST_DIR/share/pcb/allegrolib/symbols' '/projects/HEP_Instrumentation/cad/ral_cdslib/lib_psd15.x/pads' '/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/pads' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/padstacks/padstack_smd' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/padstacks/padstacks/padstack3'
hdl_psmpath '.' 'symbols' '..' '../symbols' '$CADENCE_INST_DIR/share/pcb/pcb_lib/symbols' '$CADENCE_INST_DIR/share/pcb/allegrolib/symbols' '/projects/HEP_Instrumentation/cad/ral_cdslib/lib_psd15.x/symbols' '/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/symbols' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/connector' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/discrete'
hdl_topology_template_path '.' 'templates' '..' '../templates' '$CADENCE_INST_DIR/share/pcb/pcb_lib/templates' '$CADENCE_INST_DIR/share/pcb/allegrolib/templates'
END_ALLEGRO
// generated by NetAssembler Version 16.5-S016 (v16-5-13AQ) 2/14/2012
// on Mon Mar 17 15:01:01 2014
`timescale 1ns/1ns
`define scale_fs * 0.000001000000000
`define scale_ps * 0.001000000000000
`define scale_ns * 1.000000000000000
`define scale_us * 1000.000000000000000
`define scale_ms * 1000000.000000000000000
`define scale_sec * 1000000000.000000000000000
`define scale_min * 60000000000.000000000000000
`define scale_hr * 3600000000000.000000000000000
module alias_vector (a, a);
parameter size = 1;
inout [size-1:0] a;
endmodule
module alias_bit (a, a);
inout a;
endmodule
module glbl ();
// Verilog global signals module
wire avdd;
wire gnd_signal;
endmodule
config pc043c_single_maroc;
design uob_hep_pc043a_lib.pc043c_single_maroc:sch_1;
liblist uob_hep_pc043a_lib, bris_cds_standard, standard, cnconnector, cndiscrete, cnlinear, cnstandard, cnpassive, cnpower, cnspecial, bris_cds_connectors, bris_cds_analogue;
design uob_hep_pc049a_lib.pc043c_single_maroc:sch_1;
liblist uob_hep_pc049a_lib, bris_cds_analogue, bris_cds_connectors, bris_cds_discrete, bris_cds_logic, bris_cds_memory, bris_cds_pld, bris_cds_special, bris_cds_standard, bris_cds_switches, cn74lv, cn74tiac, cn75als, cncmos, cnconnector, cndiscrete, cnpassive, cnpld, cnpower, cnspecial, cnstandard, cnvlsi, standard, cnlinear;
viewlist edif, vlog_rtl, vhdl_rtl, sch_1, entity;
stoplist none;
endconfig
config pc043c_single_maroc;
design uob_hep_pc043a_lib.pc043c_single_maroc:sim_sch_1;
liblist uob_hep_pc043a_lib, bris_cds_standard, standard, cnconnector, cndiscrete, cnlinear, cnstandard, cnpassive, cnpower, cnspecial, bris_cds_connectors, bris_cds_analogue;
design uob_hep_pc049a_lib.pc043c_single_maroc:sim_sch_1;
liblist uob_hep_pc049a_lib, bris_cds_analogue, bris_cds_connectors, bris_cds_discrete, bris_cds_logic, bris_cds_memory, bris_cds_pld, bris_cds_special, bris_cds_standard, bris_cds_switches, cn74lv, cn74tiac, cn75als, cncmos, cnconnector, cndiscrete, cnpassive, cnpld, cnpower, cnspecial, cnstandard, cnvlsi, standard, cnlinear;
viewlist vlog_map, hw_map, swift_map, vlog_model, hw_model, swift_model, vlog_structural, vlog_rtl, vlog_behavioral, vlog_system, mcvlog, pic_1, picopt_1, tbl_1, sim_sch_1, sch_1, entity;
stoplist vlog_model, swift_model;
endconfig
config pc043c_single_maroc;
design uob_hep_pc043a_lib.pc043c_single_maroc:sim_sch_1;
liblist uob_hep_pc043a_lib, bris_cds_standard, standard, cnconnector, cndiscrete, cnlinear, cnstandard, cnpassive, cnpower, cnspecial, bris_cds_connectors, bris_cds_analogue;
design uob_hep_pc049a_lib.pc043c_single_maroc:sim_sch_1;
liblist uob_hep_pc049a_lib, bris_cds_analogue, bris_cds_connectors, bris_cds_discrete, bris_cds_logic, bris_cds_memory, bris_cds_pld, bris_cds_special, bris_cds_standard, bris_cds_switches, cn74lv, cn74tiac, cn75als, cncmos, cnconnector, cndiscrete, cnpassive, cnpld, cnpower, cnspecial, cnstandard, cnvlsi, standard, cnlinear;
viewlist vhdl_model, hw_model, swift_model, vhdl_structural, vhdl_rtl, vhdl_behavioral, vhdl_system, mc_arch, pic_1, picopt_1, sim_sch_1, sch_1;
stoplist none;
endconfig
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A!REFDES!COMP_REUSE_ID!COMP_SIGNAL_MODEL!COMP_NO_XNET_CONNECTION!COMP_PARENT_PPT!COMP_SYMBOL_EDITED!COMP_PARENT_PPT_PART!COMP_EMBEDDED_PLACEMENT!
J!/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc043c_single_maroc/physical/pc043c_single_maroc_29.brd!Thu Mar 20 09:19:21 2014!-310.8900!-191.4865!310.3900!189.9135!0.0001!millimeters!PC043C_SINGLE_MAROC!62.951181 mil!6!OUT OF DATE!
S!J1!4!!!CON6P!!CON6P-SSW-103-01-G-D!!
S!C48!2!!!ELCAPTAN!!ELCAPTAN_SMD_A-22UF,6.3V!!
S!RG1!1!!!TPS776XX!!TPS77625D!!
S!D1!3!!!DIODE_CA!!DIODE_CA_SCHOTTKY-RB751V40T1!!
S!C1!147!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C2!145!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C3!141!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C4!139!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C5!135!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C6!132!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C7!130!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C8!129!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C9!125!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C10!123!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C11!119!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C12!117!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C13!115!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C14!110!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C15!108!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C16!106!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C17!105!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C18!99!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C19!98!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C20!92!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C21!91!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C22!88!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C23!87!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C24!82!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C25!81!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C26!78!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C27!77!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C28!66!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C29!65!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C30!64!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C31!63!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C32!54!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C33!53!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C34!52!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C35!51!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C36!44!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C37!43!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C38!42!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C39!41!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C40!36!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C41!35!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C42!34!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C43!33!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C44!26!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C45!25!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C46!24!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C47!23!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C50!219!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C51!213!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C52!244!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-10UF_X5R,6.3V!!
S!C53!242!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-10UF_X5R,6.3V!!
S!C54!241!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-10UF_X5R,6.3V!!
S!R3!192!!!RSMD0402!!RSMD0402_1/16W-10R,5%!!
S!R4!191!!!RSMD0402!!RSMD0402_1/16W-10R,5%!!
S!R5!190!!!RSMD0402!!RSMD0402_1/16W-10R,5%!!
S!R6!189!!!RSMD0402!!RSMD0402_1/16W-10R,5%!!
S!R7!188!!!RSMD0402!!RSMD0402_1/16W-10R,5%!!
S!R8!187!!!RSMD0402!!RSMD0402_1/16W-10R,5%!!
S!R9!186!!!RSMD0402!!RSMD0402_1/16W-10R,5%!!
S!R10!185!!!RSMD0402!!RSMD0402_1/16W-10R,5%!!
S!R11!184!!!RSMD0402!!RSMD0402_1/16W-10R,5%!!
S!R12!183!!!RSMD0402!!RSMD0402_1/16W-10R,5%!!
S!R13!182!!!RSMD0402!!RSMD0402_1/16W-10R,5%!!
S!R15!180!!!RSMD0402!!RSMD0402_1/16W-10R,5%!!
S!R16!179!!!RSMD0402!!RSMD0402_1/16W-10R,5%!!
S!R46!245!!!RSMD0402!!RSMD0402_1/16W-3.3R,5%!!
S!R47!243!!!RSMD0402!!RSMD0402_1/16W-3.3R,5%!!
S!U1!149!!!MAROC3!!MAROC3_PQFP-IN2P3!!
S!R42!218!!!RSMD0603!!RSMD0603_1/10W-82,1%!!
S!LK1!144!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK2!143!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK3!138!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK4!137!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK5!134!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK6!128!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK7!127!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK8!122!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK9!121!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK10!114!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK11!113!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK12!112!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK13!104!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK14!103!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK15!102!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK16!97!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK17!96!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK18!90!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK19!89!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK20!86!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK21!85!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK22!80!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK23!79!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK24!76!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK25!75!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK27!73!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK28!72!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK29!71!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK30!70!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK31!62!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK32!61!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK33!60!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK34!59!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK35!50!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK36!49!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK37!48!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK38!47!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK39!40!!!1-HOLE!!1-HOLE_0-8-BASE!!
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S!LK45!30!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK46!29!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK47!22!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK48!21!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK49!20!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK50!19!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK26!239!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK51!238!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK52!237!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK53!236!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK54!235!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK55!234!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK56!233!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK57!232!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK58!230!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK59!229!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK60!228!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK61!227!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK62!226!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK63!225!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK64!224!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK65!223!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK66!222!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK67!221!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK68!220!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!J3!231!!!CON3P!!CON3P-SIL254D!!
S!J4!214!!!CON3P!!CON3P-SIL254D!!
S!R20!175!!!RSMD0402!!RSMD0402_0.0625W-XX,1%!!
S!R21!174!!!RSMD0402!!RSMD0402_0.0625W-XX,1%!!
S!R22!173!!!RSMD0402!!RSMD0402_0.0625W-XX,1%!!
S!R23!172!!!RSMD0402!!RSMD0402_0.0625W-XX,1%!!
S!R25!170!!!RSMD0402!!RSMD0402_0.0625W-XX,1%!!
S!R26!169!!!RSMD0402!!RSMD0402_0.0625W-XX,1%!!
S!R28!167!!!RSMD0402!!RSMD0402_0.0625W-XX,1%!!
S!R29!166!!!RSMD0402!!RSMD0402_0.0625W-XX,1%!!
S!R30!165!!!RSMD0402!!RSMD0402_0.0625W-XX,1%!!
S!R31!164!!!RSMD0402!!RSMD0402_0.0625W-XX,1%!!
S!R32!163!!!RSMD0402!!RSMD0402_0.0625W-XX,1%!!
S!R33!162!!!RSMD0402!!RSMD0402_0.0625W-XX,1%!!
S!R34!161!!!RSMD0402!!RSMD0402_0.0625W-XX,1%!!
S!R35!160!!!RSMD0402!!RSMD0402_0.0625W-XX,1%!!
S!R36!159!!!RSMD0402!!RSMD0402_0.0625W-XX,1%!!
S!R37!158!!!RSMD0402!!RSMD0402_0.0625W-XX,1%!!
S!R14!181!!!RSMD0402!!RSMD0402_1/16W-100,0.1%_GEN!!
S!R17!178!!!RSMD0402!!RSMD0402_1/16W-100,0.1%_GEN!!
S!R24!171!!!RSMD0402!!RSMD0402_1/16W-100,1%!!
S!R27!168!!!RSMD0402!!RSMD0402_1/16W-1K,5%!!
S!R1!194!!!RSMD0402!!RSMD0402_1/16W-51,1%!!
S!R2!193!!!RSMD0402!!RSMD0402_1/16W-51,1%!!
S!R18!177!!!RSMD0402!!RSMD0402_1/16W-51,1%!!
S!R19!176!!!RSMD0402!!RSMD0402_1/16W-51,1%!!
This diff is collapsed.
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{ Packager-XL run on 13-Mar-2014 AT 16:16:51 }
{ Packager-XL run on 20-Mar-2014 AT 09:19:22 }
FILE_TYPE = BACK_ANNOTATION;
DRAWING = "@uob_hep_pc049a_lib.pc043c_single_maroc(sch_1):page1";
BODY = "MAROC3","I1": LOCATION = "U1" #&CDS_LOCATION = "U1" &SEC = "1" #&CDS_SEC = "1";
......@@ -141,18 +141,18 @@ BODY = "MAROC3","I1": LOCATION = "U1" #&CDS_LOCATION = "U1" &SEC = "1" #&CDS_SEC
"SUM6": PN = "218" !CDS_PN = "218";
"SUM7": PN = "216" !CDS_PN = "216";
"SUM8": PN = "214" !CDS_PN = "214";
BODY = "RSMD0402","I146": LOCATION = "R1" #&CDS_LOCATION = "R1" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0402","I147": LOCATION = "R2" #&CDS_LOCATION = "R2" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "1-HOLE","I148": LOCATION = "LK51" #&CDS_LOCATION = "LK51" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
BODY = "1-HOLE","I149": LOCATION = "LK52" #&CDS_LOCATION = "LK52" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
BODY = "1-HOLE","I150": LOCATION = "LK26" #&CDS_LOCATION = "LK26" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
BODY = "RSMD0402","I146": LOCATION = "R1" #&CDS_LOCATION = "R1" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0402","I147": LOCATION = "R2" #&CDS_LOCATION = "R2" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
DRAWING = "@uob_hep_pc049a_lib.pc043c_single_maroc(sch_1):page2";
BODY = "MAROC3","I1": LOCATION = "U1" #&CDS_LOCATION = "U1" &SEC = "3" #&CDS_SEC = "3";
"GND_CAPA": PN = "217" !CDS_PN = "217";
......@@ -654,12 +654,6 @@ BODY = "CON3P","I231": LOCATION = "J4" #&CDS_LOCATION = "J4" &SEC = "1" #&CDS_SE
"A<0>": PN = "1" !CDS_PN = "1";
"A<1>": PN = "2" !CDS_PN = "2";
"A<2>": PN = "3" !CDS_PN = "3";
BODY = "RSMD0603","I233": LOCATION = "R44" #&CDS_LOCATION = "R44" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0603","I234": LOCATION = "R45" #&CDS_LOCATION = "R45" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0603","I236": LOCATION = "R42" #&CDS_LOCATION = "R42" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
......@@ -669,9 +663,6 @@ BODY = "CAPCERSMDCL2","I237": LOCATION = "C51" #&CDS_LOCATION = "C51" &SEC = "1"
BODY = "CAPCERSMDCL2","I238": LOCATION = "C50" #&CDS_LOCATION = "C50" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "RSMD0402","I241": LOCATION = "R48" #&CDS_LOCATION = "R48" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "CAPCERSMDCL2","I242": LOCATION = "C54" #&CDS_LOCATION = "C54" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
......@@ -685,4 +676,15 @@ BODY = "CON6P","I246": LOCATION = "J1" #&CDS_LOCATION = "J1" &SEC = "1" #&CDS_SE
BODY = "DIODE_CA","I245": LOCATION = "D1" #&CDS_LOCATION = "D1" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "2" !CDS_PN = "2";
"K<0>": PN = "1" !CDS_PN = "1";
BODY = "ELCAPTAN","I252": LOCATION = "C48" #&CDS_LOCATION = "C48" &SEC = "1" #&CDS_SEC = "1";
"A<0>": PN = "1" !CDS_PN = "1";
"B<0>": PN = "2" !CDS_PN = "2";
BODY = "TPS776XX","I253": LOCATION = "RG1" #&CDS_LOCATION = "RG1" &SEC = "1" #&CDS_SEC = "1";
"EN*": PN = "2" !CDS_PN = "2";
"GND": PN = "1" !CDS_PN = "1";
"IN<1>": PN = "3" !CDS_PN = "3";
"IN<2>": PN = "4" !CDS_PN = "4";
"OUT<1>": PN = "5" !CDS_PN = "5";
"OUT<2>": PN = "6" !CDS_PN = "6";
"PG": PN = "8" !CDS_PN = "8";
END.
This diff is collapsed.
; Packager-XL run on 13-Mar-2014 AT 16:16:51 CONSTRAINTS_VIEW_GENERATED
; Packager-XL run on 20-Mar-2014 AT 09:19:22 CONSTRAINTS_VIEW_GENERATED
( ConstraintFile "pc043c_single_maroc"
( constraintHeader
( objectKey
......@@ -8,11 +8,12 @@
( 16.5 )
)
( revisionNumber
( logicalViewRevNum 25 )
( physicalViewRevNum 0 )
( logicalViewRevNum 29 )
( physicalViewRevNum 1 )
( otherViewRevNum 0 )
)
( contents
( drawing )
( dictionaryExtensions )
( worksheetCustomizations )
( electricalConstraints )
......@@ -20,8 +21,14 @@
( properties )
)
( precision
( units mil )
( numberOfDecimalPlaces 2 )
( units mm )
( numberOfDecimalPlaces 4 )
)
)
( drawing
( attribute "DRAWING_EXTENTS" "621.2800,381.4000"
)
( attribute "DRAWING_LOWER_LEFT" "-310.8900,-191.4865"
)
)
( DictionaryExtensions
......@@ -371,6 +378,106 @@
( Analysis
)
)
( Attribute
( Name "IC" )
( Description " " )
( Value
( DataType ( dString ) )
( Status sProperty sPackage )
)
( Objects
( ValidObjects oGate oGateDefn oBlock oPart oDesign oSystem oPartDefn )
( NoInherit
( oGate oPin )
)
)
( Analysis
)
)
( Attribute
( Name "KNEE" )
( Description " " )
( Value