Commit d64c82c3 authored by David Cussans's avatar David Cussans

marocInterface_rtl.vhd - Added external trigger from GPIO header as well as…

marocInterface_rtl.vhd  - Added external trigger from GPIO header as well as from DIN41612 connectors

marocTriggerGenerator_rtl.vhd - added attributes to prevent synchronization steps being optimized to a shift register



git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@42 e1591323-3689-4d5a-aa31-d1a7cbdc5706
parent df9b217a
......@@ -20,7 +20,7 @@ architecture rtl of ipbus_ver is
begin
ipbus_out.ipb_rdata <= X"a623" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_rdata <= X"a625" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
ipbus_out.ipb_err <= '0';
......
......@@ -26,6 +26,7 @@ entity marocInterface is
-- Trigger signals
external_Trigger_i : in std_logic;
gpio_Trigger_i : in std_logic;
trigger_o : out std_logic;
-- Pins connected to MAROC
......@@ -134,7 +135,7 @@ begin -- rtl
-- Fast clock and external trigger signals
clk_fast_i => clk_fast_i,
externalTrigger_a_i => external_trigger_i,
externalTrigger_a_i => external_trigger_i or gpio_trigger_i,
externalTrigger_o => s_externalTrigger_o,
-- Signals to MAROC
......
......@@ -93,18 +93,27 @@ END marocTriggerGenerator ;
--
ARCHITECTURE rtl OF marocTriggerGenerator IS
attribute shreg_extract : string; -- Don't want synchronizer registers optimized to SRL16
signal s_or1_d1 : std_logic; -- ! OR1 signal delayed by one-clock of clk_fast_i
signal s_or1_d2 : std_logic; --!
attribute shreg_extract of s_or1_d1: signal is "no";
attribute shreg_extract of s_or1_d2: signal is "no";
signal s_or2_d1 : std_logic; --!
signal s_or2_d2 : std_logic; --!
attribute shreg_extract of s_or2_d1: signal is "no";
attribute shreg_extract of s_or2_d2: signal is "no";
signal s_externalTrigger_d1 : std_logic; --!
signal s_externalTrigger_d2 : std_logic; --!
attribute shreg_extract of s_externalTrigger_d1: signal is "no";
attribute shreg_extract of s_externalTrigger_d2: signal is "no";
signal s_internalTrigger_d1 : std_logic; --!
signal s_internalTrigger_d2 : std_logic; --!
signal s_hold1 : std_logic; --!
--! hold1,hold2 are active low. This signal gets put through a delay.
......
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