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Scalable MAROC Charge Sensitive Readout
Commit de1cbaf1 authored by David Cussans's avatar David Cussans
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Edited UCF to specify termination of some of the LVDS lines. 

Edited pc049a_top.vhd in order to only build the IPBus ( not the White Rabbit ) cores by default. Reduces power dissipation and keeps chip cooler.



git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@30 e1591323-3689-4d5a-aa31-d1a7cbdc5706
parent b31f50a2
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Showing with 40 additions and 30 deletions
firmware/top/pc049a/demo/pc049a_top.ucf
View file @ de1cbaf1
...@@ -37,10 +37,10 @@ NET "CK_SC_O" IOSTANDARD = LVCMOS33; ...@@ -37,10 +37,10 @@ NET "CK_SC_O" IOSTANDARD = LVCMOS33;
NET "CK_SC_O" LOC = V1; NET "CK_SC_O" LOC = V1;
NET "CK_SC_O" SLEW = SLOW; NET "CK_SC_O" SLEW = SLOW;
NET "clk_125m_pllref_n_i" IOSTANDARD = LVDS_25; NET "clk_125m_pllref_n_i" IOSTANDARD = LVDS_25;
NET "clk_125m_pllref_n_i" LOC = K22; NET "clk_125m_pllref_n_i" LOC = K22 | DIFF_TERM=TRUE;
NET "clk_125m_pllref_n_i" TNM_NET = "clk_125m_pllref_n_i"; NET "clk_125m_pllref_n_i" TNM_NET = "clk_125m_pllref_n_i";
NET "clk_125m_pllref_p_i" IOSTANDARD = LVDS_25; NET "clk_125m_pllref_p_i" IOSTANDARD = LVDS_25;
NET "clk_125m_pllref_p_i" LOC = K21; NET "clk_125m_pllref_p_i" LOC = K21 | DIFF_TERM=TRUE;
NET "clk_125m_pllref_p_i" TNM_NET = "clk_125m_pllref_p_i"; NET "clk_125m_pllref_p_i" TNM_NET = "clk_125m_pllref_p_i";
NET "clk_20m_vcxo_i" IOSTANDARD = LVCMOS33; NET "clk_20m_vcxo_i" IOSTANDARD = LVCMOS33;
NET "clk_20m_vcxo_i" LOC = L3; NET "clk_20m_vcxo_i" LOC = L3;
...@@ -98,11 +98,11 @@ NET "EN_OTAQ_O" DRIVE = 12; ...@@ -98,11 +98,11 @@ NET "EN_OTAQ_O" DRIVE = 12;
NET "EN_OTAQ_O" IOSTANDARD = LVCMOS33; NET "EN_OTAQ_O" IOSTANDARD = LVCMOS33;
NET "EN_OTAQ_O" LOC = V5; NET "EN_OTAQ_O" LOC = V5;
NET "EN_OTAQ_O" SLEW = SLOW; NET "EN_OTAQ_O" SLEW = SLOW;
NET "fpga_pll_ref_clk_101_n_i" LOC = F12; NET "fpga_pll_ref_clk_101_n_i" LOC = F12 | DIFF_TERM=TRUE;
NET "fpga_pll_ref_clk_101_n_i" TNM_NET = "fpga_pll_ref_clk_101_n_i"; NET "fpga_pll_ref_clk_101_n_i" TNM_NET = "fpga_pll_ref_clk_101_n_i";
NET "fpga_pll_ref_clk_101_p_i" LOC = E12; NET "fpga_pll_ref_clk_101_p_i" LOC = E12 | DIFF_TERM=TRUE;
NET "fpga_pll_ref_clk_123_n_i" LOC = D11; NET "fpga_pll_ref_clk_123_n_i" LOC = D11 | DIFF_TERM=TRUE;
NET "fpga_pll_ref_clk_123_p_i" LOC = C11; NET "fpga_pll_ref_clk_123_p_i" LOC = C11 | DIFF_TERM=TRUE;
NET "fpga_pll_ref_clk_123_p_i" TNM_NET = "fpga_pll_ref_clk_123_p_i"; NET "fpga_pll_ref_clk_123_p_i" TNM_NET = "fpga_pll_ref_clk_123_p_i";
NET "fpga_scl_b" DRIVE = 12; NET "fpga_scl_b" DRIVE = 12;
NET "fpga_scl_b" IOSTANDARD = LVCMOS33; NET "fpga_scl_b" IOSTANDARD = LVCMOS33;
...@@ -588,3 +588,5 @@ TIMESPEC TS_fpga_pll_ref_clk_101_n_i = PERIOD "fpga_pll_ref_clk_101_n_i" 125 MHz ...@@ -588,3 +588,5 @@ TIMESPEC TS_fpga_pll_ref_clk_101_n_i = PERIOD "fpga_pll_ref_clk_101_n_i" 125 MHz
TIMESPEC TS_fpga_pll_ref_clk_123_p_i = PERIOD "fpga_pll_ref_clk_123_p_i" 125 MHz HIGH 50 %; TIMESPEC TS_fpga_pll_ref_clk_123_p_i = PERIOD "fpga_pll_ref_clk_123_p_i" 125 MHz HIGH 50 %;
TIMESPEC TS_lvds_left_clk_p_b = PERIOD "lvds_left_clk_p_b" 125 MHz HIGH 50 %; TIMESPEC TS_lvds_left_clk_p_b = PERIOD "lvds_left_clk_p_b" 125 MHz HIGH 50 %;
TIMESPEC TS_lvds_right_clk_p_b = PERIOD "lvds_right_clk_p_b" 125 MHz HIGH 50 %; TIMESPEC TS_lvds_right_clk_p_b = PERIOD "lvds_right_clk_p_b" 125 MHz HIGH 50 %;
NET "IPBusInterface_inst/clocks/rst" TIG;
\ No newline at end of file
firmware/top/pc049a/demo/pc049a_top.vhd
View file @ de1cbaf1
...@@ -67,7 +67,7 @@ use work.wishbone_pkg.all; ...@@ -67,7 +67,7 @@ use work.wishbone_pkg.all;
entity pc049a_top is entity pc049a_top is
generic generic
( (
BUILD_WHITERABBIT : integer := 1 -- set to 1 to synthesize White Rabbit cores BUILD_WHITERABBIT : integer := 0 -- set to 1 to synthesize White Rabbit cores
); );
port port
( (
...@@ -611,7 +611,38 @@ begin ...@@ -611,7 +611,38 @@ begin
master_o(0) => wrc_slave_i); master_o(0) => wrc_slave_i);
--------------------- ---------------------
U_DAC_ARB : spec_serial_dac_arb
generic map (
g_invert_sclk => false,
g_num_extra_bits => 8)
port map (
clk_i => clk_sys,
rst_n_i => local_reset_n,
val1_i => dac_dpll_data,
load1_i => dac_dpll_load_p1,
val2_i => dac_hpll_data,
load2_i => dac_hpll_load_p1,
dac_cs_n_o(0) => pll25dac1_sync_n_o,
dac_cs_n_o(1) => pll25dac2_sync_n_o,
dac_clr_n_o => open, -- Not used
dac_sclk_o => pll25dac_sclk_o,
dac_din_o => pll25dac_din_o);
end generate generate_whiterabbit;
-- messy hack to connect up LEDs even if White Rabbit not built.
generate_whiterabbit_leds: if ( BUILD_WHITERABBIT /= 1 ) generate
leds_o(0) <= '0';
leds_o(1) <= '0';
end generate generate_whiterabbit_leds;
-- for now always instantiate the White rabbit GTP + interface
-- MAP complains otherwise and I can't figure out why.
U_GTP : wr_gtp_phy_spartan6 U_GTP : wr_gtp_phy_spartan6
generic map ( generic map (
g_enable_ch0 => 0, g_enable_ch0 => 0,
...@@ -660,29 +691,6 @@ begin ...@@ -660,29 +691,6 @@ begin
U_DAC_ARB : spec_serial_dac_arb
generic map (
g_invert_sclk => false,
g_num_extra_bits => 8)
port map (
clk_i => clk_sys,
rst_n_i => local_reset_n,
val1_i => dac_dpll_data,
load1_i => dac_dpll_load_p1,
val2_i => dac_hpll_data,
load2_i => dac_hpll_load_p1,
dac_cs_n_o(0) => pll25dac1_sync_n_o,
dac_cs_n_o(1) => pll25dac2_sync_n_o,
dac_clr_n_o => open, -- Not used
dac_sclk_o => pll25dac_sclk_o,
dac_din_o => pll25dac_din_o);
end generate generate_whiterabbit;
-- for now connect leds_o(4) to IPBus LOS -- for now connect leds_o(4) to IPBus LOS
--U_Extend_PPS : gc_extend_pulse --U_Extend_PPS : gc_extend_pulse
-- generic map ( -- generic map (
......
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