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Scalable MAROC Charge Sensitive Readout
Commit e1318150 authored by David Cussans's avatar David Cussans
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Minor changes following PCB checking 

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@21 e1591323-3689-4d5a-aa31-d1a7cbdc5706
parent 1bad2acc
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Showing with 30331 additions and 23204 deletions
design_files/worklib/pc049a_toplevel/physical/PC049A_DD.art
View file @ e1318150
G04 ================== begin FILE IDENTIFICATION RECORD ==================* G04 ================== begin FILE IDENTIFICATION RECORD ==================*
G04 Layout Name: pc049a_toplevel_47.brd* G04 Layout Name: pc049a_toplevel_48.brd*
G04 Film Name: PC049A_DD* G04 Film Name: PC049A_DD*
G04 File Format: Gerber RS274X* G04 File Format: Gerber RS274X*
G04 File Origin: Cadence Allegro 16.6-S014* G04 File Origin: Cadence Allegro 16.6-S014*
G04 Origin Date: Tue Feb 10 12:06:20 2015* G04 Origin Date: Wed Feb 11 18:23:25 2015*
G04 * G04 *
G04 Layer: MANUFACTURING/NCDRILL_LEGEND* G04 Layer: MANUFACTURING/NCDRILL_LEGEND*
G04 Layer: MANUFACTURING/NCDRILL_FIGURE* G04 Layer: MANUFACTURING/NCDRILL_FIGURE*
...@@ -22247,7 +22247,7 @@ Y17821750D03* ...@@ -22247,7 +22247,7 @@ Y17821750D03*
Y18050350D03* Y18050350D03*
Y18253550D03* Y18253550D03*
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X3484300Y13846650D03* X3484300Y13846650D03*
X3627500Y1129400D03* X3627500Y1129400D03*
...@@ -22445,7 +22445,7 @@ X1691000Y10193000D03* ...@@ -22445,7 +22445,7 @@ X1691000Y10193000D03*
X1684400Y10324200D03* X1684400Y10324200D03*
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X1684400Y10870300D03* X1684400Y10870300D03*
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...@@ -22528,7 +22528,7 @@ Y10209900D03* ...@@ -22528,7 +22528,7 @@ Y10209900D03*
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X2014600Y10819500D03* X2014600Y10819500D03*
X1862200Y11505300D03* X1862200Y11505300D03*
......
design_files/worklib/pc049a_toplevel/physical/PC049A_L2.art
View file @ e1318150
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design_files/worklib/pc049a_toplevel/physical/PC049A_L3.art
View file @ e1318150
G04 ================== begin FILE IDENTIFICATION RECORD ==================* G04 ================== begin FILE IDENTIFICATION RECORD ==================*
G04 Layout Name: pc049a_toplevel_47.brd* G04 Layout Name: pc049a_toplevel_48.brd*
G04 Film Name: PC049A_L3* G04 Film Name: PC049A_L3*
G04 File Format: Gerber RS274X* G04 File Format: Gerber RS274X*
G04 File Origin: Cadence Allegro 16.6-S014* G04 File Origin: Cadence Allegro 16.6-S014*
G04 Origin Date: Tue Feb 10 12:07:01 2015* G04 Origin Date: Wed Feb 11 18:23:25 2015*
G04 * G04 *
G04 Layer: VIA CLASS/L3* G04 Layer: VIA CLASS/L3*
G04 Layer: PIN/L3* G04 Layer: PIN/L3*
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......
design_files/worklib/pc049a_toplevel/physical/PC049A_L5.art
View file @ e1318150
G04 ================== begin FILE IDENTIFICATION RECORD ==================* G04 ================== begin FILE IDENTIFICATION RECORD ==================*
G04 Layout Name: pc049a_toplevel_47.brd* G04 Layout Name: pc049a_toplevel_48.brd*
G04 Film Name: PC049A_L5* G04 Film Name: PC049A_L5*
G04 File Format: Gerber RS274X* G04 File Format: Gerber RS274X*
G04 File Origin: Cadence Allegro 16.6-S014* G04 File Origin: Cadence Allegro 16.6-S014*
G04 Origin Date: Tue Feb 10 12:07:02 2015* G04 Origin Date: Wed Feb 11 18:23:26 2015*
G04 * G04 *
G04 Layer: VIA CLASS/L5* G04 Layer: VIA CLASS/L5*
G04 Layer: PIN/L5* G04 Layer: PIN/L5*
...@@ -20,10 +20,11 @@ G04 ================== end FILE IDENTIFICATION RECORD ====================* ...@@ -20,10 +20,11 @@ G04 ================== end FILE IDENTIFICATION RECORD ====================*
%FSLAX25Y25*MOMM*% %FSLAX25Y25*MOMM*%
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%ADD21C,1.6002*% %ADD21C,1.6002*%
...@@ -33,8 +34,8 @@ G04 ================== end FILE IDENTIFICATION RECORD ====================* ...@@ -33,8 +34,8 @@ G04 ================== end FILE IDENTIFICATION RECORD ====================*
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%LPD*% %LPD*%
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......
design_files/worklib/pc049a_toplevel/physical/PC049A_L6.art
View file @ e1318150
G04 ================== begin FILE IDENTIFICATION RECORD ==================* G04 ================== begin FILE IDENTIFICATION RECORD ==================*
G04 Layout Name: pc049a_toplevel_47.brd* G04 Layout Name: pc049a_toplevel_48.brd*
G04 Film Name: PC049A_L6* G04 Film Name: PC049A_L6*
G04 File Format: Gerber RS274X* G04 File Format: Gerber RS274X*
G04 File Origin: Cadence Allegro 16.6-S014* G04 File Origin: Cadence Allegro 16.6-S014*
G04 Origin Date: Tue Feb 10 12:07:02 2015* G04 Origin Date: Wed Feb 11 18:23:26 2015*
G04 * G04 *
G04 Layer: VIA CLASS/L6* G04 Layer: VIA CLASS/L6*
G04 Layer: PIN/L6* G04 Layer: PIN/L6*
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......
design_files/worklib/pc049a_toplevel/physical/PC049A_SM1.art
View file @ e1318150
G04 ================== begin FILE IDENTIFICATION RECORD ==================* G04 ================== begin FILE IDENTIFICATION RECORD ==================*
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G04 Film Name: PC049A_SM1* G04 Film Name: PC049A_SM1*
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......
design_files/worklib/pc049a_toplevel/physical/PC049A_SM10.art
View file @ e1318150
G04 ================== begin FILE IDENTIFICATION RECORD ==================* G04 ================== begin FILE IDENTIFICATION RECORD ==================*
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......
design_files/worklib/pc049a_toplevel/physical/PC049A_SP1.art
View file @ e1318150
G04 ================== begin FILE IDENTIFICATION RECORD ==================* G04 ================== begin FILE IDENTIFICATION RECORD ==================*
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G04 Layer: PACKAGE GEOMETRY/PASTEMASK_TOP* G04 Layer: PACKAGE GEOMETRY/PASTEMASK_TOP*
......
design_files/worklib/pc049a_toplevel/physical/PC049A_SP10.art
View file @ e1318150
G04 ================== begin FILE IDENTIFICATION RECORD ==================* G04 ================== begin FILE IDENTIFICATION RECORD ==================*
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G04 Film Name: PC049A_SP10* G04 Film Name: PC049A_SP10*
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......
design_files/worklib/pc049a_toplevel/physical/PC049A_SS1.art
View file @ e1318150
G04 ================== begin FILE IDENTIFICATION RECORD ==================* G04 ================== begin FILE IDENTIFICATION RECORD ==================*
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......
design_files/worklib/pc049a_toplevel/physical/PC049A_SS10.art
View file @ e1318150
G04 ================== begin FILE IDENTIFICATION RECORD ==================* G04 ================== begin FILE IDENTIFICATION RECORD ==================*
G04 Layout Name: pc049a_toplevel_47.brd* G04 Layout Name: pc049a_toplevel_48.brd*
G04 Film Name: PC049A_SS10* G04 Film Name: PC049A_SS10*
G04 File Format: Gerber RS274X* G04 File Format: Gerber RS274X*
G04 File Origin: Cadence Allegro 16.6-S014* G04 File Origin: Cadence Allegro 16.6-S014*
G04 Origin Date: Tue Feb 10 12:06:45 2015* G04 Origin Date: Wed Feb 11 18:23:26 2015*
G04 * G04 *
G04 Layer: MANUFACTURING/AUTOSILK_BOTTOM* G04 Layer: MANUFACTURING/AUTOSILK_BOTTOM*
G04 Layer: BOARD GEOMETRY/CTEXT_BOTTOM* G04 Layer: BOARD GEOMETRY/CTEXT_BOTTOM*
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......
design_files/worklib/pc049a_toplevel/physical/batch_drc.log
View file @ e1318150
...@@ -2,9 +2,9 @@ ...@@ -2,9 +2,9 @@
( ) ( )
( DRC Update ) ( DRC Update )
( ) ( )
( Drawing : pc049a_toplevel_47.brd ) ( Drawing : pc049a_toplevel_48.brd )
( Software Version : 16.6S014 ) ( Software Version : 16.6S014 )
( Date/Time : Tue Feb 10 12:06:09 2015 ) ( Date/Time : Wed Feb 11 18:23:18 2015 )
( ) ( )
(---------------------------------------------------------------------) (---------------------------------------------------------------------)
...@@ -22,6 +22,6 @@ ...@@ -22,6 +22,6 @@
..... Total number of DRC errors 0 ..... Total number of DRC errors 0
..... DRC update completed, total CPU time 0:00:01 ..... DRC update completed, total CPU time 0:00:02
************************************************************************* *************************************************************************
design_files/worklib/pc049a_toplevel/physical/batch_drc.log,1
View file @ e1318150
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
( ) ( )
( Drawing : pc049a_toplevel_46.brd ) ( Drawing : pc049a_toplevel_46.brd )
( Software Version : 16.6S014 ) ( Software Version : 16.6S014 )
( Date/Time : Tue Feb 10 09:56:45 2015 ) ( Date/Time : Tue Feb 10 10:13:01 2015 )
( ) ( )
(---------------------------------------------------------------------) (---------------------------------------------------------------------)
...@@ -20,7 +20,7 @@ ...@@ -20,7 +20,7 @@
========= check standalone text 0:00:00 ========= check standalone text 0:00:00
========= check standalone rectangles 0:00:00 ========= check standalone rectangles 0:00:00
..... Total number of DRC errors 1 ..... Total number of DRC errors 0
..... DRC update completed, total CPU time 0:00:02 ..... DRC update completed, total CPU time 0:00:02
************************************************************************* *************************************************************************
......
design_files/worklib/pc049a_toplevel/physical/nc_tools_auto.txt
View file @ e1318150
0.3000 P T01 0.000000 0.000000 0.3000 P T01 0.000000 0.000000
0.3302 P T02 0.000000 0.000000 0.3302 P T02 0.000000 0.000000
0.8128 P T03 0.000000 0.000000 0.4000 P T03 0.000000 0.000000
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0.9000 P T05 0.000000 0.000000 0.8500 P T05 0.000000 0.000000
0.9144 P T06 0.000000 0.000000 0.9000 P T06 0.000000 0.000000
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1.0000 P T08 0.000000 0.000000 0.9500 P T08 0.000000 0.000000
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1.4986 P T12 0.000000 0.000000 1.3500 P T12 0.000000 0.000000
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1.5500 N T15 0.000000 0.000000 3.5560 P T15 0.000000 0.000000
4.2672 N T16 0.000000 0.000000 1.5500 N T16 0.000000 0.000000
4.2672 N T17 0.000000 0.000000
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