Commit f79f13e7 authored by David Cussans's avatar David Cussans

Checking in files before another attempted Git migration.

More firmware development:

Took copies of firmware/hdl/i2c_master_* to avoid having to pull in.

Wrote some test-benches for data mux code:
dummyMarocADC_behavioural.vhd
marocTimeStampMuxArray_tb.vhd
marocTimeStampMux_tb.vhd
marocTriggerTimeStampArray_tb.vhd
marocTriggerTimeStamp_tb.vhd

Added pick-and-place information to BoM



git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@47 e1591323-3689-4d5a-aa31-d1a7cbdc5706
parent 9ce72440
This diff is collapsed.
TITLE: Bill of Materials
DATE: 04/14/2016
DESIGN: pc049a_db
TEMPLATE: /projects/HEP_Instrumentation/cad/tools/cadence_templates/spreadsheet-format_1per_line.bom
CALLOUT:
Part Name,Ref Des,Qty,PART_NUMBER,PART_DESCRIPTION,OL_COMMENTS,KL_COMMENTS,PL_COMMENTS
"CAPN4I-100NF,16V,X7R,CKCA43",CN16,1,CKCA43X7R1C104M,?,?,?,?
"CAPN4I-100NF,16V,X7R,CKCA43",CN15,1,CKCA43X7R1C104M,?,?,?,?
"CAPN4I-100NF,16V,X7R,CKCA43",CN14,1,CKCA43X7R1C104M,?,?,?,?
"CAPN4I-100NF,16V,X7R,CKCA43",CN13,1,CKCA43X7R1C104M,?,?,?,?
"CAPN4I-100NF,16V,X7R,CKCA43",CN12,1,CKCA43X7R1C104M,?,?,?,?
"CAPN4I-100NF,16V,X7R,CKCA43",CN11,1,CKCA43X7R1C104M,?,?,?,?
"CAPN4I-100NF,16V,X7R,CKCA43",CN10,1,CKCA43X7R1C104M,?,?,?,?
"CAPN4I-100NF,16V,X7R,CKCA43",CN9,1,CKCA43X7R1C104M,?,?,?,?
"CAPN4I-100NF,16V,X7R,CKCA43",CN8,1,CKCA43X7R1C104M,?,?,?,?
"CAPN4I-100NF,16V,X7R,CKCA43",CN7,1,CKCA43X7R1C104M,?,?,?,?
"CAPN4I-100NF,16V,X7R,CKCA43",CN6,1,CKCA43X7R1C104M,?,?,?,?
"CAPN4I-100NF,16V,X7R,CKCA43",CN5,1,CKCA43X7R1C104M,?,?,?,?
"CAPN4I-100NF,16V,X7R,CKCA43",CN4,1,CKCA43X7R1C104M,?,?,?,?
"CAPN4I-100NF,16V,X7R,CKCA43",CN3,1,CKCA43X7R1C104M,?,?,?,?
"CAPN4I-100NF,16V,X7R,CKCA43",CN2,1,CKCA43X7R1C104M,?,?,?,?
"CAPN4I-100NF,16V,X7R,CKCA43",CN1,1,CKCA43X7R1C104M,?,?,?,?
COAX-PLEMO00D,PX62,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX61,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX54,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX53,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX64,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX63,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX56,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX55,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX58,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX57,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX50,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX49,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX60,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX59,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX52,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX51,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX46,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX45,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX38,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX37,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX48,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX47,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX40,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX39,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX42,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX41,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX34,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX33,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX44,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX43,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX36,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX35,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX30,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX29,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX22,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX21,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX32,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX31,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX24,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX23,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX26,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX25,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX18,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX17,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX28,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX27,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX20,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX19,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX14,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX13,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX6,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX5,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX16,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX15,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX8,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX7,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX10,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX9,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX2,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX1,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX12,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX11,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX4,1,EPA.00.250.NTN,?,?,?,?
COAX-PLEMO00D,PX3,1,EPA.00.250.NTN,?,?,?,?
CON150P-QSS75_01FDA,J1,1,QSS-075-01-F-D-A,?,?,?,?
R4ISMD_1206-180,RZ16,1,307-0141,?,?,?,?
R4ISMD_1206-180,RZ15,1,307-0141,?,?,?,?
R4ISMD_1206-180,RZ14,1,307-0141,?,?,?,?
R4ISMD_1206-180,RZ13,1,307-0141,?,?,?,?
R4ISMD_1206-180,RZ12,1,307-0141,?,?,?,?
R4ISMD_1206-180,RZ11,1,307-0141,?,?,?,?
R4ISMD_1206-180,RZ10,1,307-0141,?,?,?,?
R4ISMD_1206-180,RZ9,1,307-0141,?,?,?,?
R4ISMD_1206-180,RZ8,1,307-0141,?,?,?,?
R4ISMD_1206-180,RZ7,1,307-0141,?,?,?,?
R4ISMD_1206-180,RZ6,1,307-0141,?,?,?,?
R4ISMD_1206-180,RZ5,1,307-0141,?,?,?,?
R4ISMD_1206-180,RZ4,1,307-0141,?,?,?,?
R4ISMD_1206-180,RZ3,1,307-0141,?,?,?,?
R4ISMD_1206-180,RZ2,1,307-0141,?,?,?,?
R4ISMD_1206-180,RZ1,1,307-0141,?,?,?,?
TVS_DIODE_ARRAY_SP3010_UDFN-SP3010-04UTG,D16,1,SP3010-04UTG,?,?,?,?
TVS_DIODE_ARRAY_SP3010_UDFN-SP3010-04UTG,D15,1,SP3010-04UTG,?,?,?,?
TVS_DIODE_ARRAY_SP3010_UDFN-SP3010-04UTG,D14,1,SP3010-04UTG,?,?,?,?
TVS_DIODE_ARRAY_SP3010_UDFN-SP3010-04UTG,D13,1,SP3010-04UTG,?,?,?,?
TVS_DIODE_ARRAY_SP3010_UDFN-SP3010-04UTG,D12,1,SP3010-04UTG,?,?,?,?
TVS_DIODE_ARRAY_SP3010_UDFN-SP3010-04UTG,D11,1,SP3010-04UTG,?,?,?,?
TVS_DIODE_ARRAY_SP3010_UDFN-SP3010-04UTG,D10,1,SP3010-04UTG,?,?,?,?
TVS_DIODE_ARRAY_SP3010_UDFN-SP3010-04UTG,D9,1,SP3010-04UTG,?,?,?,?
TVS_DIODE_ARRAY_SP3010_UDFN-SP3010-04UTG,D8,1,SP3010-04UTG,?,?,?,?
TVS_DIODE_ARRAY_SP3010_UDFN-SP3010-04UTG,D7,1,SP3010-04UTG,?,?,?,?
TVS_DIODE_ARRAY_SP3010_UDFN-SP3010-04UTG,D6,1,SP3010-04UTG,?,?,?,?
TVS_DIODE_ARRAY_SP3010_UDFN-SP3010-04UTG,D5,1,SP3010-04UTG,?,?,?,?
TVS_DIODE_ARRAY_SP3010_UDFN-SP3010-04UTG,D4,1,SP3010-04UTG,?,?,?,?
TVS_DIODE_ARRAY_SP3010_UDFN-SP3010-04UTG,D3,1,SP3010-04UTG,?,?,?,?
TVS_DIODE_ARRAY_SP3010_UDFN-SP3010-04UTG,D2,1,SP3010-04UTG,?,?,?,?
TVS_DIODE_ARRAY_SP3010_UDFN-SP3010-04UTG,D1,1,SP3010-04UTG,?,?,?,?
TOTAL, ,113, , , , ,
\t (46:40:57) allegro 16.6-2015 S055 (v16-6-112EH) Linux I32
\t (46:40:57) Journal start - Thu Feb 18 12:01:04 2016
\t (46:40:57) Host=fortis.phy.bris.ac.uk User=phdgc Pid=27642 CPUs=4
\t (46:40:57) CmdLine= /software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055//tools/pcb/bin/allegro.exe
\t (46:40:57)
\d (46:40:57) Design opened: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_db/physical/pc049a_lemo_db_12.brd
\i (46:40:57) ifp
\i (46:41:04) zoom out 1
\i (46:41:04) setwindow pcb
\i (46:41:04) zoom out 6.9427 -31.5851
\t (46:41:04) Grids are drawn 1.6000, 1.6000 apart for enhanced viewability.
\i (46:41:04) trapsize 14257
\i (46:41:04) zoom out 1
\i (46:41:04) setwindow pcb
\i (46:41:04) zoom out 7.2279 -31.5851
\t (46:41:04) Grids are drawn 3.2000, 3.2000 apart for enhanced viewability.
\i (46:41:04) trapsize 28514
\i (46:41:04) zoom out 1
\i (46:41:04) setwindow pcb
\i (46:41:04) zoom out 109.4609 6.2657
\i (46:41:04) trapsize 36740
\i (46:41:05) zoom in 1
\i (46:41:05) setwindow pcb
\i (46:41:05) zoom in 224.1233 80.7952
\t (46:41:05) Grids are drawn 1.6000, 1.6000 apart for enhanced viewability.
\i (46:41:05) trapsize 18370
\i (46:41:05) zoom in 1
\i (46:41:05) setwindow pcb
\i (46:41:05) zoom in 224.1233 80.7952
\t (46:41:05) Grids are drawn 0.8000, 0.8000 apart for enhanced viewability.
\i (46:41:05) trapsize 9185
\i (46:41:05) zoom out 1
\i (46:41:05) setwindow pcb
\i (46:41:05) zoom out 224.1233 80.6115
\t (46:41:05) Grids are drawn 1.6000, 1.6000 apart for enhanced viewability.
\i (46:41:05) trapsize 18370
\i (46:41:06) zoom out 1
\i (46:41:06) setwindow pcb
\i (46:41:06) zoom out 224.1233 80.2441
\t (46:41:06) Grids are drawn 3.2000, 3.2000 apart for enhanced viewability.
\i (46:41:06) trapsize 36740
\i (46:41:11) zoom points
\t (46:41:11) Pick 1st corner of the new window.
\i (46:41:11) pick -90.3718 91.0824
\t (46:41:11) last pick: -90.3718 91.0824
\t (46:41:11) Pick to complete the window.
\i (46:41:12) pick 38.2185 -60.2867
\t (46:41:12) last pick: 38.2185 -60.2867
\t (46:41:12) Grids are drawn 1.6000, 1.6000 apart for enhanced viewability.
\i (46:41:12) trapsize 11114
\i (46:41:12) ifp
\i (46:41:15) show element
\i (46:41:19) pick grid -64.8102 72.1890
\t (46:41:19) last pick: -64.8000 72.2000
\i (46:41:27) prmed
\i (46:41:29) setwindow form.prmedit
\i (46:41:29) FORM prmedit text
\i (46:41:31) FORM prmedit text_setup_button
\i (46:41:38) setwindow form.textblock
\i (46:41:38) FORM textblock cancel
\i (46:41:42) setwindow pcb
\i (46:41:42) show element
\i (46:41:43) pick grid -65.9216 71.7445
\t (46:41:43) last pick: -65.9000 71.7000
\i (46:41:50) prmed
\i (46:41:52) setwindow form.prmedit
\i (46:41:52) FORM prmedit text_setup_button
\i (46:41:59) setwindow form.textblock
\i (46:41:59) FORM textblock 9 photoplot_width 0.5000
\i (46:42:00) FORM textblock done
\i (46:42:02) setwindow form.prmedit
\i (46:42:02) FORM prmedit done
\i (46:42:02) setwindow pcb
\i (46:42:02) ifp
\i (46:42:06) zoom points
\t (46:42:06) Pick 1st corner of the new window.
\i (46:42:07) pick -73.2566 79.5241
\t (46:42:07) last pick: -73.2566 79.5241
\t (46:42:07) Pick to complete the window.
\i (46:42:07) pick -66.1439 64.8540
\t (46:42:07) last pick: -66.1439 64.8540
\i (46:42:07) trapsize 1077
\i (46:42:07) ifp
\i (46:42:10) zoom out
\i (46:42:10) setwindow pcb
\i (46:42:10) zoom out -57.8325 72.1783
\t (46:42:10) Grids are drawn 0.2000, 0.2000 apart for enhanced viewability.
\i (46:42:10) trapsize 2154
\i (46:42:10) zoom out
\i (46:42:10) setwindow pcb
\i (46:42:10) zoom out -57.8325 72.1783
\t (46:42:10) Grids are drawn 0.4000, 0.4000 apart for enhanced viewability.
\i (46:42:10) trapsize 4308
\i (46:42:11) zoom out
\i (46:42:11) setwindow pcb
\i (46:42:11) zoom out -57.8326 72.1782
\t (46:42:11) Grids are drawn 0.8000, 0.8000 apart for enhanced viewability.
\i (46:42:11) trapsize 8617
\i (46:42:13) roam x 96
\i (46:42:13) roam x 96
\i (46:42:13) roam x 96
\i (46:42:13) roam x 96
\i (46:42:13) roam y 96
\i (46:42:13) roam y 96
\i (46:42:14) roam y 96
\i (46:42:14) roam y 96
\i (46:42:14) roam y 96
\i (46:42:14) roam y 96
\i (46:42:14) roam y 96
\i (46:42:14) roam y 96
\i (46:42:15) roam y 96
\i (46:42:15) roam y 96
\i (46:42:15) roam y 96
\i (46:42:15) roam y 96
\i (46:42:15) roam y 96
\i (46:42:15) roam y 96
\i (46:42:16) roam y -96
\i (46:42:16) roam y -96
\i (46:42:16) roam y -96
\i (46:42:16) roam y -96
\i (46:42:17) roam y -96
\i (46:42:17) roam y -96
\i (46:42:17) roam y -96
\i (46:42:17) roam y -96
\i (46:42:17) roam y -96
\i (46:42:17) roam y -96
\i (46:42:24) pick grid -127.9598 32.4568
\t (46:42:24) last pick: -128.0000 32.5000
\i (46:42:25) zoom out
\i (46:42:25) setwindow pcb
\i (46:42:25) zoom out -24.9029 39.0056
\t (46:42:25) Grids are drawn 1.6000, 1.6000 apart for enhanced viewability.
\i (46:42:25) trapsize 17234
\i (46:42:25) zoom out
\i (46:42:25) setwindow pcb
\i (46:42:25) zoom out -24.9029 39.0055
\t (46:42:25) Grids are drawn 3.2000, 3.2000 apart for enhanced viewability.
\i (46:42:25) trapsize 36740
\i (46:42:25) zoom out
\i (46:42:25) setwindow pcb
\i (46:42:25) zoom out 243.2281 -2.2374
\i (46:42:25) trapsize 36740
\i (46:42:29) zoom points
\t (46:42:29) Pick 1st corner of the new window.
\i (46:42:29) pick -122.7031 96.2260
\t (46:42:29) last pick: -122.7031 96.2260
\t (46:42:29) Pick to complete the window.
\i (46:42:30) pick -27.1789 -97.7616
\t (46:42:30) last pick: -27.1789 -97.7616
\t (46:42:30) Grids are drawn 1.6000, 1.6000 apart for enhanced viewability.
\i (46:42:30) trapsize 14243
\i (46:42:30) ifp
\i (46:42:34) plot
(46:42:34) Loading plot.cxt
(46:42:34) Loading fputil.cxt
\i (46:42:37) setwindow form.fpfileplot
\i (46:42:37) FORM fpfileplot printtofile YES
\i (46:42:54) FORM fpfileplot fileprintfilename ~/pc049a_lemo_breakout.eps
\i (46:42:54) FORM fpfileplot done
\i (46:42:54) create plotunix /tmp/#Taaaaad27642.tmp
\w (46:42:54) WARNING(SPMHMF-233): Plotting is being performed with non-vectorized text.
\w (46:42:54) WARNING(SPMHSK-57): No 'allegro_plot_param.stipples' file found for color plotting.
\i (46:55:33) setwindow pcb
\i (46:55:33) zoom in 1
\i (46:55:33) setwindow pcb
\i (46:55:33) zoom in -10.1846 -39.3659
\t (46:55:33) Grids are drawn 0.8000, 0.8000 apart for enhanced viewability.
\i (46:55:33) trapsize 7121
\i (46:55:33) zoom in 1
\i (46:55:33) setwindow pcb
\i (46:55:33) zoom in -10.1845 -39.3659
\t (46:55:33) Grids are drawn 0.4000, 0.4000 apart for enhanced viewability.
\i (46:55:33) trapsize 3561
\i (46:55:34) zoom out 1
\i (46:55:34) setwindow pcb
\i (46:55:34) zoom out -10.1133 -39.5083
\t (46:55:34) Grids are drawn 0.8000, 0.8000 apart for enhanced viewability.
\i (46:55:34) trapsize 7121
\i (46:55:55) show element
\i (46:56:02) setwindow form.find
\i (46:56:02) FORM find symbols YES
\i (46:56:03) setwindow pcb
\i (46:56:03) pick grid 13.5299 -2.6193
\t (46:56:03) last pick: 13.5000 -2.6000
\i (46:56:26) pick grid 84.8866 -34.8082
\t (46:56:26) last pick: 84.9000 -34.8000
\i (46:56:27) roam y 96
\i (46:56:27) roam y 96
\i (46:56:27) roam y 96
\i (46:56:27) roam y 96
\i (46:56:27) roam y 96
\i (46:56:27) roam y 96
\i (46:56:28) roam y -96
\i (46:56:28) roam y -96
\i (46:56:30) roam y -96
\i (46:56:30) roam y -96
\i (46:56:33) roam y 96
\i (46:56:33) roam y 96
\i (46:56:45) roam y -96
\i (46:56:45) roam y -96
\i (46:56:46) roam y 96
\i (46:56:46) roam y 96
\i (47:02:15) pick grid 10.2541 -74.3192
\t (47:02:15) last pick: 10.3000 -74.3000
\i (47:02:16) roam y -96
\i (47:02:16) roam y -96
\i (47:02:17) roam x -96
\i (47:02:17) roam x -96
\i (47:02:18) roam x -96
\i (47:02:18) roam x -96
\i (47:02:19) roam y -96
\i (47:02:19) roam y -96
\i (47:02:20) roam y -96
\i (47:02:20) roam y -96
\i (47:02:21) roam y -96
\i (47:02:21) roam y -96
\i (47:02:21) roam y -96
\i (47:02:21) roam y -96
\i (47:02:21) roam y -96
\i (47:02:21) roam y -96
\i (47:02:22) roam y -96
\i (47:02:22) roam y -96
\i (75:51:42) exit
\e (75:51:43) Do you want to save the changes you made to pc049a_lemo_db_12.brd?
\i (75:51:45) fillin no
\t (75:51:47) Journal end - Fri Feb 19 17:11:53 2016
\t (00:00:51) allegro 16.6-2015 S055 (v16-6-112EH) Linux I32
\t (00:00:51) Journal start - Thu Apr 14 12:38:47 2016
\t (00:00:51) Host=voltar.phy.bris.ac.uk User=phdgc Pid=1851 CPUs=8
\t (00:00:51) CmdLine= /software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055/tools/pcb/bin/allegro.exe -proj /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/pc049a_lemo_daughter_board.cpm -product Concept_HDL_studio -mpssession phdgc_ProjectMgr7061 -mpshost voltar.phy.bris.ac.uk
\t (00:00:51)
\d (00:00:51) Design opened: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_db/physical/pc049a_lemo_db_4l_13.brd
\i (00:00:51) ifp
\i (00:00:54) zoom fit
\t (00:00:54) Grids are drawn 1.6000, 1.6000 apart for enhanced viewability.
\i (00:00:54) trapsize 10169
\i (00:43:42) trapsize 13752
\i (00:44:11) exit
\t (00:44:12) Journal end - Thu Apr 14 13:22:07 2016
\t (00:02:09) allegro 16.5 S030 (v16-5-13BU) Linux IA32
\t (00:02:09) Journal start - Mon Mar 24 18:25:07 2014
\t (00:02:09) Host=calgary.phy.bris.ac.uk User=phdgc Pid=10809 CPUs=4
\t (00:02:09)
\d (00:02:09) Database opened: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_lemo_daughter_board/physical/pc049a_lemo_daughter_board_blank.brd
\i (00:02:10) generaledit
\i (00:02:12) open
\i (00:03:07) fillin "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_db/physical/pc049a_lemo_db_04.brd"
\i (00:03:07) cd "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_db/physical"
\t (00:03:07) Opening existing design...
\i (00:03:07) trapsize 8585
\t (00:03:08) Journal end - Mon Mar 24 18:26:06 2014
\t (00:00:21) allegro 16.6-2015 S055 (v16-6-112EH) Linux I32
\t (00:00:21) Journal start - Thu Apr 14 12:38:17 2016
\t (00:00:21) Host=voltar.phy.bris.ac.uk User=phdgc Pid=1851 CPUs=8
\t (00:00:21) CmdLine= /software/CAD/Cadence/2015-16/RHELx86/SPB_16.60.055/tools/pcb/bin/allegro.exe -proj /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/pc049a_lemo_daughter_board.cpm -product Concept_HDL_studio -mpssession phdgc_ProjectMgr7061 -mpshost voltar.phy.bris.ac.uk
\t (00:00:21)
\t (00:00:21) Opening existing design...
\i (00:00:24) fillin yes
\d (00:00:24) Design opened: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_lemo_daughter_board/physical/pc049a_lemo_daughter_board_blank.brd
\i (00:00:26) trapsize 13353
\i (00:00:26) trapsize 13113
\i (00:00:27) trapsize 13394
\i (00:00:27) trapsize 11830
\i (00:00:27) trapsize 11830
\i (00:00:28) ifp
\i (00:00:30) open
\i (00:00:50) fillin "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_db/physical/pc049a_lemo_db_4l_13.brd"
\i (00:00:50) cd "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/design_files/worklib/pc049a_db/physical"
\t (00:00:50) Opening existing design...
\t (00:00:50) Grids are drawn 1.6000, 1.6000 apart for enhanced viewability.
\t (00:00:50) Grids are drawn 0.4000, 0.4000 apart for enhanced viewability.
\i (00:00:50) trapsize 3077
\t (00:00:50) Journal end - Thu Apr 14 12:38:46 2016
--=============================================================================
--! @file dataMux_rtl.vhd
--=============================================================================
--! Standard library
library IEEE;
--! Standard packages
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
--! Package containing type definition and constants for MAROC interface
--use work.maroc.ALL;
--! Package containing type definition and constants for IPBUS
use work.ipbus.all;
--! Use UNISIM for Xilix primitives
Library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- unit name: dataMux_rtl (dataMux / rtl)
--
--! @brief connects to the output of multiple FIFOs, multiplexs data and pushes
--! into circular dual-port-ram buffer
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 30\3\2016
--
--! @version v0.1
--
--! @details
--!
--! <b>Dependencies:</b>\n
--! Instantiates dataMuxFSM
--!
--! <b>References:</b>\n
--! referenced by dataMux \n
--!
--! <b>Modified by:</b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
--!
-------------------------------------------------------------------------------
--! @todo
--
---------------------------------------------------------------------------------
entity dataMux is
generic (
g_ADDRWIDTH : positive := 12; --! size of circular buffer
g_BUSWIDTH : positive := 32 --! IPBUS data width
);
port (
clk_i : in std_logic; --! clock. rising edge active.
);
end entity dataMux;
architecture rtl of dataMux is
begin -- architecture rtl
end architecture rtl;
This diff is collapsed.
This diff is collapsed.
----------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<
----------------------------------------------------------------------
--///////////////////////////////////////////////////////////////////
--// ////
--// WISHBONE rev.B2 compliant I2C Master registers ////
--// ////
--// ////
--// Author: Richard Herveille ////
--// richard@asics.ws ////
--// www.asics.ws ////
--// ////
--// Downloaded from: http://www.opencores.org/projects/i2c/ ////
--// ////
--///////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2001 Richard Herveille ////
--// richard@asics.ws ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer.////
--// ////
--// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
--// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
--// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
--// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
--// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
--// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
--// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
--// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
--// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
--// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
--// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
--// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
--// POSSIBILITY OF SUCH DAMAGE. ////
--// ////
--///////////////////////////////////////////////////////////////////
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2008 - 2010 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
-- Disclaimer:
--
-- This VHDL or Verilog source code is intended as a design reference
-- which illustrates how these types of functions can be implemented.
-- It is the user's responsibility to verify their design for
-- consistency and functionality through the use of formal
-- verification methods. Lattice Semiconductor provides no warranty
-- regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 503-268-8001 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: techsupport@latticesemi.com
--
-- --------------------------------------------------------------------
-- Code Revision History :
-- --------------------------------------------------------------------
-- Ver: | Author |Mod. Date |Changes Made:
-- V1.0 |K.P. | 7/09 | Initial ver for VHDL
-- | converted from LSC ref design RD1046
-- --------------------------------------------------------------------
-- --------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity i2c_master_registers is
port (
wb_clk_i : in std_logic;
rst_i : in std_logic;
wb_rst_i : in std_logic;
wb_dat_i : in std_logic_vector(7 downto 0);
wb_adr_i : in std_logic_vector(2 downto 0);
wb_wacc : in std_logic;
i2c_al : in std_logic;
i2c_busy : in std_logic;
done : in std_logic;
irxack : in std_logic;
prer : out std_logic_vector(15 downto 0); -- clock prescale register
ctr : out std_logic_vector(7 downto 0); -- control register
txr : out std_logic_vector(7 downto 0); -- transmit register
cr : out std_logic_vector(7 downto 0); -- command register
sr : out std_logic_vector(7 downto 0) -- status register
);
end;
architecture arch of i2c_master_registers is
signal ctr_int : std_logic_vector(7 downto 0);
signal cr_int : std_logic_vector(7 downto 0);
signal al : std_logic; -- status register arbitration lost bit
signal rxack : std_logic; -- received aknowledge from slave
signal tip : std_logic; -- transfer in progress
signal irq_flag : std_logic; -- interrupt pending flag
begin
-- generate prescale regisres, control registers, and transmit register
process(wb_clk_i,rst_i)
begin
if (rst_i = '0') then
prer <= (others => '1');
ctr_int <= (others => '0');
txr <= (others => '0');
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
prer <= (others => '1');
ctr_int <= (others => '0');
txr <= (others => '0');
elsif (wb_wacc = '1') then
case (wb_adr_i) is
when "000" => prer(7 downto 0) <= wb_dat_i;
when "001" => prer(15 downto 8) <= wb_dat_i;
when "010" => ctr_int <= wb_dat_i;
when "011" => txr <= wb_dat_i;
when others => NULL;
end case;
end if;
end if;
end process;
ctr <= ctr_int;
-- generate command register (special case)
process(wb_clk_i,rst_i)
begin
if (rst_i = '0') then
cr_int <= (others => '0');
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
cr_int <= (others => '0');
elsif (wb_wacc = '1') then
if ((ctr_int(7) = '1') AND (wb_adr_i = "100")) then
cr_int <= wb_dat_i;
end if;
else
if ((done = '1') OR (i2c_al = '1')) then
cr_int(7 downto 4) <= "0000"; -- clear command b
end if; -- or when aribitr
cr_int(2 downto 1) <= "00"; -- reserved bits
cr_int(0) <= '0'; -- clear IRQ_ACK b
end if;
end if;
end process;
cr <= cr_int;
-- generate status register block + interrupt request signal
-- each output will be assigned to corresponding sr register locations on top level
process(wb_clk_i,rst_i)
begin
if (rst_i = '0') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
else
al <= i2c_al OR (al AND NOT(cr_int(7)));
rxack <= irxack;
tip <= (cr_int(5) OR cr_int(4));
irq_flag <= (done OR i2c_al OR irq_flag) AND NOT(cr_int(0)); -- interrupt request flag is always generated
end if;
end if;
end process;
sr(7) <= rxack;
sr(6) <= i2c_busy;
sr(5) <= al;
sr(4 downto 2) <= "000"; -- reserved
sr(1) <= tip;
sr(0) <= irq_flag;
end arch;
This diff is collapsed.
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
## variables #############################
PWD := $(shell pwd)
MODELSIM_INI_PATH := /software/CAD/Mentor/2014_2015/HDS_2013.1b/questasim
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := ../hdl/pc049a_demo_tb.vhd \
../../top/pc049a/demo/pc049a_top.vhd \
../../IPBus/firmware/ethernet/sim/eth_mac_sim.vhd \
../../hdl/IPBusInterfaceGTP_rtl.vhd \