Commit f862dbf7 authored by David Cussans's avatar David Cussans

Adding last of PCB files and some of firmware

git-svn-id: https://svn2.phy.bris.ac.uk/svn/uob-hep-pc049a/trunk@16 e1591323-3689-4d5a-aa31-d1a7cbdc5706
parent c879f7f8
{ Machine generated file created by SPI }
{ Last modified was 15:22:02 Wednesday, May 07, 2014 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
START_GLOBAL
view_pcb './worklib/pc049a_4lemos/physical'
design_name 'pc049a_4lemos'
design_library 'uob_hep_pc049a_lib'
library 'uob_hep_pc049a_lib' 'bris_cds_analogue' 'bris_cds_connectors' 'bris_cds_discrete' 'bris_cds_logic' 'bris_cds_memory' 'bris_cds_pld' 'bris_cds_special' 'bris_cds_standard' 'bris_cds_switches' 'cn74lv' 'cn74tiac' 'cn75als' 'cncmos' 'cnconnector' 'cndiscrete' 'cnpassive' 'cnpld' 'cnpower' 'cnspecial' 'cnstandard' 'cnvlsi' 'standard' 'cnlinear'
temp_dir 'temp'
cpm_version '16.5'
session_name 'ProjectMgr58303345'
ppt '$BRIS_CDSLIB/cds_analogue/cds_analogue.ptf' '$BRIS_CDSLIB/cds_connectors/cds_connectors.ptf' '$BRIS_CDSLIB/cds_logic/cds_logic.ptf' '$BRIS_CDSLIB/cds_pld/cds_pld.ptf' '$BRIS_CDSLIB/cds_special/cds_special.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnconnector.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cndiscrete.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnpassive.ptf'
EXCLUDE_PPT
INCLUDE_PPT
cdsprop_file ''
log_file ''
physical_path './worklib/pc049a_4lemos/physical'
expand_with_errors 'OFF'
END_GLOBAL
START_CONCEPTHDL
LOGIC_GRID_SIZE '0.050'
DOC_GRID_SIZE '0.050'
CHECK_VOLTAGE_ON_HDL 'OFF'
PLOT_FIT_TO_PAGE 'ON'
PLOT_FONT 'Arial'
HPF_PLOTTER 'postscriptbw'
HPF_FONT 'native'
HPF_SPEC_PLOT_PAGESIZE 'YES'
HPF_BATCH 'YES'
HPF_PLOT_FILE_LOCATION '/home/phdgc'
HPF_PLOT_FILE_NAME 'pc049a_4lemos1.ps'
PLOTTER_FACILITY 'HPF'
PLOT_EDGE_TO_EDGE 'ON'
PAPER_SIZE '9'
PAPER_ORIENTATION '1'
PAPER_SOURCE '15'
WPLOTTER_NAME ''
HPF_PLOT_PAGESIZE 'A4'
HPF_PAGESCALETYPE 'PAGESIZE'
HPF_PAGESIZE 'A4'
HPF_SCALEFACTOR '0.000000'
END_CONCEPTHDL
START_PKGRXL
comp_def_prop 'ALT_SYMBOLS' 'JEDEC_TYPE' 'MERGE_NC_PINS' 'MERGE_POWER_PINS' 'NC_PINS' 'PINCOUNT' 'POWER_GROUP' 'POWER_PINS'
comp_inst_prop 'DEFAULT_SIGNAL_MODEL' 'GROUP' 'REUSE_ID' 'REUSE_INSTANCE' 'REUSE_NAME' 'ROOM' 'SIGNAL_MODEL' 'VOLT_TEMP_SIGNAL_MODEL'
regenerate_physical_net_name 'OFF'
electrical_constraints 'ON'
overwrite_constraints 'OFF'
USE_SUBDESIGN
FORCE_SUBDESIGN
GEN_SUBDESIGN 'pc049a_4lemos'
FILTER_PROPERTY
PASS_PROPERTY
FILTER_CONFLICTING_PROP
END_PKGRXL
START_DESIGNSYNC
replace_symbol '1'
etch_removal 'NO'
ignore_fixed 'NO'
create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'pc049a_4lemos_03.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
END_DESIGNSYNC
START_BOMHDL
last_output_file '/projects/HEP_Instrumentation/cad/designs/uob_hep_pc049a/trunk/design_files/worklib/pc049a_4lemos/bom/pc049a_4lemos.csv'
last_template_file '/projects/HEP_Instrumentation/cad/tools/cadence_templates/spreadsheet-format.bom'
last_standard_option '1'
last_what_to_output '0'
last_variant_file ''
last_ss_delimiter 'Colon :'
use_filters '0'
last_callout_file ''
last_variant ''
END_BOMHDL
START_VXL
run_directory './worklib/pc049a_4lemos/cfg_verilog/sim1'
END_VXL
START_ECSET_MODELS
retain_existing_xnets_and_diffpairs 'NO'
END_ECSET_MODELS
START_VARIANT
last_variant_file 'variant.dat'
last_edit_type '2'
last_sorted_column 'REFDES'
pref_status_name 'Pref'
sort_style '0'
annotation_property_name 'VARIANT'
annotation_property_value '*'
annotation_DNIproperty_value 'DNI'
columns 'REFDES' 'CDS_VAR_STATUS' 'PART_NAME' 'PART_NUMBER'
END_VARIANT
START_ALLEGRO
hdl_padpath '.' 'symbols' '..' '../symbols' '$CADENCE_INST_DIR/share/pcb/pcb_lib/symbols' '$CADENCE_INST_DIR/share/pcb/allegrolib/symbols' '/projects/HEP_Instrumentation/cad/ral_cdslib/lib_psd15.x/pads' '/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/pads' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/padstacks/padstack_smd' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/padstacks/padstacks/padstack3'
hdl_psmpath '.' 'symbols' '..' '../symbols' '$CADENCE_INST_DIR/share/pcb/pcb_lib/symbols' '$CADENCE_INST_DIR/share/pcb/allegrolib/symbols' '/projects/HEP_Instrumentation/cad/ral_cdslib/lib_psd15.x/symbols' '/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/symbols' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/connector' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/discrete'
hdl_topology_template_path '.' 'templates' '..' '../templates' '$CADENCE_INST_DIR/share/pcb/pcb_lib/templates' '$CADENCE_INST_DIR/share/pcb/allegrolib/templates'
END_ALLEGRO
{ Machine generated file created by SPI }
{ Last modified was 15:05:37 Monday, March 17, 2014 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
START_GLOBAL
view_pcb './worklib/pc049a_lemo_daughter_board/physical'
design_name 'pc049a_lemo_daughter_board'
design_library 'uob_hep_pc049a_lib'
library 'uob_hep_pc049a_lib' 'bris_cds_analogue' 'bris_cds_connectors' 'bris_cds_discrete' 'bris_cds_logic' 'bris_cds_memory' 'bris_cds_pld' 'bris_cds_special' 'bris_cds_standard' 'bris_cds_switches' 'cn74lv' 'cn74tiac' 'cn75als' 'cncmos' 'cnconnector' 'cndiscrete' 'cnpassive' 'cnpld' 'cnpower' 'cnspecial' 'cnstandard' 'cnvlsi' 'standard' 'cnlinear'
temp_dir 'temp'
cpm_version '16.5'
session_name 'ProjectMgr58303345'
ppt '$BRIS_CDSLIB/cds_analogue/cds_analogue.ptf' '$BRIS_CDSLIB/cds_connectors/cds_connectors.ptf' '$BRIS_CDSLIB/cds_logic/cds_logic.ptf' '$BRIS_CDSLIB/cds_pld/cds_pld.ptf' '$BRIS_CDSLIB/cds_special/cds_special.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnconnector.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cndiscrete.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnpassive.ptf'
EXCLUDE_PPT
INCLUDE_PPT
cdsprop_file ''
log_file ''
physical_path './worklib/pc049a_lemo_daughter_board/physical'
expand_with_errors 'OFF'
END_GLOBAL
START_CONCEPTHDL
LOGIC_GRID_SIZE '0.050'
DOC_GRID_SIZE '0.050'
CHECK_VOLTAGE_ON_HDL 'OFF'
PLOT_FIT_TO_PAGE 'ON'
PLOT_FONT 'Arial'
HPF_PLOTTER 'postscriptbw'
HPF_FONT 'native'
HPF_SPEC_PLOT_PAGESIZE 'YES'
HPF_BATCH 'YES'
HPF_PLOT_FILE_LOCATION '/home/phdgc'
HPF_PLOT_FILE_NAME 'pc049a_lemo_daughter_board1.ps'
PLOTTER_FACILITY 'HPF'
PLOT_EDGE_TO_EDGE 'ON'
PAPER_SIZE '9'
PAPER_ORIENTATION '1'
PAPER_SOURCE '15'
WPLOTTER_NAME ''
HPF_PLOT_PAGESIZE 'A4'
HPF_PAGESCALETYPE 'PAGESIZE'
HPF_PAGESIZE 'A4'
HPF_SCALEFACTOR '0.000000'
END_CONCEPTHDL
START_PKGRXL
comp_def_prop 'ALT_SYMBOLS' 'JEDEC_TYPE' 'MERGE_NC_PINS' 'MERGE_POWER_PINS' 'NC_PINS' 'PINCOUNT' 'POWER_GROUP' 'POWER_PINS'
comp_inst_prop 'DEFAULT_SIGNAL_MODEL' 'GROUP' 'REUSE_ID' 'REUSE_INSTANCE' 'REUSE_NAME' 'ROOM' 'SIGNAL_MODEL' 'VOLT_TEMP_SIGNAL_MODEL'
repackage 'ON'
regenerate_physical_net_name 'OFF'
electrical_constraints 'OFF'
overwrite_constraints 'OFF'
USE_SUBDESIGN 'pc049a_4lemos'
FORCE_SUBDESIGN
GEN_SUBDESIGN
FILTER_PROPERTY
PASS_PROPERTY
FILTER_CONFLICTING_PROP
END_PKGRXL
START_DESIGNSYNC
replace_symbol '2'
etch_removal 'NO'
ignore_fixed 'NO'
create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'pc049a_lemo_daughter_board_27.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
END_DESIGNSYNC
START_BOMHDL
last_output_file '/projects/HEP_Instrumentation/cad/designs/uob_hep_pc049a/trunk/design_files/worklib/pc049a_lemo_daughter_board/bom/pc049a_lemo_daughter_board.csv'
last_template_file '/projects/HEP_Instrumentation/cad/tools/cadence_templates/spreadsheet-format.bom'
last_standard_option '1'
last_what_to_output '0'
last_variant_file ''
last_ss_delimiter 'Colon :'
use_filters '0'
last_callout_file ''
last_variant ''
END_BOMHDL
START_VXL
run_directory './worklib/pc049a_lemo_daughter_board/cfg_verilog/sim1'
END_VXL
START_ECSET_MODELS
retain_existing_xnets_and_diffpairs 'NO'
END_ECSET_MODELS
START_VARIANT
last_variant_file 'variant.dat'
last_edit_type '2'
last_sorted_column 'REFDES'
pref_status_name 'Pref'
sort_style '0'
annotation_property_name 'VARIANT'
annotation_property_value '*'
annotation_DNIproperty_value 'DNI'
columns 'REFDES' 'CDS_VAR_STATUS' 'PART_NAME' 'PART_NUMBER'
END_VARIANT
START_ALLEGRO
hdl_padpath '.' 'symbols' '..' '../symbols' '$CADENCE_INST_DIR/share/pcb/pcb_lib/symbols' '$CADENCE_INST_DIR/share/pcb/allegrolib/symbols' '/projects/HEP_Instrumentation/cad/ral_cdslib/lib_psd15.x/pads' '/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/pads' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/padstacks/padstack_smd' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/padstacks/padstacks/padstack3'
hdl_psmpath '.' 'symbols' '..' '../symbols' '$CADENCE_INST_DIR/share/pcb/pcb_lib/symbols' '$CADENCE_INST_DIR/share/pcb/allegrolib/symbols' '/projects/HEP_Instrumentation/cad/ral_cdslib/lib_psd15.x/symbols' '/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/symbols' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/connector' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/discrete'
hdl_topology_template_path '.' 'templates' '..' '../templates' '$CADENCE_INST_DIR/share/pcb/pcb_lib/templates' '$CADENCE_INST_DIR/share/pcb/allegrolib/templates'
END_ALLEGRO
{ Machine generated file created by SPI }
{ Last modified was 12:25:02 Thursday, May 08, 2014 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
START_GLOBAL
design_name 'pc049a_db'
design_library 'uob_hep_pc049a_lib'
library 'uob_hep_pc049a_lib' 'cnpassive' 'cndiscrete' 'cnconnector' 'bris_cds_standard' 'cnpower' 'cnstandard' 'standard'
temp_dir 'temp'
cpm_version '16.5'
session_name 'ProjectMgr27973'
ppt '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnconnector.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnpassive.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cndiscrete.ptf'
physical_path './worklib/pc049a_db/physical'
cdsprop_file ''
END_GLOBAL
START_PKGRXL
regenerate_physical_net_name 'OFF'
electrical_constraints 'ON'
overwrite_constraints 'OFF'
force_subdesign 'pc049a_4lemos'
END_PKGRXL
START_DESIGNSYNC
replace_symbol '1'
etch_removal 'NO'
ignore_fixed 'NO'
create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'pc049a_lemo_db_08.brd'
END_DESIGNSYNC
START_CONSTRAINT_MGR
EDIT_PHYSICAL_SPACING_CONSTRAINTS 'ON'
END_CONSTRAINT_MGR
{ Machine generated file created by SPI }
{ Last modified was 09:32:14 Friday, January 17, 2014 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
START_GLOBAL
design_name 'pc049a_test'
design_library 'uob_hep_pc049a_lib'
library 'bris_cds_analogue' 'bris_cds_connectors' 'bris_cds_discrete' 'bris_cds_logic' 'bris_cds_memory' 'bris_cds_pld' 'bris_cds_special' 'bris_cds_standard' 'bris_cds_switches' 'cn100e' 'cn10e' 'cn10el' 'cn10k' 'cn10kh' 'cn74lv' 'cn74tiac' 'cn75als' 'cncmos' 'cnconnector' 'cndiscrete' 'cnfast' 'cngaas' 'cninterface' 'cnlinear' 'cnmech' 'cnmemory' 'cnmicro' 'cnpassive' 'cnpld' 'cnpower' 'cnspecial' 'cnstandard' 'cnvlsi' 'standard' 'uob_hep_pc049a_lib'
temp_dir 'temp'
cpm_version '16.5'
session_name 'ProjectMgr4478'
END_GLOBAL
START_CONSTRAINT_MGR
EDIT_PHYSICAL_SPACING_CONSTRAINTS 'ON'
END_CONSTRAINT_MGR
--
-- Dummy block for data I/O
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
-- Packages for IPBus
LIBRARY work;
USE work.ipbus.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ExpansionIO is
generic (
g_NEXPANSION_BITS : positive := 16);
port (
-- IPBus
ipbus_clk_i: in STD_LOGIC;
ipbus_reset_i: in STD_LOGIC;
ipbus_wbus_i: in ipb_wbus;
ipbus_rbus_o: out ipb_rbus;
-- Data....
lvds_left_data_p_b, lvds_left_data_n_b : out std_logic_vector(g_NEXPANSION_BITS-1 downto 0);
lvds_left_clk_p_b, lvds_left_clk_n_b : in std_logic; -- clock for data on left hand I/O
lvds_right_data_p_b, lvds_right_data_n_b : out std_logic_vector(g_NEXPANSION_BITS-1 downto 0);
lvds_right_clk_p_b, lvds_right_clk_n_b : in std_logic -- clock for data on left hand I/O
);
end entity ExpansionIO;
architecture rtl of ExpansionIO is
signal s_spydata, s_ctrl_reg: std_logic_vector(31 downto 0);
signal s_data_direction : std_logic := '0'; -- 1 = left to right ( left rx,
-- right tx ),
-- 0 = right to left ( right rx
-- left tx )
signal s_left_counter , s_right_counter : unsigned( g_NEXPANSION_BITS-1 downto 0) := ( others => '0');
signal s_data_right_from_connector ,
s_data_right_to_connector ,
s_data_left_from_connector ,
s_data_left_to_connector ,
s_data_r1 , s_data_r2 , s_data_r3: std_logic_vector(g_NEXPANSION_BITS-1 downto 0);
signal s_right_clk_from_connector,
s_right_clk_to_connector,
s_left_clk_from_connector,
s_left_clk_to_connector , s_data_clk : std_logic;
begin -- architecture rtl
controlReg: entity work.ipbus_ctrlreg
port map(
clk => ipbus_clk_i,
reset => ipbus_reset_i,
ipbus_in => ipbus_wbus_i,
ipbus_out => ipbus_rbus_o,
d => s_spydata,
q => s_ctrl_reg
);
s_data_direction <= s_ctrl_reg(0);
--
gen_iobuf: for dataBit in 0 to g_NEXPANSION_BITS-1 generate
cmp_IOBUFDS_left : OBUFDS
generic map (
IOSTANDARD => "DEFAULT"
)
port map (
O => lvds_left_data_p_b(dataBit), -- Diff_p inout (connect directly to top-level port)
OB => lvds_left_data_n_b(dataBit), -- Diff_n inout (connect directly to top-level port)
I => s_data_left_to_connector(dataBit) -- Buffer input
);
cmp_IOBUFDS_right : OBUFDS
generic map (
IOSTANDARD => "DEFAULT"
)
port map (
O => lvds_right_data_p_b(dataBit), -- Diff_p inout (connect directly to top-level port)
OB => lvds_right_data_n_b(dataBit), -- Diff_n inout (connect directly to top-level port)
I => s_data_right_to_connector(dataBit) -- Buffer input
);
end generate gen_iobuf;
cmp_IOBUFDS_left_clk : IBUFGDS
generic map (
IOSTANDARD => "DEFAULT",
DIFF_TERM => TRUE
)
port map (
O => s_left_clk_from_connector, -- Buffer output
I => lvds_left_clk_p_b, -- Diff_p inout (connect directly to top-level port)
IB => lvds_left_clk_n_b -- Diff_n inout (connect directly to top-level port)
);
cmp_IOBUFDS_right_clk : IBUFGDS
generic map (
IOSTANDARD => "DEFAULT",
DIFF_TERM => TRUE
)
port map (
O => s_right_clk_from_connector, -- Buffer output
I => lvds_right_clk_p_b, -- Diff_p inout (connect directly to top-level port)
IB => lvds_right_clk_n_b -- Diff_n inout (connect directly to top-level port)
);
-- purpose: output counter
-- type : combinational
-- inputs : s_left_clk_from_connector
-- outputs:
p_register_left_data: process (s_left_clk_from_connector) is
begin -- process p_register_data
if rising_edge(s_left_clk_from_connector) then
s_left_counter <= s_left_counter + 1;
s_data_left_to_connector <= std_logic_vector(s_left_counter);
end if;
end process p_register_left_data;
-- purpose: output counter
-- type : combinational
-- inputs : s_left_clk_from_connector
-- outputs:
p_register_right_data: process (s_right_clk_from_connector) is
begin -- process p_register_data
if rising_edge(s_right_clk_from_connector) then
s_right_counter <= s_right_counter + 1;
s_data_right_to_connector <= std_logic_vector(s_right_counter);
end if;
end process p_register_right_data;
end architecture rtl;
--
-- Dummy block for data I/O
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
-- Packages for IPBus
LIBRARY work;
USE work.ipbus.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ExpansionIO is
generic (
g_NEXPANSION_BITS : positive := 16);
port (
-- IPBus
ipbus_clk_i: in STD_LOGIC;
ipbus_reset_i: in STD_LOGIC;
ipbus_wbus_i: in ipb_wbus;
ipbus_rbus_o: out ipb_rbus;
-- Data....
lvds_left_data_p_b, lvds_left_data_n_b : out std_logic_vector(g_NEXPANSION_BITS-1 downto 0);
lvds_left_clk_p_b, lvds_left_clk_n_b : in std_logic; -- clock for data on left hand I/O
lvds_right_data_p_b, lvds_right_data_n_b : out std_logic_vector(g_NEXPANSION_BITS-1 downto 0);
lvds_right_clk_p_b, lvds_right_clk_n_b : in std_logic -- clock for data on left hand I/O
);
end entity ExpansionIO;
architecture rtl of ExpansionIO is
signal s_spydata, s_ctrl_reg: std_logic_vector(31 downto 0);
signal s_data_direction : std_logic := '0'; -- 1 = left to right ( left rx,
-- right tx ),
-- 0 = right to left ( right rx
-- left tx )
signal s_data_right_from_connector ,
s_data_right_to_connector ,
s_data_left_from_connector ,
s_data_left_to_connector ,
s_data_r1 , s_data_r2 , s_data_r3: std_logic_vector(g_NEXPANSION_BITS-1 downto 0);
signal s_right_clk_from_connector,
s_right_clk_to_connector,
s_left_clk_from_connector,
s_left_clk_to_connector , s_data_clk : std_logic;
begin -- architecture rtl
controlReg: entity work.ipbus_ctrlreg
port map(
clk => ipbus_clk_i,
reset => ipbus_reset_i,
ipbus_in => ipbus_wbus_i,
ipbus_out => ipbus_rbus_o,
d => s_spydata,
q => s_ctrl_reg
);
s_data_direction <= s_ctrl_reg(0);
--
gen_iobuf: for dataBit in 0 to g_NEXPANSION_BITS-1 generate
-- -- Take T low and output is enabled, ie. is output
--cmp_IOBUFDS_left : IOBUFDS
-- generic map (
-- IOSTANDARD => "BLVDS_25",
-- DIFF_TERM => TRUE
-- )
-- port map (
-- O => s_data_left_from_connector(dataBit), -- Buffer output
-- IO => lvds_left_data_p_b(dataBit), -- Diff_p inout (connect directly to top-level port)
-- IOB => lvds_left_data_n_b(dataBit), -- Diff_n inout (connect directly to top-level port)
-- I => s_data_left_to_connector(dataBit), -- Buffer input
-- T => s_data_direction -- 3-state enable input. Take high to be a
-- -- receiver only.
-- );
--cmp_IOBUFDS_right : IOBUFDS
-- generic map (
-- IOSTANDARD => "BLVDS_25",
-- DIFF_TERM => TRUE
-- )
-- port map (
-- O => s_data_right_from_connector(dataBit), -- Buffer output
-- IO => lvds_right_data_p_b(dataBit), -- Diff_p inout (connect directly to top-level port)
-- IOB => lvds_right_data_n_b(dataBit), -- Diff_n inout (connect directly to top-level port)
-- I => s_data_right_to_connector(dataBit), -- Buffer input
-- T => not s_data_direction -- 3-state enable input. Take high to be a
-- -- receiver only.
-- );
cmp_IOBUFDS_left : IBUFDS
generic map (
IOSTANDARD => "DEFAULT",
DIFF_TERM => TRUE
)
port map (
O => s_data_left_from_connector(dataBit), -- Buffer output
I => lvds_left_data_p_b(dataBit), -- Diff_p inout (connect directly to top-level port)
IB => lvds_left_data_n_b(dataBit) -- Diff_n inout (connect directly to top-level port)
);
cmp_IOBUFDS_right : OBUFDS
generic map (
IOSTANDARD => "DEFAULT"
)
port map (
O => lvds_right_data_p_b(dataBit), -- Diff_p inout (connect directly to top-level port)
OB => lvds_right_data_n_b(dataBit), -- Diff_n inout (connect directly to top-level port)
I => s_data_right_to_connector(dataBit) -- Buffer input
);
end generate gen_iobuf;
--cmp_IOBUFDS_left_clk : IOBUFDS
-- generic map (
-- IOSTANDARD => "BLVDS_25",
-- DIFF_TERM => TRUE
-- )
-- port map (
-- O => s_left_clk_from_connector, -- Buffer output
-- IO => lvds_left_clk_p_b, -- Diff_p inout (connect directly to top-level port)
-- IOB => lvds_left_clk_n_b, -- Diff_n inout (connect directly to top-level port)
-- I => s_left_clk_to_connector, -- Buffer input
-- T => s_data_direction -- 3-state enable input. Take high to be a
-- -- receiver only.
-- );
-- cmp_IOBUFDS_right_clk : IOBUFDS
-- generic map (
-- IOSTANDARD => "BLVDS_25",
-- DIFF_TERM => TRUE
-- )
-- port map (
-- O => s_right_clk_from_connector, -- Buffer output
-- IO => lvds_right_clk_p_b, -- Diff_p inout (connect directly to top-level port)
-- IOB => lvds_right_clk_n_b, -- Diff_n inout (connect directly to top-level port)
-- I => s_right_clk_to_connector, -- Buffer input
-- T => not s_data_direction -- 3-state enable input. Take high to be a
-- -- receiver only.
-- );
cmp_IOBUFDS_left_clk : IBUFDS
generic map (
IOSTANDARD => "DEFAULT",
DIFF_TERM => TRUE
)
port map (
O => s_left_clk_from_connector, -- Buffer output
I => lvds_left_clk_p_b, -- Diff_p inout (connect directly to top-level port)
IB => lvds_left_clk_n_b -- Diff_n inout (connect directly to top-level port)
);
cmp_IOBUFDS_right_clk : OBUFDS
generic map (
IOSTANDARD => "DEFAULT"
)
port map (
O => lvds_right_clk_p_b, -- Diff_p inout (connect directly to top-level port)
OB => lvds_right_clk_n_b, -- Diff_n inout (connect directly to top-level port)
I => s_right_clk_to_connector -- Buffer input
);
-- multiplex the clocks....
-- 0 = take data from right I/O ( right = rx )
--BUFGMUX_inst: BUFGMUX
--generic map
--(
-- CLK_SEL_TYPE => "SYNC" Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
-- )
--port map
--(O => s_data_clk,
-- I0 => s_right_clk_from_connector, (S=0)
-- I1 => s_left_clk_from_connector, (S=1)
-- S => s_data_direction Clock buffer select
-- );
s_data_clk <= s_left_clk_from_connector;
-- purpose: register data and transfer from left <--> right connector
-- type : combinational
-- inputs : s_data_clk
-- outputs:
p_register_data: process (s_data_clk) is
begin -- process p_register_data
if rising_edge(s_data_clk) then
case s_data_direction is
-- 0 => right is rx, left is tx
when '0' =>
s_data_r1 <= s_data_right_from_connector;
s_data_left_to_connector <= s_data_r3;
-- 1 => left is rx , right is tx
when '1' =>
s_data_r1 <= s_data_left_from_connector;
s_data_right_to_connector <= s_data_r3;
when others => null;
end case;
s_data_r2 <= s_data_r1;
s_data_r3 <= s_data_r2;
end if;
end process p_register_data;
end architecture rtl;
--
-- Dummy block for data I/O
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- Packages for IPBus
LIBRARY work;
USE work.ipbus.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ExpansionIO is
generic (
g_NEXPANSION_BITS : positive := 16);
port (
-- IPBus
ipbus_clk_i: in STD_LOGIC;
ipbus_reset_i: in STD_LOGIC;
ipbus_wbus_i: in ipb_wbus;
ipbus_rbus_o: out ipb_rbus;
-- Data....
lvds_left_data_p_b, lvds_left_data_n_b : in std_logic_vector(g_NEXPANSION_BITS-1 downto 0);
lvds_left_clk_p_b, lvds_left_clk_n_b : in std_logic; -- clock for data on left hand I/O
lvds_right_data_p_b, lvds_right_data_n_b : out std_logic_vector(g_NEXPANSION_BITS-1 downto 0);
lvds_right_clk_p_b, lvds_right_clk_n_b : out std_logic -- clock for data on left hand I/O
);
end entity ExpansionIO;
architecture rtl of ExpansionIO is
signal s_spydata, s_ctrl_reg: std_logic_vector(31 downto 0);
signal s_data_direction : std_logic := '0'; -- 1 = left to right ( left rx,
-- right tx ),
-- 0 = right to left ( right rx
-- left tx )
signal s_data_right_from_connector ,
s_data_right_to_connector ,
s_data_left_from_connector ,
s_data_left_to_connector ,
s_data_r1 , s_data_r2 , s_data_r3: std_logic_vector(g_NEXPANSION_BITS-1 downto 0);
signal s_right_clk_from_connector,
s_right_clk_to_connector,
s_left_clk_from_connector,
s_left_clk_to_connector , s_data_clk : std_logic;
begin -- architecture rtl