Commit fd606682 authored by David Cussans's avatar David Cussans

Repairing code-rot in Maroc example firmware.

Modified "demo" to work with newer WhiteRabbit core

Write "simple" example that just uses IPBus and Maroc cores ( no White Rabbit )

Started on the path towards "build out of the box" but not there yet.
parent d79561af
----------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<
----------------------------------------------------------------------
--///////////////////////////////////////////////////////////////////
--// ////
--// WISHBONE rev.B2 compliant I2C Master bit-controller ////
--// ////
--// ////
--// Author: Richard Herveille ////
--// richard@asics.ws ////
--// www.asics.ws ////
--// ////
--// Downloaded from: http://www.opencores.org/projects/i2c/ ////
--// ////
--///////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2001 Richard Herveille ////
--// richard@asics.ws ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer.////
--// ////
--// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
--// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
--// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
--// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
--// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
--// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
--// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
--// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
--// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
--// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
--// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
--// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
--// POSSIBILITY OF SUCH DAMAGE. ////
--// ////
--///////////////////////////////////////////////////////////////////
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2008 - 2010 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
-- Disclaimer:
--
-- This VHDL or Verilog source code is intended as a design reference
-- which illustrates how these types of functions can be implemented.
-- It is the user's responsibility to verify their design for
-- consistency and functionality through the use of formal
-- verification methods. Lattice Semiconductor provides no warranty
-- regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 503-268-8001 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: techsupport@latticesemi.com
--
-- --------------------------------------------------------------------
-- Code Revision History :
-- --------------------------------------------------------------------
-- Ver: | Author |Mod. Date |Changes Made:
-- V1.0 |K.P. | 7/09 | Initial ver for VHDL
-- | converted from LSC ref design RD1046
-- --------------------------------------------------------------------
--/////////////////////////////////////
--// Bit controller section
--/////////////////////////////////////
--//
--// Translate simple commands into SCL/SDA transitions
--// Each command has 5 states, A/B/C/D/idle
--//
--// start: SCL ~~~~~~~~~~\____
--// SDA ~~~~~~~~\______
--// x | A | B | C | D | i
--//
--// repstart SCL ____/~~~~\___
--// SDA __/~~~\______
--// x | A | B | C | D | i
--//
--// stop SCL ____/~~~~~~~~
--// SDA ==\____/~~~~~
--// x | A | B | C | D | i
--//
--//- write SCL ____/~~~~\____
--// SDA ==X=========X=
--// x | A | B | C | D | i
--//
--//- read SCL ____/~~~~\____
--// SDA XXXX=====XXXX
--// x | A | B | C | D | i
--//
--
--// Timing: Normal mode Fast mode
--///////////////////////////////////////////////////////////////////////
--// Fscl 100KHz 400KHz
--// Th_scl 4.0us 0.6us High period of SCL
--// Tl_scl 4.7us 1.3us Low period of SCL
--// Tsu:sta 4.7us 0.6us setup time for a repeated start condition
--// Tsu:sto 4.0us 0.6us setup time for a stop conditon
--// Tbuf 4.7us 1.3us Bus free time between a stop and start condition
--//
--
-- --------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity i2c_master_bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
ena : in std_logic; -- core enable signal
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command complete acknowledge
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- i2c bus arbitration lost
din : in std_logic;
dout : out std_logic;
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable (active low)
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable (active low)
);
end;
architecture arch of i2c_master_bit_ctrl is
--attribute UGROUP:string;
--attribute UGROUP of arch : label is "bit_group";
signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
signal dscl_oen : std_logic; -- delayed scl_oen
signal sda_chk : std_logic; -- check SDA output (Multi-master arbitration)
signal clk_en : std_logic; -- clock generation signals
signal slave_wait : std_logic;
-- bus status controller signals
signal dSCL,dSDA : std_logic;
signal sta_condition : std_logic;
signal sto_condition : std_logic;
signal cmd_stop : std_logic;
signal cnt : std_logic_vector(15 downto 0); -- clock divider counter
signal scl_oen_int : std_logic;
signal sda_oen_int : std_logic;
signal busy_int : std_logic;
signal al_int : std_logic;
-- state machine variable
signal c_state : std_logic_vector(16 downto 0);
constant idle : std_logic_vector(16 downto 0) := "00000000000000000";
constant start_a : std_logic_vector(16 downto 0) := "00000000000000001";
constant start_b : std_logic_vector(16 downto 0) := "00000000000000010";
constant start_c : std_logic_vector(16 downto 0) := "00000000000000100";
constant start_d : std_logic_vector(16 downto 0) := "00000000000001000";
constant start_e : std_logic_vector(16 downto 0) := "00000000000010000";
constant stop_a : std_logic_vector(16 downto 0) := "00000000000100000";
constant stop_b : std_logic_vector(16 downto 0) := "00000000001000000";
constant stop_c : std_logic_vector(16 downto 0) := "00000000010000000";
constant stop_d : std_logic_vector(16 downto 0) := "00000000100000000";
constant rd_a : std_logic_vector(16 downto 0) := "00000001000000000";
constant rd_b : std_logic_vector(16 downto 0) := "00000010000000000";
constant rd_c : std_logic_vector(16 downto 0) := "00000100000000000";
constant rd_d : std_logic_vector(16 downto 0) := "00001000000000000";
constant wr_a : std_logic_vector(16 downto 0) := "00010000000000000";
constant wr_b : std_logic_vector(16 downto 0) := "00100000000000000";
constant wr_c : std_logic_vector(16 downto 0) := "01000000000000000";
constant wr_d : std_logic_vector(16 downto 0) := "10000000000000000";
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "1000";
begin
scl_oen <= scl_oen_int;
sda_oen <= sda_oen_int;
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
process(clk)
begin
if rising_edge(clk) then
dscl_oen <= scl_oen_int;
end if;
end process;
slave_wait <= '1' when ((dscl_oen = '1') AND (sSCL = '0')) else '0';
-- generate clk enable signal
process(clk,nReset)
begin
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1';
elsif rising_edge(clk) then
if (rst = '1') then
cnt <= (others => '0');
clk_en <= '1';
elsif ((cnt = "0000000000000000") OR (ena = '0')) then
cnt <= clk_cnt;
clk_en <= '1';
elsif (slave_wait = '1') then
cnt <= cnt;
clk_en <= '0';
else
cnt <= cnt - '1';
clk_en <= '0';
end if;
end if;
end process;
-- synchronize SCL and SDA inputs
-- reduce metastability risc
process(clk,nReset)
begin
if (nReset = '0') then
sSCL <= '1';
sSDA <= '1';
dSCL <= '1';
dSDA <= '1';
elsif rising_edge(clk) then
if (rst = '1') then
sSCL <= '1';
sSDA <= '1';
dSCL <= '1';
dSDA <= '1';
else
dSCL <= sSCL;
dSDA <= sSDA;
-- Don't need to treat 'H' if separate I and O
-- if ((scl_i = '1') OR (scl_i = 'H')) then
if (scl_i = '1') then
sSCL <= '1';
else
sSCL <= '0';
end if;
-- if ((sda_i = '1') OR (sda_i = 'H')) then
if (sda_i = '1') then
sSDA <= '1';
else
sSDA <= '0';
end if;
end if;
end if;
end process;
-- detect start condition => detect falling edge on SDA while SCL is high
-- detect stop condition => detect rising edge on SDA while SCL is high
process(clk,nReset)
begin
if (nReset = '0') then
sta_condition <= '0';
sto_condition <= '0';
elsif rising_edge(clk) then
if (rst = '1') then
sta_condition <= '0';
sto_condition <= '0';
else
sta_condition <= NOT(sSDA) AND dSDA AND sSCL;
sto_condition <= sSDA AND NOT(dSDA) AND sSCL;
end if;
end if;
end process;
-- generate i2c bus busy signal
process(clk,nReset)
begin
if (nReset = '0') then
busy_int <= '0';
elsif rising_edge(clk) then
if (rst = '1') then
busy_int <= '0';
else
busy_int <= (sta_condition OR busy_int) AND NOT(sto_condition);
end if;
end if;
end process;
busy <= busy_int;
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
-- 2) stop detected while not requested
process(clk,nReset)
begin
if (nReset = '0') then
cmd_stop <= '0';
elsif rising_edge(clk) then
if (rst = '1') then
cmd_stop <= '0';
elsif (clk_en = '1') then
if (cmd = I2C_CMD_STOP) then
cmd_stop <= '1';
else
cmd_stop <= '0';
end if;
end if;
end if;
end process;
process(clk,nReset)
begin
if (nReset = '0') then
al_int <= '0';
elsif rising_edge(clk) then
if (rst = '1') then
al_int <= '0';
else
if (((sda_chk = '1') AND (sSDA = '0') AND (sda_oen_int = '1')) OR ((c_state /= idle) AND (sto_condition = '1') AND (cmd_stop = '0'))) then
al_int <= '1';
else
al_int <= '0';
end if;
end if;
end if;
end process;
al <= al_int;
-- generate dout signal (store SDA on rising edge of SCL)
process(clk)
begin
if rising_edge(clk) then
if ((sSCL = '1') AND (dSCL = '0')) then
dout <= sSDA;
end if;
end if;
end process;
--generate state machine
process(clk,nReset)
begin
if (nReset = '0') then
c_state <= idle;
cmd_ack <= '0';
scl_oen_int <= '1';
sda_oen_int <= '1';
sda_chk <= '0';
elsif rising_edge(clk) then
if ((rst = '1') OR (al_int = '1')) then
c_state <= idle;
cmd_ack <= '0';
scl_oen_int <= '1';
sda_oen_int <= '1';
sda_chk <= '0';
else
cmd_ack <= '0'; --default no command acknowledge + assert cmd_ack only 1clk cycle
if (clk_en = '1') then
case (c_state) is
when idle =>
case (cmd) is
when I2C_CMD_START => c_state <= start_a;
when I2C_CMD_STOP => c_state <= stop_a;
when I2C_CMD_WRITE => c_state <= wr_a;
when I2C_CMD_READ => c_state <= rd_a;
when others => c_state <= idle;
end case;
scl_oen_int <= scl_oen_int; -- keep SCL in same state
sda_oen_int <= sda_oen_int; -- keep SDA in same state
sda_chk <= '0'; -- don't check SDA output
when start_a => -- start
c_state <= start_b;
scl_oen_int <= scl_oen_int; -- keep SCL in same state
sda_oen_int <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA output
when start_b =>
c_state <= start_c;
scl_oen_int <= '1'; -- set SCL high
sda_oen_int <= '1'; -- keep SDA high
sda_chk <= '0'; -- don't check SDA output
when start_c =>
c_state <= start_d;
scl_oen_int <= '1'; -- keep SCL high
sda_oen_int <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA output
when start_d =>
c_state <= start_e;
scl_oen_int <= '1'; -- keep SCL high
sda_oen_int <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA output
when start_e =>
c_state <= idle;
cmd_ack <= '1';
scl_oen_int <= '0'; -- set SCL low
sda_oen_int <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA output
when stop_a => -- stop
c_state <= stop_b;
scl_oen_int <= '0'; -- keep SCL low
sda_oen_int <= '0'; -- set SDA low
sda_chk <= '0'; -- don't check SDA output
when stop_b =>
c_state <= stop_c;
scl_oen_int <= '1'; -- set SCL high
sda_oen_int <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA output
when stop_c =>
c_state <= stop_d;
scl_oen_int <= '1'; -- keep SCL high
sda_oen_int <= '0'; -- keep SDA low
sda_chk <= '0'; -- don't check SDA output
when stop_d =>
c_state <= idle;
cmd_ack <= '1';
scl_oen_int <= '1'; -- keep SCL high
sda_oen_int <= '1'; -- set SDA high
sda_chk <= '0'; -- don't check SDA output
when rd_a => -- read
c_state <= rd_b;
scl_oen_int <= '0'; -- keep SCL low
sda_oen_int <= '1'; -- tri-state SDA
sda_chk <= '0'; -- don't check SDA output
when rd_b =>
c_state <= rd_c;
scl_oen_int <= '1'; -- set SCL high
sda_oen_int <= '1'; -- keep SDA tri-stated
sda_chk <= '0'; -- don't check SDA output
when rd_c =>
c_state <= rd_d;
scl_oen_int <= '1'; -- keep SCL high
sda_oen_int <= '1'; -- keep SDA tri-stated
sda_chk <= '0'; -- don't check SDA output
when rd_d =>
c_state <= idle;
cmd_ack <= '1';
scl_oen_int <= '0'; -- set SCL low
sda_oen_int <= '1'; -- keep SDA tri-stated
sda_chk <= '0'; -- don't check SDA output
when wr_a => -- write
c_state <= wr_b;
scl_oen_int <= '0'; -- keep SCL low
sda_oen_int <= din; -- set SDA
sda_chk <= '0'; -- don't check SDA output (SCL low)
when wr_b =>
c_state <= wr_c;
scl_oen_int <= '1'; -- set SCL high
sda_oen_int <= din; -- keep SDA
sda_chk <= '1'; -- check SDA output
when wr_c =>
c_state <= wr_d;
scl_oen_int <= '1'; -- keep SCL high
sda_oen_int <= din;
sda_chk <= '1'; -- check SDA output
when wr_d =>
c_state <= idle;
cmd_ack <= '1';
scl_oen_int <= '0'; -- set SCL low
sda_oen_int <= din;
sda_chk <= '0'; -- don't check SDA output (SCL low)
when others => NULL;
end case;
end if;
end if;
end if;
end process;
-- assign scl and sda output (always gnd)
scl_o <= '0';
sda_o <= '0';
end arch;
----------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<
----------------------------------------------------------------------
--///////////////////////////////////////////////////////////////////
--// ////
--// WISHBONE rev.B2 compliant I2C Master byte-controller ////
--// ////
--// ////
--// Author: Richard Herveille ////
--// richard@asics.ws ////
--// www.asics.ws ////
--// ////
--// Downloaded from: http://www.opencores.org/projects/i2c/ ////
--// ////
--///////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2001 Richard Herveille ////
--// richard@asics.ws ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer.////
--// ////
--// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
--// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
--// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
--// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
--// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
--// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
--// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
--// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
--// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
--// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
--// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
--// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
--// POSSIBILITY OF SUCH DAMAGE. ////
--// ////
--///////////////////////////////////////////////////////////////////
-----------------------------------------------------------------------
-- Copyright (c) 2008 - 2010 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
-- Disclaimer:
--
-- This VHDL or Verilog source code is intended as a design reference
-- which illustrates how these types of functions can be implemented.
-- It is the user's responsibility to verify their design for
-- consistency and functionality through the use of formal
-- verification methods. Lattice Semiconductor provides no warranty
-- regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 503-268-8001 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: techsupport@latticesemi.com
--
-- --------------------------------------------------------------------
-- Code Revision History :
-- --------------------------------------------------------------------
-- Ver: | Author |Mod. Date |Changes Made:
-- V1.0 |K.P. | 7/09 | Initial ver for VHDL
-- | converted from LSC ref design RD1046
-- --------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity i2c_master_byte_ctrl is
port (
clk : in std_logic; -- master clock
rst : in std_logic; -- synchronous active high reset
nReset : in std_logic; -- asynchronous active low reset
clk_cnt : in std_logic_vector(15 downto 0); -- 4x SCL
-- control inputs
start : in std_logic;
stop : in std_logic;
read : in std_logic;
write : in std_logic;
ack_in : in std_logic;
din : in std_logic_vector(7 downto 0);
-- status outputs
cmd_ack : out std_logic;
ack_out : out std_logic; -- i2c clock line input
dout : out std_logic_vector(7 downto 0);
i2c_al : in std_logic;
-- signals for bit_controller
core_cmd : out std_logic_vector(3 downto 0);
core_txd : out std_logic;
core_rxd : in std_logic;
core_ack : in std_logic
);
end;
architecture arch of i2c_master_byte_ctrl is
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "1000";
constant ST_IDLE : std_logic_vector(4 downto 0) := "00000";
constant ST_START : std_logic_vector(4 downto 0) := "00001";
constant ST_READ : std_logic_vector(4 downto 0) := "00010";
constant ST_WRITE : std_logic_vector(4 downto 0) := "00100";
constant ST_ACK : std_logic_vector(4 downto 0) := "01000";
constant ST_STOP : std_logic_vector(4 downto 0) := "10000";
signal c_state : std_logic_vector(4 downto 0);
signal go : std_logic;
signal dcnt : std_logic_vector(2 downto 0);
signal cnt_done : std_logic;
signal sr : std_logic_vector(7 downto 0); --8bit shift register
signal shift, ld : std_logic;
signal cmd_ack_int : std_logic;
begin
go <= '1' when (((read = '1') OR (write = '1') OR (stop = '1')) AND (cmd_ack_int = '0')) else '0';
dout <= sr;
-- generate shift register
process(clk,nReset)
begin
if (nReset = '0') then
sr <= (others => '0');
elsif rising_edge(clk) then
if (rst = '1') then
sr <= (others => '0');
elsif (ld = '1') then
sr <= din;
elsif (shift = '1') then
sr <= sr(6 downto 0) & core_rxd;
end if;
end if;
end process;
-- generate counter
process(clk,nReset)
begin
if (nReset = '0') then
dcnt <= (others => '0');
elsif rising_edge(clk) then
if (rst = '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
dcnt <= "111";
elsif (shift = '1') then
dcnt <= dcnt - '1';
end if;
end if;
end process;
cnt_done <= '1' when (dcnt = "000") else '0';
-- state machine
process(clk,nReset)
begin
if (nReset = '0') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
cmd_ack_int <= '0';
c_state <= ST_IDLE;
ack_out <= '0';
elsif rising_edge(clk) then
if ((rst = '1') OR (i2c_al = '1')) then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
cmd_ack_int <= '0';
c_state <= ST_IDLE;
ack_out <= '0';
else
-- initially reset all signals
core_txd <= sr(7);
shift <= '0';
ld <= '0';
cmd_ack_int <= '0';
case (c_state) is
when ST_IDLE =>
if (go = '1') then
if (start = '1') then
c_state <= ST_START;
core_cmd <= I2C_CMD_START;
elsif (read = '1') then
c_state <= ST_READ;
core_cmd <= I2C_CMD_READ;
elsif (write = '1') then
c_state <= ST_WRITE;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= ST_STOP;
core_cmd <= I2C_CMD_STOP;
end if;
ld <= '1';
end if;
when ST_START =>
if (core_ack = '1') then
if (read = '1') then
c_state <= ST_READ;
core_cmd <= I2C_CMD_READ;
else
c_state <= ST_WRITE;
core_cmd <= I2C_CMD_WRITE;
end if;
ld <= '1';
end if;
when ST_WRITE =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= ST_ACK;
core_cmd <= I2C_CMD_READ;
else
c_state <= ST_WRITE; -- stay in same state
core_cmd <= I2C_CMD_WRITE; -- write next bit
shift <= '1';
end if;
end if;
when ST_READ =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= ST_ACK;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= ST_READ; -- stay in same state
core_cmd <= I2C_CMD_READ; -- read next bit
shift <= '1';
end if;
shift <= '1';
core_txd <= ack_in;
end if;
when ST_ACK =>
if (core_ack = '1') then
if (stop = '1') then
c_state <= ST_STOP;
core_cmd <= I2C_CMD_STOP;
else
c_state <= ST_IDLE;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
cmd_ack_int <= '1';
end if;
-- assign ack_out output to bit_controller_rxd (contains last received bit)
ack_out <= core_rxd;
core_txd <= '1';
else
core_txd <= ack_in;
end if;
when ST_STOP =>
if (core_ack = '1') then
c_state <= ST_IDLE;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
cmd_ack_int <= '1';
end if;
when others => NULL;
end case;
end if;
end if;
end process;
cmd_ack <= cmd_ack_int;
end arch;
----------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<
----------------------------------------------------------------------
--///////////////////////////////////////////////////////////////////
--// ////
--// WISHBONE rev.B2 compliant I2C Master registers ////
--// ////
--// ////
--// Author: Richard Herveille ////
--// richard@asics.ws ////
--// www.asics.ws ////
--// ////
--// Downloaded from: http://www.opencores.org/projects/i2c/ ////
--// ////
--///////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2001 Richard Herveille ////
--// richard@asics.ws ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer.////
--// ////
--// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
--// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
--// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
--// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
--// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
--// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
--// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
--// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
--// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
--// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
--// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
--// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
--// POSSIBILITY OF SUCH DAMAGE. ////
--// ////
--///////////////////////////////////////////////////////////////////
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2008 - 2010 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
-- Disclaimer:
--
-- This VHDL or Verilog source code is intended as a design reference
-- which illustrates how these types of functions can be implemented.
-- It is the user's responsibility to verify their design for
-- consistency and functionality through the use of formal
-- verification methods. Lattice Semiconductor provides no warranty
-- regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 503-268-8001 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: techsupport@latticesemi.com
--
-- --------------------------------------------------------------------
-- Code Revision History :
-- --------------------------------------------------------------------
-- Ver: | Author |Mod. Date |Changes Made:
-- V1.0 |K.P. | 7/09 | Initial ver for VHDL
-- | converted from LSC ref design RD1046
-- --------------------------------------------------------------------
-- --------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity i2c_master_registers is
port (
wb_clk_i : in std_logic;
rst_i : in std_logic;
wb_rst_i : in std_logic;
wb_dat_i : in std_logic_vector(7 downto 0);
wb_adr_i : in std_logic_vector(2 downto 0);
wb_wacc : in std_logic;
i2c_al : in std_logic;
i2c_busy : in std_logic;
done : in std_logic;
irxack : in std_logic;
prer : out std_logic_vector(15 downto 0); -- clock prescale register
ctr : out std_logic_vector(7 downto 0); -- control register
txr : out std_logic_vector(7 downto 0); -- transmit register
cr : out std_logic_vector(7 downto 0); -- command register
sr : out std_logic_vector(7 downto 0) -- status register
);
end;
architecture arch of i2c_master_registers is
signal ctr_int : std_logic_vector(7 downto 0);
signal cr_int : std_logic_vector(7 downto 0);
signal al : std_logic; -- status register arbitration lost bit
signal rxack : std_logic; -- received aknowledge from slave
signal tip : std_logic; -- transfer in progress
signal irq_flag : std_logic; -- interrupt pending flag
begin
-- generate prescale regisres, control registers, and transmit register
process(wb_clk_i,rst_i)
begin
if (rst_i = '0') then
prer <= (others => '1');
ctr_int <= (others => '0');
txr <= (others => '0');
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
prer <= (others => '1');
ctr_int <= (others => '0');
txr <= (others => '0');
elsif (wb_wacc = '1') then
case (wb_adr_i) is
when "000" => prer(7 downto 0) <= wb_dat_i;
when "001" => prer(15 downto 8) <= wb_dat_i;
when "010" => ctr_int <= wb_dat_i;
when "011" => txr <= wb_dat_i;
when others => NULL;
end case;
end if;
end if;
end process;
ctr <= ctr_int;
-- generate command register (special case)
process(wb_clk_i,rst_i)
begin
if (rst_i = '0') then
cr_int <= (others => '0');
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
cr_int <= (others => '0');
elsif (wb_wacc = '1') then
if ((ctr_int(7) = '1') AND (wb_adr_i = "100")) then
cr_int <= wb_dat_i;
end if;
else
if ((done = '1') OR (i2c_al = '1')) then
cr_int(7 downto 4) <= "0000"; -- clear command b
end if; -- or when aribitr
cr_int(2 downto 1) <= "00"; -- reserved bits
cr_int(0) <= '0'; -- clear IRQ_ACK b
end if;
end if;
end process;
cr <= cr_int;
-- generate status register block + interrupt request signal
-- each output will be assigned to corresponding sr register locations on top level
process(wb_clk_i,rst_i)
begin
if (rst_i = '0') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
elsif rising_edge(wb_clk_i) then
if (wb_rst_i = '1') then
al <= '0';
rxack <= '0';
tip <= '0';
irq_flag <= '0';
else
al <= i2c_al OR (al AND NOT(cr_int(7)));
rxack <= irxack;
tip <= (cr_int(5) OR cr_int(4));
irq_flag <= (done OR i2c_al OR irq_flag) AND NOT(cr_int(0)); -- interrupt request flag is always generated
end if;
end if;
end process;
sr(7) <= rxack;
sr(6) <= i2c_busy;
sr(5) <= al;
sr(4 downto 2) <= "000"; -- reserved
sr(1) <= tip;
sr(0) <= irq_flag;
end arch;
----------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<
----------------------------------------------------------------------
--///////////////////////////////////////////////////////////////////
--// ////
--// WISHBONE rev.B2 compliant I2C Master bit-controller ////
--// ////
--// ////
--// Author: Richard Herveille ////
--// richard@asics.ws ////
--// www.asics.ws ////
--// ////
--// Downloaded from: http://www.opencores.org/projects/i2c/ ////
--// ////
--///////////////////////////////////////////////////////////////////
--// ////
--// Copyright (C) 2001 Richard Herveille ////
--// richard@asics.ws ////
--// ////
--// This source file may be used and distributed without ////
--// restriction provided that this copyright statement is not ////
--// removed from the file and that any derivative work contains ////
--// the original copyright notice and the associated disclaimer.////
--// ////
--// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
--// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
--// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
--// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
--// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
--// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
--// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
--// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
--// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
--// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
--// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
--// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
--// POSSIBILITY OF SUCH DAMAGE. ////
--// ////
--///////////////////////////////////////////////////////////////////
-- --------------------------------------------------------------------
-- >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
-- --------------------------------------------------------------------
-- Copyright (c) 2008 - 2010 by Lattice Semiconductor Corporation
-- --------------------------------------------------------------------
--
-- Disclaimer:
--
-- This VHDL or Verilog source code is intended as a design reference
-- which illustrates how these types of functions can be implemented.
-- It is the user's responsibility to verify their design for
-- consistency and functionality through the use of formal
-- verification methods. Lattice Semiconductor provides no warranty
-- regarding the use or functionality of this code.
--
-- --------------------------------------------------------------------
--
-- Lattice Semiconductor Corporation
-- 5555 NE Moore Court
-- Hillsboro, OR 97214
-- U.S.A
--
-- TEL: 1-800-Lattice (USA and Canada)
-- 503-268-8001 (other locations)
--
-- web: http://www.latticesemi.com/
-- email: techsupport@latticesemi.com
--
-- --------------------------------------------------------------------
-- Code Revision History :
-- --------------------------------------------------------------------
-- Ver: | Author |Mod. Date |Changes Made:
-- V1.0 |K.P. | 7/09 | Initial ver for VHDL
-- | converted from LSC ref design RD1046
-------------------------------------------------------------------------------
-- Changes at University of bristol:
-- V1.0A|D.G.C | 5/11 | Changed name and ports to fit OC original
-- --------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity i2c_master_top is
generic (
ARST_LVL : integer := 0
);
port (
wb_clk_i : in std_logic;
wb_rst_i : in std_logic;
arst_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(7 downto 0);
wb_dat_o : out std_logic_vector(7 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_ack_o : out std_logic;
wb_inta_o: out std_logic;
scl_pad_i: in std_logic;
scl_pad_o: out std_logic;
scl_padoen_o: out std_logic;
sda_pad_i: in std_logic;
sda_pad_o: out std_logic;
sda_padoen_o: out std_logic
-- scl : inout std_logic;
-- sda : inout std_logic
);
end;
architecture arch of i2c_master_top is
component i2c_master_bit_ctrl
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
ena : in std_logic; -- core enable signal
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command complete acknowledge
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- i2c bus arbitration lost
din : in std_logic;
dout : out std_logic;
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable (active low)
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable (active low)
);
end component;
component i2c_master_byte_ctrl
port (
clk : in std_logic; -- master clock
rst : in std_logic; -- synchronous active high reset
nReset : in std_logic; -- asynchronous active low reset
clk_cnt : in std_logic_vector(15 downto 0); -- 4x SCL
-- control inputs
start : in std_logic;
stop : in std_logic;
read : in std_logic;
write : in std_logic;
ack_in : in std_logic;
din : in std_logic_vector(7 downto 0);
-- status outputs
cmd_ack : out std_logic;
ack_out : out std_logic; -- i2c clock line input
dout : out std_logic_vector(7 downto 0);
i2c_al : in std_logic;
-- signals for bit_controller
core_cmd : out std_logic_vector(3 downto 0);
core_txd : out std_logic;
core_rxd : in std_logic;
core_ack : in std_logic
);
end component;
component i2c_master_registers
port (
wb_clk_i : in std_logic;
rst_i : in std_logic;
wb_rst_i : in std_logic;
wb_dat_i : in std_logic_vector(7 downto 0);
wb_adr_i : in std_logic_vector(2 downto 0);
wb_wacc : in std_logic;
i2c_al : in std_logic;
i2c_busy : in std_logic;
done : in std_logic;
irxack : in std_logic;
prer : out std_logic_vector(15 downto 0); -- clock prescale register
ctr : out std_logic_vector(7 downto 0); -- control register
txr : out std_logic_vector(7 downto 0); -- transmit register
cr : out std_logic_vector(7 downto 0); -- command register
sr : out std_logic_vector(7 downto 0) -- status register
);
end component;
signal prer : std_logic_vector(15 downto 0);
signal ctr : std_logic_vector(7 downto 0);
signal txr : std_logic_vector(7 downto 0);
signal rxr : std_logic_vector(7 downto 0);
signal cr : std_logic_vector(7 downto 0);
signal sr : std_logic_vector(7 downto 0);
signal done : std_logic;
signal core_en : std_logic;
signal ien : std_logic;
signal irxack : std_logic;
signal irq_flag : std_logic;
signal i2c_busy : std_logic;
signal i2c_al : std_logic;
signal core_cmd : std_logic_vector(3 downto 0);
signal core_txd : std_logic;
signal core_ack, core_rxd : std_logic;
-- Don't need these signals, since passing them through
-- component interface
--signal scl_pad_i : std_logic;
--signal scl_pad_o : std_logic;
--signal scl_padoen_o : std_logic;
--
--signal sda_pad_i : std_logic;
--signal sda_pad_o : std_logic;
--signal sda_padoen_o : std_logic;
signal rst_i : std_logic;
signal sta : std_logic;
signal sto : std_logic;
signal rd : std_logic;
signal wr : std_logic;
signal ack : std_logic;
signal iack : std_logic;
signal wb_ack_o_int : std_logic;
signal wb_wacc : std_logic;
signal acki : std_logic;
begin
-- Don't need to copy these signal - passing through
-- component interface
--scl_pad_i <= scl;
--sda_pad_i <= sda;
rst_i <= arst_i when (ARST_LVL = 0) else NOT(arst_i);
wb_wacc <= wb_cyc_i AND wb_stb_i AND wb_we_i;
sta <= cr(7);
sto <= cr(6);
rd <= cr(5);
wr <= cr(4);
ack <= cr(3);
acki <= cr(0);
core_en <= ctr(7);
ien <= ctr(6);
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o_int <= wb_cyc_i AND wb_stb_i AND NOT(wb_ack_o_int);
end if;
end process;
wb_ack_o <= wb_ack_o_int;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
case (wb_adr_i) is
when "000" => wb_dat_o <= prer(7 downto 0);
when "001" => wb_dat_o <= prer(15 downto 8);
when "010" => wb_dat_o <= ctr;
when "011" => wb_dat_o <= rxr;
when "100" => wb_dat_o <= sr;
when "101" => wb_dat_o <= txr;
when "110" => wb_dat_o <= cr;
when "111" => wb_dat_o <= "00000000";
when others => NULL;
end case;
end if;
end process;
process(wb_clk_i,rst_i)
begin
if (rst_i = '0') then
wb_inta_o <= '0';
elsif rising_edge(wb_clk_i) then
wb_inta_o <= sr(0) AND ien;
end if;
end process;
byte_controller: i2c_master_byte_ctrl port map(
clk => wb_clk_i,
rst => wb_rst_i,
nReset => rst_i,
clk_cnt => prer,
start => sta,
stop => sto,
read => rd,
write => wr,
ack_in => ack,
din => txr,
cmd_ack => done,
ack_out => irxack,
dout => rxr,
i2c_al => i2c_al,
core_cmd => core_cmd,
core_ack => core_ack,
core_txd => core_txd,
core_rxd => core_rxd);
bit_controller: i2c_master_bit_ctrl port map(
clk => wb_clk_i,
rst => wb_rst_i,
nReset => rst_i,
ena => core_en,
clk_cnt => prer,
cmd => core_cmd,
cmd_ack => core_ack,
busy => i2c_busy,
al => i2c_al,
din => core_txd,
dout => core_rxd,
scl_i => scl_pad_i,
scl_o => scl_pad_o,
scl_oen => scl_padoen_o,
sda_i => sda_pad_i,
sda_o => sda_pad_o,
sda_oen => sda_padoen_o);
registers: i2c_master_registers port map(
wb_clk_i => wb_clk_i,
rst_i => rst_i,
wb_rst_i => wb_rst_i,
wb_dat_i => wb_dat_i,
wb_wacc => wb_wacc,
wb_adr_i => wb_adr_i,
i2c_al => i2c_al,
i2c_busy => i2c_busy,
done => done,
irxack => irxack,
prer => prer,
ctr => ctr,
txr => txr,
cr => cr,
sr => sr);
-- edited from Lattice original to pass uni-directional signals
--scl <= scl_pad_o when (scl_padoen_o = '0') else 'Z';
--sda <= sda_pad_o when (sda_padoen_o = '0') else 'Z';
end arch;
This source diff could not be displayed because it is too large. You can view the blob instead.
target = "xilinx"
action = "synthesis"
fetchto = "../../../ip_cores"
syn_device = "xc6slx100t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "pc049a_top"
syn_project = "pc049a_top_simple.xise"
syn_tool = "ise"
modules = { "local" : "../../../top/pc049a/simple"
}
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
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<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx100t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
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<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|pc049a_top|rtl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../top/pc049a/simple/pc049a_top.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/pc049a_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
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<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
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<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="pc049a_top" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="pc049a_top_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="pc049a_top_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="pc049a_top_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
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<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
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<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
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<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
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<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
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<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="pc049a_top_simple" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-10-06T14:37:47" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A04838744DC34F1EA3605660AAA049BE" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<libraries/>
<files>
<file xil_pn:name="../../../top/pc049a/simple/pc049a_top.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_streamers/streamers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/timing/dmtd_phase_meas.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_streamers/gc_escape_inserter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../IPBus/firmware/ipbus_core/hdl/transactor_cfg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../../../IPBus/firmware/ipbus_core/hdl/udp_if_flat.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_packet_filter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../hdl/clocks_s6_basex.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../../IPBus/firmware/ipbus_core/hdl/udp_build_payload.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_eca/eca_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../IPBus/firmware/ipbus_core/hdl/trans_arb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_streamers/xtx_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../hdl/ipbusMarocADC_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../hdl/risingEdgeDetect_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_eca/eca_wr_time.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../IPBus/firmware/ipbus_core/hdl/udp_tx_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../hdl/ipbus_reg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../IPBus/firmware/ipbus_core/hdl/udp_dualportram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/platform/xilinx/wr_gtp_phy/gtx_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_streamers/rx_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../hdl/i2c_master_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="79"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="../../../hdl/ipbusMarocShiftReg_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_aligner.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../IPBus/firmware/ipbus_core/hdl/ipbus_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../hdl/marocInterface_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/modules/fabric/xwrf_loopback/xwrf_loopback.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../IPBus/firmware/ipbus_core/hdl/udp_dualportram_tx.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../ip_cores/wr-cores/ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../IPBus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="397"/>
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="../../../IPBus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="404"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../../../IPBus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../IPBus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<bindings>
<binding xil_pn:location="/pc049a_top" xil_pn:name="../../../top/pc049a/simple/pc049a_top.ucf"/>
</bindings>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
</project>
files = ["pc049a_top.vhd", "pc049a_top.ucf", "../../../hdl/ExpansionIO_rtl.vhd"]
modules = { "local" : ["../../../"] }
files = ["pc049a_top.vhd", "pc049a_top.ucf", "spec_reset_gen.vhd", "../../../hdl/ExpansionIO_rtl.vhd"]
modules = { "local" : ["../../../"] }
CONFIG PROHIBIT = AA20;
CONFIG PROHIBIT = AA21;
CONFIG PROHIBIT = AA3;
CONFIG PROHIBIT = AB20;
CONFIG PROHIBIT = C3;
CONFIG PROHIBIT = L1;
CONFIG PROHIBIT = V19;
CONFIG PROHIBIT = V20;
CONFIG PROHIBIT = Y19;
CONFIG PROHIBIT = Y20;
CONFIG PROHIBIT = Y4;
CONFIG VCCAUX=2.5;
NET "ADC_DAV_I" IOSTANDARD = SSTL2_I;
NET "ADC_DAV_I" LOC = W1;
NET "button1_i" IOSTANDARD = LVCMOS33;
NET "button1_i" LOC = H5;
NET "button2_i" IOSTANDARD = LVCMOS33;
NET "button2_i" LOC = H6;
NET "CK_40M_N_O" IOSTANDARD = LVDS_25;
NET "CK_40M_N_O" LOC = AB4;
NET "CK_40M_P_O" IOSTANDARD = LVDS_25;
NET "CK_40M_P_O" LOC = AA4;
NET "CK_R_O" DRIVE = 12;
NET "CK_R_O" IOSTANDARD = LVCMOS33;
NET "CK_R_O" LOC = W4;
NET "CK_R_O" SLEW = SLOW;
NET "CK_SC_O" DRIVE = 12;
NET "CK_SC_O" IOSTANDARD = LVCMOS33;
NET "CK_SC_O" LOC = V1;
NET "CK_SC_O" SLEW = SLOW;
NET "clk_125m_pllref_n_i" IOSTANDARD = LVDS_25;
NET "clk_125m_pllref_n_i" LOC = K22 | DIFF_TERM=TRUE;
NET "clk_125m_pllref_n_i" TNM_NET = "clk_125m_pllref_n_i";
NET "clk_125m_pllref_p_i" IOSTANDARD = LVDS_25;
NET "clk_125m_pllref_p_i" LOC = K21 | DIFF_TERM=TRUE;
NET "clk_125m_pllref_p_i" TNM_NET = "clk_125m_pllref_p_i";
NET "clk_20m_vcxo_i" IOSTANDARD = LVCMOS33;
NET "clk_20m_vcxo_i" LOC = L3;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
NET "CTEST_O[0]" DRIVE = 12;
NET "CTEST_O[0]" IOSTANDARD = LVCMOS33;
NET "CTEST_O[0]" LOC = E3;
NET "CTEST_O[0]" SLEW = SLOW;
NET "CTEST_O[1]" DRIVE = 12;
NET "CTEST_O[1]" IOSTANDARD = LVCMOS33;
NET "CTEST_O[1]" LOC = E1;
NET "CTEST_O[1]" SLEW = SLOW;
NET "CTEST_O[2]" DRIVE = 12;
NET "CTEST_O[2]" IOSTANDARD = LVCMOS33;
NET "CTEST_O[2]" LOC = D2;
NET "CTEST_O[2]" SLEW = SLOW;
NET "CTEST_O[3]" DRIVE = 12;
NET "CTEST_O[3]" IOSTANDARD = LVCMOS33;
NET "CTEST_O[3]" LOC = D1;
NET "CTEST_O[3]" SLEW = SLOW;
NET "CTEST_O[4]" DRIVE = 12;
NET "CTEST_O[4]" IOSTANDARD = LVCMOS33;
NET "CTEST_O[4]" LOC = C1;
NET "CTEST_O[4]" SLEW = SLOW;
NET "CTEST_O[5]" DRIVE = 12;
NET "CTEST_O[5]" IOSTANDARD = LVCMOS33;
# NET "CTEST_O[5]" LOC = B1;
NET "CTEST_O[5]" LOC = E4;
NET "CTEST_O[5]" SLEW = SLOW;
NET "dip_switch_i[0]" IOSTANDARD = LVCMOS33;
NET "dip_switch_i[0]" LOC = J6;
NET "dip_switch_i[1]" IOSTANDARD = LVCMOS33;
NET "dip_switch_i[1]" LOC = J4;
NET "dip_switch_i[2]" IOSTANDARD = LVCMOS33;
NET "dip_switch_i[2]" LOC = J3;
NET "dip_switch_i[3]" IOSTANDARD = LVCMOS33;
NET "dip_switch_i[3]" LOC = K1;
NET "D_R_O" DRIVE = 12;
NET "D_R_O" IOSTANDARD = LVCMOS33;
NET "D_R_O" LOC = V2;
NET "D_R_O" SLEW = SLOW;
NET "D_SC_O" DRIVE = 12;
NET "D_SC_O" IOSTANDARD = LVCMOS33;
NET "D_SC_O" LOC = V3;
NET "D_SC_O" SLEW = SLOW;
NET "enable_gclk_drive_o" DRIVE = 12;
NET "enable_gclk_drive_o" IOSTANDARD = LVCMOS33;
NET "enable_gclk_drive_o" LOC = T1;
NET "enable_gclk_drive_o" SLEW = SLOW;
NET "enable_globaltrig_drive_o" DRIVE = 12;
NET "enable_globaltrig_drive_o" IOSTANDARD = LVCMOS33;
NET "enable_globaltrig_drive_o" LOC = T2;
NET "enable_globaltrig_drive_o" SLEW = SLOW;
NET "EN_OTAQ_O" DRIVE = 12;
NET "EN_OTAQ_O" IOSTANDARD = LVCMOS33;
NET "EN_OTAQ_O" LOC = V5;
NET "EN_OTAQ_O" SLEW = SLOW;
#- NET "fpga_pll_ref_clk_101_n_i" LOC = F12 | DIFF_TERM=TRUE;
#- NET "fpga_pll_ref_clk_101_n_i" TNM_NET = "fpga_pll_ref_clk_101_n_i";
#- NET "fpga_pll_ref_clk_101_p_i" LOC = E12 | DIFF_TERM=TRUE;
NET "fpga_pll_ref_clk_123_n_i" LOC = D11 | DIFF_TERM=TRUE;
NET "fpga_pll_ref_clk_123_p_i" LOC = C11 | DIFF_TERM=TRUE;
NET "fpga_pll_ref_clk_123_p_i" TNM_NET = "fpga_pll_ref_clk_123_p_i";
NET "fpga_scl_b" DRIVE = 12;
NET "fpga_scl_b" IOSTANDARD = LVCMOS33;
NET "fpga_scl_b" LOC = T3;
NET "fpga_scl_b" SLEW = SLOW;
NET "fpga_sda_b" DRIVE = 12;
NET "fpga_sda_b" IOSTANDARD = LVCMOS33;
NET "fpga_sda_b" LOC = T4;
NET "fpga_sda_b" SLEW = SLOW;
NET "GPIO[0]" DRIVE = 12;
NET "GPIO[0]" IOSTANDARD = LVCMOS33;
NET "GPIO[0]" LOC = G4;
NET "GPIO[0]" SLEW = SLOW;
NET "GPIO[1]" DRIVE = 12;
NET "GPIO[1]" IOSTANDARD = LVCMOS33;
NET "GPIO[1]" LOC = G3;
NET "GPIO[1]" SLEW = SLOW;
NET "GPIO[2]" DRIVE = 12;
NET "GPIO[2]" IOSTANDARD = LVCMOS33;
NET "GPIO[2]" LOC = G1;
NET "GPIO[2]" SLEW = SLOW;
NET "GPIO[3]" DRIVE = 12;
NET "GPIO[3]" IOSTANDARD = LVCMOS33;
NET "GPIO[3]" LOC = G6;
NET "GPIO[3]" SLEW = SLOW;
NET "GPIO[4]" DRIVE = 12;
NET "GPIO[4]" IOSTANDARD = LVCMOS33;
NET "GPIO[4]" LOC = F3;
NET "GPIO[4]" SLEW = SLOW;
NET "GPIO[5]" DRIVE = 12;
NET "GPIO[5]" IOSTANDARD = LVCMOS33;
NET "GPIO[5]" LOC = F2;
NET "GPIO[5]" SLEW = SLOW;
NET "GPIO[6]" DRIVE = 12;
NET "GPIO[6]" IOSTANDARD = LVCMOS33;
NET "GPIO[6]" LOC = F1;
NET "GPIO[6]" SLEW = SLOW;
NET "GPIO[7]" IOSTANDARD = LVCMOS33;
NET "GPIO[7]" LOC = F5;
NET "GPIO[7]" PULLDOWN=true;
NET "HOLD1_O" DRIVE = 12;
NET "HOLD1_O" IOSTANDARD = LVCMOS33;
NET "HOLD1_O" LOC = Y2;
NET "HOLD1_O" SLEW = SLOW;
NET "HOLD2_O" DRIVE = 12;
NET "HOLD2_O" IOSTANDARD = LVCMOS33;
NET "HOLD2_O" LOC = AA2;
NET "HOLD2_O" SLEW = SLOW;
NET "leds_o[0]" DRIVE = 12;
NET "leds_o[0]" IOSTANDARD = LVCMOS33;
NET "leds_o[0]" LOC = H4;
NET "leds_o[0]" SLEW = SLOW;
NET "leds_o[1]" DRIVE = 12;
NET "leds_o[1]" IOSTANDARD = LVCMOS33;
NET "leds_o[1]" LOC = H3;
NET "leds_o[1]" SLEW = SLOW;
NET "leds_o[2]" DRIVE = 12;
NET "leds_o[2]" IOSTANDARD = LVCMOS33;
NET "leds_o[2]" LOC = H2;
NET "leds_o[2]" SLEW = SLOW;
NET "leds_o[3]" DRIVE = 12;
NET "leds_o[3]" IOSTANDARD = LVCMOS33;
NET "leds_o[3]" LOC = H1;
NET "leds_o[3]" SLEW = SLOW;
NET "leds_o[4]" DRIVE = 12;
NET "leds_o[4]" IOSTANDARD = LVCMOS33;
NET "leds_o[4]" LOC = J1;
NET "leds_o[4]" SLEW = SLOW;
NET "lvds_gclk_from_fpga_n_o" IOSTANDARD = LVDS_25;
NET "lvds_gclk_from_fpga_n_o" LOC = AB17;
NET "lvds_gclk_from_fpga_p_o" IOSTANDARD = LVDS_25;
NET "lvds_gclk_from_fpga_p_o" LOC = Y17;
NET "lvds_gclk_to_fpga_n_i" IOSTANDARD = LVDS_25;
NET "lvds_gclk_to_fpga_n_i" LOC = AB12;
NET "lvds_gclk_to_fpga_p_i" IOSTANDARD = LVDS_25;
NET "lvds_gclk_to_fpga_p_i" LOC = AA12;
NET "lvds_globaltrig_from_fpga_n_o" IOSTANDARD = LVDS_25;
NET "lvds_globaltrig_from_fpga_n_o" LOC = AB18;
NET "lvds_globaltrig_from_fpga_p_o" IOSTANDARD = LVDS_25;
NET "lvds_globaltrig_from_fpga_p_o" LOC = AA18;
NET "lvds_globaltrig_to_fpga_n_i" IOSTANDARD = LVDS_25;
NET "lvds_globaltrig_to_fpga_n_i" LOC = AB13;
NET "lvds_globaltrig_to_fpga_p_i" IOSTANDARD = LVDS_25;
NET "lvds_globaltrig_to_fpga_p_i" LOC = Y13;
NET "lvds_left_clk_n_b" IOSTANDARD = LVDS_25;
NET "lvds_left_clk_n_b" LOC = F15;
NET "lvds_left_clk_p_b" IOSTANDARD = LVDS_25;
NET "lvds_left_clk_p_b" LOC = F14;
NET "lvds_left_clk_p_b" TNM_NET = "lvds_left_clk_p_b";
NET "lvds_left_data_n_b[0]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[0]" LOC = A20;
NET "lvds_left_data_n_b[10]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[10]" LOC = E6;
NET "lvds_left_data_n_b[11]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[11]" LOC = D5;
NET "lvds_left_data_n_b[12]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[12]" LOC = A5;
NET "lvds_left_data_n_b[13]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[13]" LOC = A4;
NET "lvds_left_data_n_b[14]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[14]" LOC = A3;
NET "lvds_left_data_n_b[15]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[15]" LOC = A2;
NET "lvds_left_data_n_b[1]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[1]" LOC = A19;
NET "lvds_left_data_n_b[2]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[2]" LOC = D19;
NET "lvds_left_data_n_b[3]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[3]" LOC = A18;
NET "lvds_left_data_n_b[4]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[4]" LOC = A17;
NET "lvds_left_data_n_b[5]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[5]" LOC = C18;
NET "lvds_left_data_n_b[6]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[6]" LOC = F17;
NET "lvds_left_data_n_b[7]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[7]" LOC = F16;
NET "lvds_left_data_n_b[8]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[8]" LOC = F9;
NET "lvds_left_data_n_b[9]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[9]" LOC = F8;
NET "lvds_left_data_p_b[0]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[0]" LOC = B20;
NET "lvds_left_data_p_b[10]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[10]" LOC = E5;
NET "lvds_left_data_p_b[11]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[11]" LOC = D4;
NET "lvds_left_data_p_b[12]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[12]" LOC = C5;
NET "lvds_left_data_p_b[13]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[13]" LOC = C4;
NET "lvds_left_data_p_b[14]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[14]" LOC = B3;
NET "lvds_left_data_p_b[15]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[15]" LOC = B2;
NET "lvds_left_data_p_b[1]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[1]" LOC = C19;
NET "lvds_left_data_p_b[2]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[2]" LOC = D18;
NET "lvds_left_data_p_b[3]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[3]" LOC = B18;
NET "lvds_left_data_p_b[4]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[4]" LOC = C17;
NET "lvds_left_data_p_b[5]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[5]" LOC = D17;
NET "lvds_left_data_p_b[6]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[6]" LOC = G16;
NET "lvds_left_data_p_b[7]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[7]" LOC = E16;
NET "lvds_left_data_p_b[8]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[8]" LOC = G8;
NET "lvds_left_data_p_b[9]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[9]" LOC = F7;
NET "lvds_otrig_from_fpga_n_o" IOSTANDARD = LVDS_25;
NET "lvds_otrig_from_fpga_n_o" LOC = AB16;
NET "lvds_otrig_from_fpga_p_o" IOSTANDARD = LVDS_25;
NET "lvds_otrig_from_fpga_p_o" LOC = AA16;
NET "lvds_otrig_to_fpga_n_i" IOSTANDARD = LVDS_25;
NET "lvds_otrig_to_fpga_n_i" LOC = Y18;
NET "lvds_otrig_to_fpga_p_i" IOSTANDARD = LVDS_25;
NET "lvds_otrig_to_fpga_p_i" LOC = W17;
NET "lvds_right_clk_n_b" IOSTANDARD = LVDS_25;
NET "lvds_right_clk_n_b" LOC = AB11;
NET "lvds_right_clk_p_b" IOSTANDARD = LVDS_25;
NET "lvds_right_clk_p_b" LOC = Y11;
NET "lvds_right_clk_p_b" TNM_NET = "lvds_right_clk_p_b";
NET "lvds_right_data_n_b[0]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[0]" LOC = AB15;
NET "lvds_right_data_n_b[10]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[10]" LOC = AB8;
NET "lvds_right_data_n_b[11]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[11]" LOC = AB7;
NET "lvds_right_data_n_b[12]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[12]" LOC = W8;
NET "lvds_right_data_n_b[13]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[13]" LOC = Y6;
NET "lvds_right_data_n_b[14]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[14]" LOC = AB6;
NET "lvds_right_data_n_b[15]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[15]" LOC = AB5;
NET "lvds_right_data_n_b[1]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[1]" LOC = AB14;
NET "lvds_right_data_n_b[2]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[2]" LOC = Y14;
NET "lvds_right_data_n_b[3]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[3]" LOC = W13;
NET "lvds_right_data_n_b[4]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[4]" LOC = Y12;
NET "lvds_right_data_n_b[5]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[5]" LOC = W11;
NET "lvds_right_data_n_b[6]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[6]" LOC = Y10;
NET "lvds_right_data_n_b[7]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[7]" LOC = AB10;
NET "lvds_right_data_n_b[8]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[8]" LOC = AB9;
NET "lvds_right_data_n_b[9]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[9]" LOC = Y8;
NET "lvds_right_data_p_b[0]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[0]" LOC = Y15;
NET "lvds_right_data_p_b[10]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[10]" LOC = AA8;
NET "lvds_right_data_p_b[11]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[11]" LOC = Y7;
NET "lvds_right_data_p_b[12]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[12]" LOC = V7;
NET "lvds_right_data_p_b[13]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[13]" LOC = W6;
NET "lvds_right_data_p_b[14]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[14]" LOC = AA6;
NET "lvds_right_data_p_b[15]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[15]" LOC = Y5;
NET "lvds_right_data_p_b[1]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[1]" LOC = AA14;
NET "lvds_right_data_p_b[2]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[2]" LOC = W14;
NET "lvds_right_data_p_b[3]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[3]" LOC = V13;
NET "lvds_right_data_p_b[4]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[4]" LOC = W12;
NET "lvds_right_data_p_b[5]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[5]" LOC = V11;
NET "lvds_right_data_p_b[6]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[6]" LOC = W10;
NET "lvds_right_data_p_b[7]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[7]" LOC = AA10;
NET "lvds_right_data_p_b[8]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[8]" LOC = Y9;
NET "lvds_right_data_p_b[9]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[9]" LOC = W9;
NET "MAROC_TRIGGER_I[0]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[0]" LOC = Y21;
NET "MAROC_TRIGGER_I[10]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[10]" LOC = T18;
NET "MAROC_TRIGGER_I[11]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[11]" LOC = T19;
NET "MAROC_TRIGGER_I[12]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[12]" LOC = T20;
NET "MAROC_TRIGGER_I[13]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[13]" LOC = T21;
NET "MAROC_TRIGGER_I[14]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[14]" LOC = T22;
NET "MAROC_TRIGGER_I[15]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[15]" LOC = R20;
NET "MAROC_TRIGGER_I[16]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[16]" LOC = R22;
NET "MAROC_TRIGGER_I[17]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[17]" LOC = P17;
NET "MAROC_TRIGGER_I[18]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[18]" LOC = P18;
NET "MAROC_TRIGGER_I[19]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[19]" LOC = P19;
NET "MAROC_TRIGGER_I[1]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[1]" LOC = Y22;
NET "MAROC_TRIGGER_I[20]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[20]" LOC = P20;
NET "MAROC_TRIGGER_I[21]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[21]" LOC = P21;
NET "MAROC_TRIGGER_I[22]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[22]" LOC = P22;
NET "MAROC_TRIGGER_I[23]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[23]" LOC = N19;
NET "MAROC_TRIGGER_I[24]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[24]" LOC = N20;
NET "MAROC_TRIGGER_I[25]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[25]" LOC = N22;
NET "MAROC_TRIGGER_I[26]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[26]" LOC = M17;
NET "MAROC_TRIGGER_I[27]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[27]" LOC = M18;
NET "MAROC_TRIGGER_I[28]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[28]" LOC = M19;
NET "MAROC_TRIGGER_I[29]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[29]" LOC = M20;
NET "MAROC_TRIGGER_I[2]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[2]" LOC = W20;
NET "MAROC_TRIGGER_I[30]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[30]" LOC = M21;
NET "MAROC_TRIGGER_I[31]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[31]" LOC = M22;
NET "MAROC_TRIGGER_I[32]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[32]" LOC = L17;
NET "MAROC_TRIGGER_I[33]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[33]" LOC = L19;
NET "MAROC_TRIGGER_I[34]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[34]" LOC = L20;
NET "MAROC_TRIGGER_I[35]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[35]" LOC = L22;
NET "MAROC_TRIGGER_I[36]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[36]" LOC = K17;
NET "MAROC_TRIGGER_I[37]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[37]" LOC = K18;
NET "MAROC_TRIGGER_I[38]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[38]" LOC = K19;
NET "MAROC_TRIGGER_I[39]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[39]" LOC = K20;
NET "MAROC_TRIGGER_I[3]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[3]" LOC = W22;
NET "MAROC_TRIGGER_I[40]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[40]" LOC = J17;
NET "MAROC_TRIGGER_I[41]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[41]" LOC = J19;
NET "MAROC_TRIGGER_I[42]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[42]" LOC = J20;
NET "MAROC_TRIGGER_I[43]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[43]" LOC = J22;
NET "MAROC_TRIGGER_I[44]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[44]" LOC = H17;
NET "MAROC_TRIGGER_I[45]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[45]" LOC = H18;
NET "MAROC_TRIGGER_I[46]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[46]" LOC = H19;
NET "MAROC_TRIGGER_I[47]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[47]" LOC = H20;
NET "MAROC_TRIGGER_I[48]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[48]" LOC = H21;
NET "MAROC_TRIGGER_I[49]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[49]" LOC = H22;
NET "MAROC_TRIGGER_I[4]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[4]" LOC = V21;
NET "MAROC_TRIGGER_I[50]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[50]" LOC = G19;
NET "MAROC_TRIGGER_I[51]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[51]" LOC = G20;
NET "MAROC_TRIGGER_I[52]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[52]" LOC = G22;
NET "MAROC_TRIGGER_I[53]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[53]" LOC = F18;
NET "MAROC_TRIGGER_I[54]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[54]" LOC = F20;
NET "MAROC_TRIGGER_I[55]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[55]" LOC = F21;
NET "MAROC_TRIGGER_I[56]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[56]" LOC = F22;
NET "MAROC_TRIGGER_I[57]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[57]" LOC = E20;
NET "MAROC_TRIGGER_I[58]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[58]" LOC = E22;
NET "MAROC_TRIGGER_I[59]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[59]" LOC = D21;
NET "MAROC_TRIGGER_I[5]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[5]" LOC = V22;
NET "MAROC_TRIGGER_I[60]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[60]" LOC = C20;
NET "MAROC_TRIGGER_I[61]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[61]" LOC = C22;
NET "MAROC_TRIGGER_I[62]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[62]" LOC = B21;
NET "MAROC_TRIGGER_I[63]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[63]" LOC = B22;
NET "MAROC_TRIGGER_I[6]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[6]" LOC = U19;
NET "MAROC_TRIGGER_I[7]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[7]" LOC = U20;
NET "MAROC_TRIGGER_I[8]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[8]" LOC = U22;
NET "MAROC_TRIGGER_I[9]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[9]" LOC = T17;
NET "one_wire_b" DRIVE = 12;
NET "one_wire_b" IOSTANDARD = LVCMOS33;
NET "one_wire_b" LOC = T5;
NET "one_wire_b" SLEW = SLOW;
NET "OR_I[1]" IOSTANDARD = SSTL2_I;
NET "OR_I[1]" LOC = N6;
NET "OR_I[2]" IOSTANDARD = SSTL2_I;
NET "OR_I[2]" LOC = P6;
NET "OUT_ADC_I" IOSTANDARD = SSTL2_I;
NET "OUT_ADC_I" LOC = W3;
NET "pll25dac1_sync_n_o" DRIVE = 12;
NET "pll25dac1_sync_n_o" IOSTANDARD = LVCMOS33;
NET "pll25dac1_sync_n_o" LOC = R1;
NET "pll25dac1_sync_n_o" SLEW = SLOW;
NET "pll25dac2_sync_n_o" DRIVE = 12;
NET "pll25dac2_sync_n_o" IOSTANDARD = LVCMOS33;
NET "pll25dac2_sync_n_o" LOC = R3;
NET "pll25dac2_sync_n_o" SLEW = SLOW;
NET "pll25dac_din_o" DRIVE = 12;
NET "pll25dac_din_o" IOSTANDARD = LVCMOS33;
NET "pll25dac_din_o" LOC = R4;
NET "pll25dac_din_o" SLEW = SLOW;
NET "pll25dac_sclk_o" DRIVE = 12;
NET "pll25dac_sclk_o" IOSTANDARD = LVCMOS33;
NET "pll25dac_sclk_o" LOC = P1;
NET "pll25dac_sclk_o" SLEW = SLOW;
#NET "Q_R_I_IBUF" IOSTANDARD = LVCMOS33;
NET "Q_R_I" IOSTANDARD = LVCMOS33;
NET "Q_R_I" LOC = U1;
#NET "Q_SC_I_IBUF" IOSTANDARD = LVCMOS33;
NET "Q_SC_I" IOSTANDARD = LVCMOS33;
NET "Q_SC_I" LOC = U3;
NET "RST_ADC_N_O" DRIVE = 12;
NET "RST_ADC_N_O" IOSTANDARD = LVCMOS33;
NET "RST_ADC_N_O" LOC = AA1;
NET "RST_ADC_N_O" SLEW = SLOW;
NET "RST_R_N_O" DRIVE = 12;
NET "RST_R_N_O" IOSTANDARD = LVCMOS33;
NET "RST_R_N_O" LOC = Y1;
#NET "RST_R_N_O_OBUF" IOSTANDARD = LVCMOS33;
NET "RST_R_N_O" SLEW = SLOW;
NET "RST_SC_N_O" DRIVE = 12;
NET "RST_SC_N_O" IOSTANDARD = LVCMOS33;
NET "RST_SC_N_O" LOC = U4;
#NET "RST_SC_N_O_OBUF" IOSTANDARD = LVCMOS33;
NET "RST_SC_N_O" SLEW = SLOW;
#-NET "sata_rxp_i[0]" LOC = D13;
NET "sata_rxn_i" LOC = C9;
#-NET "sata_rxn_i[0]" LOC = C13;
NET "sata_rxp_i" LOC = D9;
#-NET "sata_txp_o[0]" LOC = B14;
NET "sata_txn_o" LOC = A8;
#-NET "sata_txn_o[0]" LOC = A14;
NET "sata_txp_o" LOC = B8;
NET "sfp_mod_def*" PULLUP=true;
NET "sfp_rate_select_b*" PULLUP=true;
NET "sfp_los_i[0]" IOSTANDARD = LVCMOS33;
NET "sfp_los_i[0]" LOC = P3;
NET "sfp_los_i[1]" IOSTANDARD = LVCMOS33;
NET "sfp_los_i[1]" LOC = N4;
NET "sfp_mod_def0_b[0]" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def0_b[0]" LOC = K4;
NET "sfp_mod_def0_b[1]" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def0_b[1]" LOC = K2;
NET "sfp_mod_def1_b[0]" DRIVE = 12;
NET "sfp_mod_def1_b[0]" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def1_b[0]" LOC = N3;
NET "sfp_mod_def1_b[0]" SLEW = SLOW;
NET "sfp_mod_def1_b[1]" DRIVE = 12;
NET "sfp_mod_def1_b[1]" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def1_b[1]" LOC = M2;
NET "sfp_mod_def1_b[1]" SLEW = SLOW;
NET "sfp_mod_def2_b[0]" DRIVE = 12;
NET "sfp_mod_def2_b[0]" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def2_b[0]" LOC = N1;
NET "sfp_mod_def2_b[0]" SLEW = SLOW;
NET "sfp_mod_def2_b[1]" DRIVE = 12;
NET "sfp_mod_def2_b[1]" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def2_b[1]" LOC = M1;
NET "sfp_mod_def2_b[1]" SLEW = SLOW;
NET "sfp_rate_select_b[0]" DRIVE = 12;
NET "sfp_rate_select_b[0]" IOSTANDARD = LVCMOS33;
NET "sfp_rate_select_b[0]" LOC = P5;
NET "sfp_rate_select_b[0]" SLEW = SLOW;
NET "sfp_rate_select_b[1]" DRIVE = 12;
NET "sfp_rate_select_b[1]" IOSTANDARD = LVCMOS33;
NET "sfp_rate_select_b[1]" LOC = P4;
NET "sfp_rate_select_b[1]" SLEW = SLOW;
#-NET "sfp_rxn_i[0]" LOC = C15;
NET "sfp_rxn_i" LOC = C7;
#-NET "sfp_rxp_i[0]" LOC = D15;
NET "sfp_rxp_i" LOC = D7;
NET "sfp_tx_disable_o[0]" DRIVE = 12;
NET "sfp_tx_disable_o[0]" IOSTANDARD = LVCMOS33;
NET "sfp_tx_disable_o[0]" LOC = K5;
NET "sfp_tx_disable_o[0]" SLEW = SLOW;
NET "sfp_tx_disable_o[1]" DRIVE = 12;
NET "sfp_tx_disable_o[1]" IOSTANDARD = LVCMOS33;
NET "sfp_tx_disable_o[1]" LOC = K6;
NET "sfp_tx_disable_o[1]" SLEW = SLOW;
NET "sfp_tx_fault_i[0]" IOSTANDARD = LVCMOS33;
NET "sfp_tx_fault_i[0]" LOC = K3;
NET "sfp_tx_fault_i[1]" IOSTANDARD = LVCMOS33;
NET "sfp_tx_fault_i[1]" LOC = L6;
#-NET "sfp_txn_o[0]" LOC = A16;
NET "sfp_txn_o" LOC = A6;
#-NET "sfp_txp_o[0]" LOC = B16;
NET "sfp_txp_o" LOC = B6;
NET "si57x_clk_n_i" IOSTANDARD = LVDS_25;
NET "si57x_clk_n_i" LOC = L4;
NET "si57x_clk_p_i" IOSTANDARD = LVDS_25;
NET "si57x_clk_p_i" LOC = M3;
NET "si57x_oe_o" DRIVE = 12;
NET "si57x_oe_o" IOSTANDARD = LVCMOS33;
NET "si57x_oe_o" LOC = P2;
NET "si57x_oe_o" SLEW = SLOW;
NET "START_ADC_N_O" DRIVE = 12;
NET "START_ADC_N_O" IOSTANDARD = LVCMOS33;
NET "START_ADC_N_O" LOC = Y3;
NET "START_ADC_N_O" SLEW = SLOW;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 125 MHz HIGH 50 %;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 20 MHz HIGH 50 %;
#- TIMESPEC TS_fpga_pll_ref_clk_101_n_i = PERIOD "fpga_pll_ref_clk_101_n_i" 125 MHz HIGH 50 %;
TIMESPEC TS_fpga_pll_ref_clk_123_p_i = PERIOD "fpga_pll_ref_clk_123_p_i" 125 MHz HIGH 50 %;
TIMESPEC TS_lvds_left_clk_p_b = PERIOD "lvds_left_clk_p_b" 125 MHz HIGH 50 %;
TIMESPEC TS_lvds_right_clk_p_b = PERIOD "lvds_right_clk_p_b" 125 MHz HIGH 50 %;
# Don't care about the timing of these signals w.r.t. clock, since they are static during data acqusition
NET "*s_triggerSourceSelect*" TIG;
NET "*s_hold1Delay*" TIG;
NET "*s_hold2Delay*" TIG;
# Don't care about timing of reset signal
NET "IPBusInterface_inst/generate_physicalmac.clocks/rst*" TIG;
NET "maroc/slave2_trigger/s_counter_reset_ipb" TIG;
# Bodge, bodge
NET "maroc/slave5_triggerCounter/*reset*" TIG;
NET "maroc/slave5_triggerCounter/inst_sync_reg/*ring*" TIG;
NET "maroc/slave5_triggerCounter/inst_sync_reg/*data*" TIG;
\ No newline at end of file
CONFIG PROHIBIT = AA20;
CONFIG PROHIBIT = AA21;
CONFIG PROHIBIT = AA3;
CONFIG PROHIBIT = AB20;
CONFIG PROHIBIT = C3;
CONFIG PROHIBIT = L1;
CONFIG PROHIBIT = V19;
CONFIG PROHIBIT = V20;
CONFIG PROHIBIT = Y19;
CONFIG PROHIBIT = Y20;
CONFIG PROHIBIT = Y4;
CONFIG VCCAUX=2.5;
#- INST "cmp_gtp_dedicated_clk_buf0" LOC = BUFDS_X2Y5;
INST "IPBusInterface_inst/generate_physicalmac.eth/ibuf0" LOC = BUFDS_X1Y5;
INST "IPBusInterface_inst/generate_physicalmac.eth/phy/transceiver_inst/GTP_1000X/tile0_s6_gtpwizard_i/gtpa1_dual_i" LOC = GTPA1_DUAL_X0Y1;
#- INST "U_GTP/U_GTP_TILE_INST/gtpa1_dual_i" LOC = GTPA1_DUAL_X1Y1;
NET "ADC_DAV_I" IOSTANDARD = SSTL2_I;
NET "ADC_DAV_I" LOC = W1;
NET "button1_i" IOSTANDARD = LVCMOS33;
NET "button1_i" LOC = H5;
NET "button2_i" IOSTANDARD = LVCMOS33;
NET "button2_i" LOC = H6;
NET "CK_40M_N_O" IOSTANDARD = LVDS_25;
NET "CK_40M_N_O" LOC = AB4;
NET "CK_40M_P_O" IOSTANDARD = LVDS_25;
NET "CK_40M_P_O" LOC = AA4;
NET "CK_R_O" DRIVE = 12;
NET "CK_R_O" IOSTANDARD = LVCMOS33;
NET "CK_R_O" LOC = W4;
NET "CK_R_O" SLEW = SLOW;
NET "CK_SC_O" DRIVE = 12;
NET "CK_SC_O" IOSTANDARD = LVCMOS33;
NET "CK_SC_O" LOC = V1;
NET "CK_SC_O" SLEW = SLOW;
NET "clk_125m_pllref_n_i" IOSTANDARD = LVDS_25;
NET "clk_125m_pllref_n_i" LOC = K22 | DIFF_TERM=TRUE;
NET "clk_125m_pllref_n_i" TNM_NET = "clk_125m_pllref_n_i";
NET "clk_125m_pllref_p_i" IOSTANDARD = LVDS_25;
NET "clk_125m_pllref_p_i" LOC = K21 | DIFF_TERM=TRUE;
NET "clk_125m_pllref_p_i" TNM_NET = "clk_125m_pllref_p_i";
NET "clk_20m_vcxo_i" IOSTANDARD = LVCMOS33;
NET "clk_20m_vcxo_i" LOC = L3;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
NET "CTEST_O[0]" DRIVE = 12;
NET "CTEST_O[0]" IOSTANDARD = LVCMOS33;
NET "CTEST_O[0]" LOC = E3;
NET "CTEST_O[0]" SLEW = SLOW;
NET "CTEST_O[1]" DRIVE = 12;
NET "CTEST_O[1]" IOSTANDARD = LVCMOS33;
NET "CTEST_O[1]" LOC = E1;
NET "CTEST_O[1]" SLEW = SLOW;
NET "CTEST_O[2]" DRIVE = 12;
NET "CTEST_O[2]" IOSTANDARD = LVCMOS33;
NET "CTEST_O[2]" LOC = D2;
NET "CTEST_O[2]" SLEW = SLOW;
NET "CTEST_O[3]" DRIVE = 12;
NET "CTEST_O[3]" IOSTANDARD = LVCMOS33;
NET "CTEST_O[3]" LOC = D1;
NET "CTEST_O[3]" SLEW = SLOW;
NET "CTEST_O[4]" DRIVE = 12;
NET "CTEST_O[4]" IOSTANDARD = LVCMOS33;
NET "CTEST_O[4]" LOC = C1;
NET "CTEST_O[4]" SLEW = SLOW;
NET "CTEST_O[5]" DRIVE = 12;
NET "CTEST_O[5]" IOSTANDARD = LVCMOS33;
# NET "CTEST_O[5]" LOC = B1;
NET "CTEST_O[5]" LOC = E4;
NET "CTEST_O[5]" SLEW = SLOW;
NET "dip_switch_i[0]" IOSTANDARD = LVCMOS33;
NET "dip_switch_i[0]" LOC = J6;
NET "dip_switch_i[1]" IOSTANDARD = LVCMOS33;
NET "dip_switch_i[1]" LOC = J4;
NET "dip_switch_i[2]" IOSTANDARD = LVCMOS33;
NET "dip_switch_i[2]" LOC = J3;
NET "dip_switch_i[3]" IOSTANDARD = LVCMOS33;
NET "dip_switch_i[3]" LOC = K1;
NET "D_R_O" DRIVE = 12;
NET "D_R_O" IOSTANDARD = LVCMOS33;
NET "D_R_O" LOC = V2;
NET "D_R_O" SLEW = SLOW;
NET "D_SC_O" DRIVE = 12;
NET "D_SC_O" IOSTANDARD = LVCMOS33;
NET "D_SC_O" LOC = V3;
NET "D_SC_O" SLEW = SLOW;
NET "enable_gclk_drive_o" DRIVE = 12;
NET "enable_gclk_drive_o" IOSTANDARD = LVCMOS33;
NET "enable_gclk_drive_o" LOC = T1;
NET "enable_gclk_drive_o" SLEW = SLOW;
NET "enable_globaltrig_drive_o" DRIVE = 12;
NET "enable_globaltrig_drive_o" IOSTANDARD = LVCMOS33;
NET "enable_globaltrig_drive_o" LOC = T2;
NET "enable_globaltrig_drive_o" SLEW = SLOW;
NET "EN_OTAQ_O" DRIVE = 12;
NET "EN_OTAQ_O" IOSTANDARD = LVCMOS33;
NET "EN_OTAQ_O" LOC = V5;
NET "EN_OTAQ_O" SLEW = SLOW;
#- NET "fpga_pll_ref_clk_101_n_i" LOC = F12 | DIFF_TERM=TRUE;
#- NET "fpga_pll_ref_clk_101_n_i" TNM_NET = "fpga_pll_ref_clk_101_n_i";
#- NET "fpga_pll_ref_clk_101_p_i" LOC = E12 | DIFF_TERM=TRUE;
NET "fpga_pll_ref_clk_123_n_i" LOC = D11 | DIFF_TERM=TRUE;
NET "fpga_pll_ref_clk_123_p_i" LOC = C11 | DIFF_TERM=TRUE;
NET "fpga_pll_ref_clk_123_p_i" TNM_NET = "fpga_pll_ref_clk_123_p_i";
NET "fpga_scl_b" DRIVE = 12;
NET "fpga_scl_b" IOSTANDARD = LVCMOS33;
NET "fpga_scl_b" LOC = T3;
NET "fpga_scl_b" SLEW = SLOW;
NET "fpga_sda_b" DRIVE = 12;
NET "fpga_sda_b" IOSTANDARD = LVCMOS33;
NET "fpga_sda_b" LOC = T4;
NET "fpga_sda_b" SLEW = SLOW;
NET "GPIO[0]" DRIVE = 12;
NET "GPIO[0]" IOSTANDARD = LVCMOS33;
NET "GPIO[0]" LOC = G4;
NET "GPIO[0]" SLEW = SLOW;
NET "GPIO[1]" DRIVE = 12;
NET "GPIO[1]" IOSTANDARD = LVCMOS33;
NET "GPIO[1]" LOC = G3;
NET "GPIO[1]" SLEW = SLOW;
NET "GPIO[2]" DRIVE = 12;
NET "GPIO[2]" IOSTANDARD = LVCMOS33;
NET "GPIO[2]" LOC = G1;
NET "GPIO[2]" SLEW = SLOW;
NET "GPIO[3]" DRIVE = 12;
NET "GPIO[3]" IOSTANDARD = LVCMOS33;
NET "GPIO[3]" LOC = G6;
NET "GPIO[3]" SLEW = SLOW;
NET "GPIO[4]" DRIVE = 12;
NET "GPIO[4]" IOSTANDARD = LVCMOS33;
NET "GPIO[4]" LOC = F3;
NET "GPIO[4]" SLEW = SLOW;
NET "GPIO[5]" DRIVE = 12;
NET "GPIO[5]" IOSTANDARD = LVCMOS33;
NET "GPIO[5]" LOC = F2;
NET "GPIO[5]" SLEW = SLOW;
NET "GPIO[6]" DRIVE = 12;
NET "GPIO[6]" IOSTANDARD = LVCMOS33;
NET "GPIO[6]" LOC = F1;
NET "GPIO[6]" SLEW = SLOW;
NET "GPIO[7]" IOSTANDARD = LVCMOS33;
NET "GPIO[7]" LOC = F5;
NET "GPIO[7]" PULLDOWN=true;
NET "HOLD1_O" DRIVE = 12;
NET "HOLD1_O" IOSTANDARD = LVCMOS33;
NET "HOLD1_O" LOC = Y2;
NET "HOLD1_O" SLEW = SLOW;
NET "HOLD2_O" DRIVE = 12;
NET "HOLD2_O" IOSTANDARD = LVCMOS33;
NET "HOLD2_O" LOC = AA2;
NET "HOLD2_O" SLEW = SLOW;
NET "leds_o[0]" DRIVE = 12;
NET "leds_o[0]" IOSTANDARD = LVCMOS33;
NET "leds_o[0]" LOC = H4;
NET "leds_o[0]" SLEW = SLOW;
NET "leds_o[1]" DRIVE = 12;
NET "leds_o[1]" IOSTANDARD = LVCMOS33;
NET "leds_o[1]" LOC = H3;
NET "leds_o[1]" SLEW = SLOW;
NET "leds_o[2]" DRIVE = 12;
NET "leds_o[2]" IOSTANDARD = LVCMOS33;
NET "leds_o[2]" LOC = H2;
NET "leds_o[2]" SLEW = SLOW;
NET "leds_o[3]" DRIVE = 12;
NET "leds_o[3]" IOSTANDARD = LVCMOS33;
NET "leds_o[3]" LOC = H1;
NET "leds_o[3]" SLEW = SLOW;
NET "leds_o[4]" DRIVE = 12;
NET "leds_o[4]" IOSTANDARD = LVCMOS33;
NET "leds_o[4]" LOC = J1;
NET "leds_o[4]" SLEW = SLOW;
NET "lvds_gclk_from_fpga_n_o" IOSTANDARD = LVDS_25;
NET "lvds_gclk_from_fpga_n_o" LOC = AB17;
NET "lvds_gclk_from_fpga_p_o" IOSTANDARD = LVDS_25;
NET "lvds_gclk_from_fpga_p_o" LOC = Y17;
NET "lvds_gclk_to_fpga_n_i" IOSTANDARD = LVDS_25;
NET "lvds_gclk_to_fpga_n_i" LOC = AB12;
NET "lvds_gclk_to_fpga_p_i" IOSTANDARD = LVDS_25;
NET "lvds_gclk_to_fpga_p_i" LOC = AA12;
NET "lvds_globaltrig_from_fpga_n_o" IOSTANDARD = LVDS_25;
NET "lvds_globaltrig_from_fpga_n_o" LOC = AB18;
NET "lvds_globaltrig_from_fpga_p_o" IOSTANDARD = LVDS_25;
NET "lvds_globaltrig_from_fpga_p_o" LOC = AA18;
NET "lvds_globaltrig_to_fpga_n_i" IOSTANDARD = LVDS_25;
NET "lvds_globaltrig_to_fpga_n_i" LOC = AB13;
NET "lvds_globaltrig_to_fpga_p_i" IOSTANDARD = LVDS_25;
NET "lvds_globaltrig_to_fpga_p_i" LOC = Y13;
NET "lvds_left_clk_n_b" IOSTANDARD = LVDS_25;
NET "lvds_left_clk_n_b" LOC = F15;
NET "lvds_left_clk_p_b" IOSTANDARD = LVDS_25;
NET "lvds_left_clk_p_b" LOC = F14;
NET "lvds_left_clk_p_b" TNM_NET = "lvds_left_clk_p_b";
NET "lvds_left_data_n_b[0]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[0]" LOC = A20;
NET "lvds_left_data_n_b[10]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[10]" LOC = E6;
NET "lvds_left_data_n_b[11]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[11]" LOC = D5;
NET "lvds_left_data_n_b[12]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[12]" LOC = A5;
NET "lvds_left_data_n_b[13]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[13]" LOC = A4;
NET "lvds_left_data_n_b[14]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[14]" LOC = A3;
NET "lvds_left_data_n_b[15]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[15]" LOC = A2;
NET "lvds_left_data_n_b[1]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[1]" LOC = A19;
NET "lvds_left_data_n_b[2]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[2]" LOC = D19;
NET "lvds_left_data_n_b[3]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[3]" LOC = A18;
NET "lvds_left_data_n_b[4]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[4]" LOC = A17;
NET "lvds_left_data_n_b[5]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[5]" LOC = C18;
NET "lvds_left_data_n_b[6]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[6]" LOC = F17;
NET "lvds_left_data_n_b[7]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[7]" LOC = F16;
NET "lvds_left_data_n_b[8]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[8]" LOC = F9;
NET "lvds_left_data_n_b[9]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_n_b[9]" LOC = F8;
NET "lvds_left_data_p_b[0]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[0]" LOC = B20;
NET "lvds_left_data_p_b[10]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[10]" LOC = E5;
NET "lvds_left_data_p_b[11]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[11]" LOC = D4;
NET "lvds_left_data_p_b[12]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[12]" LOC = C5;
NET "lvds_left_data_p_b[13]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[13]" LOC = C4;
NET "lvds_left_data_p_b[14]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[14]" LOC = B3;
NET "lvds_left_data_p_b[15]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[15]" LOC = B2;
NET "lvds_left_data_p_b[1]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[1]" LOC = C19;
NET "lvds_left_data_p_b[2]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[2]" LOC = D18;
NET "lvds_left_data_p_b[3]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[3]" LOC = B18;
NET "lvds_left_data_p_b[4]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[4]" LOC = C17;
NET "lvds_left_data_p_b[5]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[5]" LOC = D17;
NET "lvds_left_data_p_b[6]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[6]" LOC = G16;
NET "lvds_left_data_p_b[7]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[7]" LOC = E16;
NET "lvds_left_data_p_b[8]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[8]" LOC = G8;
NET "lvds_left_data_p_b[9]" IOSTANDARD = LVDS_25;
NET "lvds_left_data_p_b[9]" LOC = F7;
NET "lvds_otrig_from_fpga_n_o" IOSTANDARD = LVDS_25;
NET "lvds_otrig_from_fpga_n_o" LOC = AB16;
NET "lvds_otrig_from_fpga_p_o" IOSTANDARD = LVDS_25;
NET "lvds_otrig_from_fpga_p_o" LOC = AA16;
NET "lvds_otrig_to_fpga_n_i" IOSTANDARD = LVDS_25;
NET "lvds_otrig_to_fpga_n_i" LOC = Y18;
NET "lvds_otrig_to_fpga_p_i" IOSTANDARD = LVDS_25;
NET "lvds_otrig_to_fpga_p_i" LOC = W17;
NET "lvds_right_clk_n_b" IOSTANDARD = LVDS_25;
NET "lvds_right_clk_n_b" LOC = AB11;
NET "lvds_right_clk_p_b" IOSTANDARD = LVDS_25;
NET "lvds_right_clk_p_b" LOC = Y11;
NET "lvds_right_clk_p_b" TNM_NET = "lvds_right_clk_p_b";
NET "lvds_right_data_n_b[0]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[0]" LOC = AB15;
NET "lvds_right_data_n_b[10]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[10]" LOC = AB8;
NET "lvds_right_data_n_b[11]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[11]" LOC = AB7;
NET "lvds_right_data_n_b[12]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[12]" LOC = W8;
NET "lvds_right_data_n_b[13]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[13]" LOC = Y6;
NET "lvds_right_data_n_b[14]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[14]" LOC = AB6;
NET "lvds_right_data_n_b[15]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[15]" LOC = AB5;
NET "lvds_right_data_n_b[1]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[1]" LOC = AB14;
NET "lvds_right_data_n_b[2]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[2]" LOC = Y14;
NET "lvds_right_data_n_b[3]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[3]" LOC = W13;
NET "lvds_right_data_n_b[4]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[4]" LOC = Y12;
NET "lvds_right_data_n_b[5]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[5]" LOC = W11;
NET "lvds_right_data_n_b[6]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[6]" LOC = Y10;
NET "lvds_right_data_n_b[7]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[7]" LOC = AB10;
NET "lvds_right_data_n_b[8]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[8]" LOC = AB9;
NET "lvds_right_data_n_b[9]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_n_b[9]" LOC = Y8;
NET "lvds_right_data_p_b[0]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[0]" LOC = Y15;
NET "lvds_right_data_p_b[10]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[10]" LOC = AA8;
NET "lvds_right_data_p_b[11]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[11]" LOC = Y7;
NET "lvds_right_data_p_b[12]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[12]" LOC = V7;
NET "lvds_right_data_p_b[13]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[13]" LOC = W6;
NET "lvds_right_data_p_b[14]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[14]" LOC = AA6;
NET "lvds_right_data_p_b[15]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[15]" LOC = Y5;
NET "lvds_right_data_p_b[1]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[1]" LOC = AA14;
NET "lvds_right_data_p_b[2]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[2]" LOC = W14;
NET "lvds_right_data_p_b[3]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[3]" LOC = V13;
NET "lvds_right_data_p_b[4]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[4]" LOC = W12;
NET "lvds_right_data_p_b[5]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[5]" LOC = V11;
NET "lvds_right_data_p_b[6]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[6]" LOC = W10;
NET "lvds_right_data_p_b[7]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[7]" LOC = AA10;
NET "lvds_right_data_p_b[8]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[8]" LOC = Y9;
NET "lvds_right_data_p_b[9]" IOSTANDARD = LVDS_25;
NET "lvds_right_data_p_b[9]" LOC = W9;
NET "MAROC_TRIGGER_I[0]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[0]" LOC = Y21;
NET "MAROC_TRIGGER_I[10]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[10]" LOC = T18;
NET "MAROC_TRIGGER_I[11]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[11]" LOC = T19;
NET "MAROC_TRIGGER_I[12]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[12]" LOC = T20;
NET "MAROC_TRIGGER_I[13]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[13]" LOC = T21;
NET "MAROC_TRIGGER_I[14]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[14]" LOC = T22;
NET "MAROC_TRIGGER_I[15]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[15]" LOC = R20;
NET "MAROC_TRIGGER_I[16]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[16]" LOC = R22;
NET "MAROC_TRIGGER_I[17]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[17]" LOC = P17;
NET "MAROC_TRIGGER_I[18]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[18]" LOC = P18;
NET "MAROC_TRIGGER_I[19]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[19]" LOC = P19;
NET "MAROC_TRIGGER_I[1]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[1]" LOC = Y22;
NET "MAROC_TRIGGER_I[20]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[20]" LOC = P20;
NET "MAROC_TRIGGER_I[21]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[21]" LOC = P21;
NET "MAROC_TRIGGER_I[22]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[22]" LOC = P22;
NET "MAROC_TRIGGER_I[23]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[23]" LOC = N19;
NET "MAROC_TRIGGER_I[24]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[24]" LOC = N20;
NET "MAROC_TRIGGER_I[25]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[25]" LOC = N22;
NET "MAROC_TRIGGER_I[26]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[26]" LOC = M17;
NET "MAROC_TRIGGER_I[27]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[27]" LOC = M18;
NET "MAROC_TRIGGER_I[28]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[28]" LOC = M19;
NET "MAROC_TRIGGER_I[29]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[29]" LOC = M20;
NET "MAROC_TRIGGER_I[2]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[2]" LOC = W20;
NET "MAROC_TRIGGER_I[30]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[30]" LOC = M21;
NET "MAROC_TRIGGER_I[31]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[31]" LOC = M22;
NET "MAROC_TRIGGER_I[32]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[32]" LOC = L17;
NET "MAROC_TRIGGER_I[33]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[33]" LOC = L19;
NET "MAROC_TRIGGER_I[34]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[34]" LOC = L20;
NET "MAROC_TRIGGER_I[35]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[35]" LOC = L22;
NET "MAROC_TRIGGER_I[36]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[36]" LOC = K17;
NET "MAROC_TRIGGER_I[37]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[37]" LOC = K18;
NET "MAROC_TRIGGER_I[38]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[38]" LOC = K19;
NET "MAROC_TRIGGER_I[39]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[39]" LOC = K20;
NET "MAROC_TRIGGER_I[3]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[3]" LOC = W22;
NET "MAROC_TRIGGER_I[40]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[40]" LOC = J17;
NET "MAROC_TRIGGER_I[41]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[41]" LOC = J19;
NET "MAROC_TRIGGER_I[42]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[42]" LOC = J20;
NET "MAROC_TRIGGER_I[43]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[43]" LOC = J22;
NET "MAROC_TRIGGER_I[44]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[44]" LOC = H17;
NET "MAROC_TRIGGER_I[45]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[45]" LOC = H18;
NET "MAROC_TRIGGER_I[46]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[46]" LOC = H19;
NET "MAROC_TRIGGER_I[47]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[47]" LOC = H20;
NET "MAROC_TRIGGER_I[48]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[48]" LOC = H21;
NET "MAROC_TRIGGER_I[49]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[49]" LOC = H22;
NET "MAROC_TRIGGER_I[4]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[4]" LOC = V21;
NET "MAROC_TRIGGER_I[50]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[50]" LOC = G19;
NET "MAROC_TRIGGER_I[51]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[51]" LOC = G20;
NET "MAROC_TRIGGER_I[52]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[52]" LOC = G22;
NET "MAROC_TRIGGER_I[53]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[53]" LOC = F18;
NET "MAROC_TRIGGER_I[54]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[54]" LOC = F20;
NET "MAROC_TRIGGER_I[55]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[55]" LOC = F21;
NET "MAROC_TRIGGER_I[56]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[56]" LOC = F22;
NET "MAROC_TRIGGER_I[57]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[57]" LOC = E20;
NET "MAROC_TRIGGER_I[58]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[58]" LOC = E22;
NET "MAROC_TRIGGER_I[59]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[59]" LOC = D21;
NET "MAROC_TRIGGER_I[5]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[5]" LOC = V22;
NET "MAROC_TRIGGER_I[60]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[60]" LOC = C20;
NET "MAROC_TRIGGER_I[61]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[61]" LOC = C22;
NET "MAROC_TRIGGER_I[62]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[62]" LOC = B21;
NET "MAROC_TRIGGER_I[63]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[63]" LOC = B22;
NET "MAROC_TRIGGER_I[6]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[6]" LOC = U19;
NET "MAROC_TRIGGER_I[7]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[7]" LOC = U20;
NET "MAROC_TRIGGER_I[8]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[8]" LOC = U22;
NET "MAROC_TRIGGER_I[9]" IOSTANDARD = SSTL2_I;
NET "MAROC_TRIGGER_I[9]" LOC = T17;
NET "one_wire_b" DRIVE = 12;
NET "one_wire_b" IOSTANDARD = LVCMOS33;
NET "one_wire_b" LOC = T5;
NET "one_wire_b" SLEW = SLOW;
NET "OR_I[1]" IOSTANDARD = SSTL2_I;
NET "OR_I[1]" LOC = N6;
NET "OR_I[2]" IOSTANDARD = SSTL2_I;
NET "OR_I[2]" LOC = P6;
NET "OUT_ADC_I" IOSTANDARD = SSTL2_I;
NET "OUT_ADC_I" LOC = W3;
NET "pll25dac1_sync_n_o" DRIVE = 12;
NET "pll25dac1_sync_n_o" IOSTANDARD = LVCMOS33;
NET "pll25dac1_sync_n_o" LOC = R1;
NET "pll25dac1_sync_n_o" SLEW = SLOW;
NET "pll25dac2_sync_n_o" DRIVE = 12;
NET "pll25dac2_sync_n_o" IOSTANDARD = LVCMOS33;
NET "pll25dac2_sync_n_o" LOC = R3;
NET "pll25dac2_sync_n_o" SLEW = SLOW;
NET "pll25dac_din_o" DRIVE = 12;
NET "pll25dac_din_o" IOSTANDARD = LVCMOS33;
NET "pll25dac_din_o" LOC = R4;
NET "pll25dac_din_o" SLEW = SLOW;
NET "pll25dac_sclk_o" DRIVE = 12;
NET "pll25dac_sclk_o" IOSTANDARD = LVCMOS33;
NET "pll25dac_sclk_o" LOC = P1;
NET "pll25dac_sclk_o" SLEW = SLOW;
#NET "Q_R_I_IBUF" IOSTANDARD = LVCMOS33;
NET "Q_R_I" IOSTANDARD = LVCMOS33;
NET "Q_R_I" LOC = U1;
#NET "Q_SC_I_IBUF" IOSTANDARD = LVCMOS33;
NET "Q_SC_I" IOSTANDARD = LVCMOS33;
NET "Q_SC_I" LOC = U3;
NET "RST_ADC_N_O" DRIVE = 12;
NET "RST_ADC_N_O" IOSTANDARD = LVCMOS33;
NET "RST_ADC_N_O" LOC = AA1;
NET "RST_ADC_N_O" SLEW = SLOW;
NET "RST_R_N_O" DRIVE = 12;
NET "RST_R_N_O" IOSTANDARD = LVCMOS33;
NET "RST_R_N_O" LOC = Y1;
#NET "RST_R_N_O_OBUF" IOSTANDARD = LVCMOS33;
NET "RST_R_N_O" SLEW = SLOW;
NET "RST_SC_N_O" DRIVE = 12;
NET "RST_SC_N_O" IOSTANDARD = LVCMOS33;
NET "RST_SC_N_O" LOC = U4;
#NET "RST_SC_N_O_OBUF" IOSTANDARD = LVCMOS33;
NET "RST_SC_N_O" SLEW = SLOW;
#-NET "sata_rxp_i[0]" LOC = D13;
NET "sata_rxn_i" LOC = C9;
#-NET "sata_rxn_i[0]" LOC = C13;
NET "sata_rxp_i" LOC = D9;
#-NET "sata_txp_o[0]" LOC = B14;
NET "sata_txn_o" LOC = A8;
#-NET "sata_txn_o[0]" LOC = A14;
NET "sata_txp_o" LOC = B8;
NET "sfp_mod_def*" PULLUP=true;
NET "sfp_rate_select_b*" PULLUP=true;
NET "sfp_los_i[0]" IOSTANDARD = LVCMOS33;
NET "sfp_los_i[0]" LOC = P3;
NET "sfp_los_i[1]" IOSTANDARD = LVCMOS33;
NET "sfp_los_i[1]" LOC = N4;
NET "sfp_mod_def0_b[0]" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def0_b[0]" LOC = K4;
NET "sfp_mod_def0_b[1]" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def0_b[1]" LOC = K2;
NET "sfp_mod_def1_b[0]" DRIVE = 12;
NET "sfp_mod_def1_b[0]" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def1_b[0]" LOC = N3;
NET "sfp_mod_def1_b[0]" SLEW = SLOW;
NET "sfp_mod_def1_b[1]" DRIVE = 12;
NET "sfp_mod_def1_b[1]" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def1_b[1]" LOC = M2;
NET "sfp_mod_def1_b[1]" SLEW = SLOW;
NET "sfp_mod_def2_b[0]" DRIVE = 12;
NET "sfp_mod_def2_b[0]" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def2_b[0]" LOC = N1;
NET "sfp_mod_def2_b[0]" SLEW = SLOW;
NET "sfp_mod_def2_b[1]" DRIVE = 12;
NET "sfp_mod_def2_b[1]" IOSTANDARD = LVCMOS33;
NET "sfp_mod_def2_b[1]" LOC = M1;
NET "sfp_mod_def2_b[1]" SLEW = SLOW;
NET "sfp_rate_select_b[0]" DRIVE = 12;
NET "sfp_rate_select_b[0]" IOSTANDARD = LVCMOS33;
NET "sfp_rate_select_b[0]" LOC = P5;
NET "sfp_rate_select_b[0]" SLEW = SLOW;
NET "sfp_rate_select_b[1]" DRIVE = 12;
NET "sfp_rate_select_b[1]" IOSTANDARD = LVCMOS33;
NET "sfp_rate_select_b[1]" LOC = P4;
NET "sfp_rate_select_b[1]" SLEW = SLOW;
#-NET "sfp_rxn_i[0]" LOC = C15;
NET "sfp_rxn_i" LOC = C7;
#-NET "sfp_rxp_i[0]" LOC = D15;
NET "sfp_rxp_i" LOC = D7;
NET "sfp_tx_disable_o[0]" DRIVE = 12;
NET "sfp_tx_disable_o[0]" IOSTANDARD = LVCMOS33;
NET "sfp_tx_disable_o[0]" LOC = K5;
NET "sfp_tx_disable_o[0]" SLEW = SLOW;
NET "sfp_tx_disable_o[1]" DRIVE = 12;
NET "sfp_tx_disable_o[1]" IOSTANDARD = LVCMOS33;
NET "sfp_tx_disable_o[1]" LOC = K6;
NET "sfp_tx_disable_o[1]" SLEW = SLOW;
NET "sfp_tx_fault_i[0]" IOSTANDARD = LVCMOS33;
NET "sfp_tx_fault_i[0]" LOC = K3;
NET "sfp_tx_fault_i[1]" IOSTANDARD = LVCMOS33;
NET "sfp_tx_fault_i[1]" LOC = L6;
#-NET "sfp_txn_o[0]" LOC = A16;
NET "sfp_txn_o" LOC = A6;
#-NET "sfp_txp_o[0]" LOC = B16;
NET "sfp_txp_o" LOC = B6;
NET "si57x_clk_n_i" IOSTANDARD = LVDS_25;
NET "si57x_clk_n_i" LOC = L4;
NET "si57x_clk_p_i" IOSTANDARD = LVDS_25;
NET "si57x_clk_p_i" LOC = M3;
NET "si57x_oe_o" DRIVE = 12;
NET "si57x_oe_o" IOSTANDARD = LVCMOS33;
NET "si57x_oe_o" LOC = P2;
NET "si57x_oe_o" SLEW = SLOW;
NET "START_ADC_N_O" DRIVE = 12;
NET "START_ADC_N_O" IOSTANDARD = LVCMOS33;
NET "START_ADC_N_O" LOC = Y3;
NET "START_ADC_N_O" SLEW = SLOW;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 125 MHz HIGH 50 %;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 20 MHz HIGH 50 %;
#- TIMESPEC TS_fpga_pll_ref_clk_101_n_i = PERIOD "fpga_pll_ref_clk_101_n_i" 125 MHz HIGH 50 %;
TIMESPEC TS_fpga_pll_ref_clk_123_p_i = PERIOD "fpga_pll_ref_clk_123_p_i" 125 MHz HIGH 50 %;
TIMESPEC TS_lvds_left_clk_p_b = PERIOD "lvds_left_clk_p_b" 125 MHz HIGH 50 %;
TIMESPEC TS_lvds_right_clk_p_b = PERIOD "lvds_right_clk_p_b" 125 MHz HIGH 50 %;
# Don't care about the timing of these signals w.r.t. clock, since they are static during data acqusition
NET "*s_triggerSourceSelect*" TIG;
NET "*s_hold1Delay*" TIG;
NET "*s_hold2Delay*" TIG;
# Don't care about timing of reset signal
NET "IPBusInterface_inst/generate_physicalmac.clocks/rst*" TIG;
NET "maroc/slave2_trigger/s_counter_reset_ipb" TIG;
# Bodge, bodge
NET "maroc/slave5_triggerCounter/*reset*" TIG;
NET "maroc/slave5_triggerCounter/inst_sync_reg/*ring*" TIG;
NET "maroc/slave5_triggerCounter/inst_sync_reg/*data*" TIG;
\ No newline at end of file
--=============================================================================
--! @file pc049a_top.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture work. pc049a_top.rtl
--
--! @brief Top level for single-MAROC eval board simple-design. No White Rabbit\n
--! \n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 6/10/2016
--
--! @version v0.1
--
--! @details
--! Includes Maroc IPBus slaves and IPBus core.
--! LEDs:
--! LED(2) - IPBus clocks locked. ( should be on )
--! LED(3) - One Hz heart-beat ( should strobe at 1Hz)
--! LED(4) - LOS for IPBus SFP ( should be off )
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by:</b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo <next thing to do> \n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
-- Packages for White Rabbit
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.wr_xilinx_pkg.all;
use work.etherbone_pkg.all;
-- Packages for IPBus
LIBRARY work;
USE work.ipbus.all;
USE work.emac_hostbus_decl.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.wishbone_pkg.all;
entity pc049a_top is
generic
(
BUILD_SIMULATED_ETHERNET : integer := 0 --! set to 1 to build with simulated Ethernet interface using Modelsim FLI
);
port
(
-- Global ports
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_pllref_p_i , clk_125m_pllref_n_i : in std_logic; -- 125 MHz PLL reference
fpga_pll_ref_clk_101_p_i , fpga_pll_ref_clk_101_n_i : in std_logic; -- Dedicated clock for Xilinx GTP transceiver
fpga_pll_ref_clk_123_p_i , fpga_pll_ref_clk_123_n_i : in std_logic; -- Dedicated clock for Xilinx GTP transceiver
si57x_clk_p_i , si57x_clk_n_i : in std_logic ; -- clock from si570 programmable oscillator. Default = 100MHz
si57x_oe_o : out std_logic := '1'; -- Chip enable for SI570
-- General Purpose Interface
GPIO : inout std_logic_vector(7 downto 0);
-- Push buttons
button1_i : in std_logic := 'H';
button2_i : in std_logic := 'H';
-- LEDs and DIP switch
leds_o : out std_logic_vector(4 downto 0);
dip_switch_i : in std_logic_vector(3 downto 0);
-- SPI interface for DACs that tune VCXO frequencies
pll25dac_sclk_o : out std_logic := '0';
pll25dac_din_o : out std_logic := '0';
pll25dac1_sync_n_o : out std_logic := '1';
pll25dac2_sync_n_o : out std_logic := '1';
-- I2C bus
fpga_scl_b : inout std_logic;
fpga_sda_b : inout std_logic;
one_wire_b : inout std_logic; -- 1-Wire interface to DS18B20
-------------------------------------------------------------------------
-- SFP pins.
-------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_b : in std_logic_vector(1 downto 0); -- sfp detect
sfp_mod_def1_b : inout std_logic_vector(1 downto 0); -- scl
sfp_mod_def2_b : inout std_logic_vector(1 downto 0); -- sda
sfp_rate_select_b : inout std_logic_vector(1 downto 0);
sfp_tx_fault_i : in std_logic_vector(1 downto 0);
sfp_tx_disable_o : out std_logic_vector(1 downto 0);
sfp_los_i : in std_logic_vector(1 downto 0);
-------------------------------------------------------------------------
-- eSATA pins. White Rabbit=0 , IPBus=1
-------------------------------------------------------------------------
sata_txp_o : out std_logic;
sata_txn_o : out std_logic;
sata_rxp_i : in std_logic;
sata_rxn_i : in std_logic;
-----------------------------------------
--UART
-----------------------------------------
-- uart_rxd_i : in std_logic;
-- uart_txd_o : out std_logic;
-----------------------------------------
-- MAROC connections
-----------------------------------------
CK_40M_P_O,CK_40M_N_O : out STD_LOGIC;
HOLD2_O: out STD_LOGIC;
HOLD1_O: out STD_LOGIC;
OR_I: in STD_LOGIC_VECTOR(2 downto 1);
MAROC_TRIGGER_I: in std_logic_vector(63 downto 0);
EN_OTAQ_O: out STD_LOGIC;
CTEST_O: out STD_LOGIC_VECTOR(5 downto 0); -- 4-bit R/2R DAC
ADC_DAV_I: in STD_LOGIC;
OUT_ADC_I: in STD_LOGIC;
START_ADC_N_O: out STD_LOGIC;
RST_ADC_N_O: out STD_LOGIC;
RST_SC_N_O: out STD_LOGIC;
Q_SC_I: in STD_LOGIC;
D_SC_O: out STD_LOGIC;
RST_R_N_O: out STD_LOGIC;
Q_R_I: in STD_LOGIC;
D_R_O: out STD_LOGIC;
CK_R_O: out STD_LOGIC;
CK_SC_O: out STD_LOGIC;
-----------------------------------------
-- Expansion Connectors
-----------------------------------------
-- fixed direction for now....
-- Data on left connector
lvds_left_data_p_b, lvds_left_data_n_b: out std_logic_vector(15 downto 0);
lvds_left_clk_p_b,lvds_left_clk_n_b: in std_logic;
-- Data on right connector
lvds_right_data_p_b,lvds_right_data_n_b: out std_logic_vector(15 downto 0);
lvds_right_clk_p_b,lvds_right_clk_n_b: in std_logic;
-- Global trigger lines
lvds_globaltrig_from_fpga_p_o: out std_logic;
lvds_globaltrig_from_fpga_n_o: out std_logic;
enable_globaltrig_drive_o: out std_logic;
lvds_globaltrig_to_fpga_p_i: in std_logic;
lvds_globaltrig_to_fpga_n_i: in std_logic;
-- "OR trigger" lines
lvds_otrig_from_fpga_p_o: out std_logic;
lvds_otrig_from_fpga_n_o: out std_logic;
lvds_otrig_to_fpga_p_i: in std_logic;
lvds_otrig_to_fpga_n_i: in std_logic;
-- Global clock lines
lvds_gclk_from_fpga_p_o: out std_logic;
lvds_gclk_from_fpga_n_o: out std_logic;
enable_gclk_drive_o: out std_logic;
lvds_gclk_to_fpga_p_i: in std_logic;
lvds_gclk_to_fpga_n_i: in std_logic
);
end pc049a_top;
architecture rtl of pc049a_top is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component spec_reset_gen
port (
clk_sys_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic);
end component;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_BAR0_APERTURE : integer := 20;
constant c_CSR_WB_SLAVES_NB : integer := 1;
constant c_DMA_WB_SLAVES_NB : integer := 1;
constant c_DMA_WB_ADDR_WIDTH : integer := 26;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal s_globaltrig_to_fpga, s_globaltrig_from_fpga : std_logic;
signal s_otrig_to_fpga , s_otrig_from_fpga : std_logic;
signal s_gclk_to_fpga , s_gclk_from_fpga : std_logic;
-- Dedicated clock for GTP transceiver
signal gtp_dedicated_clk : std_logic_vector(1 downto 0);
-- P2L colck PLL status
signal p2l_pll_locked : std_logic;
-- Reset
signal rst_a : std_logic;
-- DMA wishbone bus
--signal dma_adr : std_logic_vector(31 downto 0);
--signal dma_dat_i : std_logic_vector((32*c_DMA_WB_SLAVES_NB)-1 downto 0);
--signal dma_dat_o : std_logic_vector(31 downto 0);
--signal dma_sel : std_logic_vector(3 downto 0);
--signal dma_cyc : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
--signal dma_stb : std_logic;
--signal dma_we : std_logic;
--signal dma_ack : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
--signal dma_stall : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal ram_we : std_logic_vector(0 downto 0);
signal ddr_dma_adr : std_logic_vector(29 downto 0);
-- SPI
signal spi_slave_select : std_logic_vector(7 downto 0);
signal pllout_clk_sys : std_logic;
signal pllout_clk_dmtd : std_logic;
signal pllout_clk_fb_pllref : std_logic;
signal pllout_clk_fb_dmtd : std_logic;
signal si57x_clk : std_logic;
signal clk_20m_vcxo_buf : std_logic;
signal clk_125m_pllref : std_logic;
signal clk_sys : std_logic;
signal clk_dmtd : std_logic;
signal dac_rst_n : std_logic;
signal led_divider : unsigned(23 downto 0);
--! I2C signals from white rabbit core.
signal wrc_scl_o : std_logic := '1'; --! By default, don't drive from WRC.
signal wrc_scl_i : std_logic := '1'; --! ... ie. set high.
signal wrc_sda_o : std_logic;
signal wrc_sda_i : std_logic;
--! I2C signals from IPBus.
signal ipb_scl_o : std_logic := '1'; --! By default, don't drive from IPBus
signal ipb_scl_i : std_logic := '1'; --! ... ie. set high.
signal ipb_sda_o : std_logic;
signal ipb_sda_i : std_logic;
signal sfp_scl_o : std_logic_vector(1 downto 0) := ( others => '0' );
signal sfp_scl_i : std_logic_vector(1 downto 0);
signal sfp_sda_o : std_logic_vector(1 downto 0);
signal sfp_sda_i : std_logic_vector(1 downto 0);
--! White Rabbit Signals
signal dio : std_logic_vector(3 downto 0);
signal dac_hpll_load_p1 : std_logic;
signal dac_dpll_load_p1 : std_logic;
signal dac_hpll_data : std_logic_vector(15 downto 0);
signal dac_dpll_data : std_logic_vector(15 downto 0);
signal pps : std_logic;
signal pps_led : std_logic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_k : std_logic;
-- signal phy_tx_k : std_logic_vector(1 downto 0);
signal phy_tx_disparity : std_logic;
signal phy_tx_enc_err : std_logic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_rx_rbclk : std_logic;
signal phy_rx_k : std_logic;
-- signal phy_rx_k : std_logic_vector(1 downto 0);
signal phy_rx_enc_err : std_logic;
signal phy_rx_bitslide : std_logic_vector(3 downto 0);
signal phy_rst : std_logic;
signal phy_loopen : std_logic;
signal dio_in : std_logic_vector(4 downto 0);
signal dio_out : std_logic_vector(4 downto 0);
signal dio_clk : std_logic;
signal local_reset_n : std_logic;
signal button1_synced : std_logic_vector(2 downto 0);
signal genum_wb_out : t_wishbone_master_out;
signal genum_wb_in : t_wishbone_master_in;
signal genum_csr_ack_i : std_logic;
signal wrc_slave_i : t_wishbone_slave_in;
signal wrc_slave_o : t_wishbone_slave_out;
signal owr_en : std_logic_vector(1 downto 0);
signal owr_i : std_logic_vector(1 downto 0);
signal wb_adr : std_logic_vector(31 downto 0); --c_BAR0_APERTURE-priv_log2_ceil(c_CSR_WB_SLAVES_NB+1)-1 downto 0);
signal etherbone_rst_n : std_logic;
signal etherbone_src_out : t_wrf_source_out;
signal etherbone_src_in : t_wrf_source_in;
signal etherbone_snk_out : t_wrf_sink_out;
signal etherbone_snk_in : t_wrf_sink_in;
signal etherbone_wb_out : t_wishbone_master_out;
signal etherbone_wb_in : t_wishbone_master_in;
signal etherbone_cfg_in : t_wishbone_slave_in;
signal etherbone_cfg_out : t_wishbone_slave_out;
constant c_NMAROC_SLAVES : integer := 6;
-- expansion IO block has one IPBus slave. I2C has another
constant c_NSLAVES : positive := c_NMAROC_SLAVES+2; -- number of IPBus slaves in system
signal s_ipb_clk : std_logic;
signal s_ipb_wbus : ipb_wbus_array(c_NSLAVES-1 downto 0);
signal s_ipb_rbus : ipb_rbus_array(c_NSLAVES-1 downto 0);
signal s_ipb_rst : std_logic := '0';
signal s_phy_rstb : std_logic;
signal s_clk_logic_xtal : std_logic;
-- Signals that used to be connected at the top level...
signal uart_rxd , uart_txd : std_logic;
-- FIXME Move to separate process
signal s_ADC_DAV_d1, s_ADC_DAV_d2: STD_LOGIC;
signal s_OUT_ADC_d1, s_OUT_ADC_d2: STD_LOGIC;
attribute shreg_extract : string; -- Don't want synchronizer registers optimized to SRL16
attribute shreg_extract of s_ADC_DAV_d1: signal is "no";
attribute shreg_extract of s_ADC_DAV_d2: signal is "no";
attribute shreg_extract of s_OUT_ADC_d1: signal is "no";
attribute shreg_extract of s_OUT_ADC_d2: signal is "no";
-- trigger on GPIO connector
signal s_gpio_trigger: STD_LOGIC;
begin
-- Leave the White Rabit SFP I2C bus and the one-wire bus floating.
sfp_mod_def1_b(0) <= '1';
sfp_mod_def2_b(0) <= '1';
one_wire_b <= '1';
cmp_clk_vcxo : BUFG
port map (
O => clk_20m_vcxo_buf,
I => clk_20m_vcxo_i);
cmp_pllrefclk_buf : IBUFGDS
generic map (
DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n buffer input (connect directly to top-level port)
);
------------------------------------------------------------------------------
-- Active high reset
------------------------------------------------------------------------------
--process(clk_sys)
--begin
-- if rising_edge(clk_sys) then
-- led_divider <= led_divider + 1;
-- end if;
--end process;
-- Drive I2C lines.
fpga_scl_b <= '0' when ((ipb_scl_o = '0') ) else 'Z';
fpga_sda_b <= '0' when ((ipb_sda_o = '0' )) else 'Z';
ipb_scl_i <= fpga_scl_b;
ipb_sda_i <= fpga_sda_b;
cmp_clk_sys_buf : BUFG
port map (
O => clk_sys,
I => pllout_clk_sys);
cmp_clk_dmtd_buf : BUFG
port map (
O => clk_dmtd,
I => pllout_clk_dmtd);
si57x_oe_o <= '1';
-------------------------------------------------------------------------
-- Instantiate MAROC interface
-------------------------------------------------------------------------
-- FIXME - s_ipb_rst should be connected to something sensible...
-- BODGE BODGE
p_register_adc_data: process (s_ipb_clk) is
begin -- process p_register_data
if falling_edge(s_ipb_clk) then -- falling clock edge
s_ADC_DAV_d1 <= ADC_DAV_I;
s_OUT_ADC_d1 <= OUT_ADC_I;
end if;
if rising_edge(s_ipb_clk) then -- rising clock edge
s_ADC_DAV_d2 <= s_ADC_DAV_d1;
s_OUT_ADC_d2 <= s_OUT_ADC_d1;
end if;
end process p_register_adc_data;
-- BODGE BODGE - put down in MAROC interface
maroc: entity work.marocInterface
generic map (
g_NSLAVES => c_NMAROC_SLAVES) -- number of IPBus slaves inside the maroc interface.
port map (
-- Interface to IPBus
ipb_clk_i => s_ipb_clk,
ipb_in => s_ipb_wbus(c_NMAROC_SLAVES-1 downto 0),
ipb_out => s_ipb_rbus(c_NMAROC_SLAVES-1 downto 0),
rst_i => s_ipb_rst,
-- fast clock
clk_fast_i => clk_125m_pllref,
-- Trigger signals
external_Trigger_i => s_globaltrig_to_fpga,
gpio_Trigger_i => s_gpio_trigger,
trigger_o => s_globaltrig_from_fpga,
-- Pins connected to MAROC
CK_40M_P_O => CK_40M_P_O,
CK_40M_N_O => CK_40M_N_O,
HOLD2_O => HOLD2_O,
HOLD1_O => HOLD1_O,
OR_I => OR_I,
MAROC_TRIGGER_I => MAROC_TRIGGER_I,
EN_OTAQ_O => EN_OTAQ_O,
CTEST_O => CTEST_O,
ADC_DAV_I => s_ADC_DAV_d2 , -- ADC_DAV_I,
OUT_ADC_I => s_OUT_ADC_d2 , -- OUT_ADC_I,
START_ADC_N_O => START_ADC_N_O,
RST_ADC_N_O => RST_ADC_N_O,
RST_SC_N_O => RST_SC_N_O,
Q_SC_I => Q_SC_I,
D_SC_O => D_SC_O,
RST_R_N_O => RST_R_N_O,
Q_R_I => Q_R_I,
D_R_O => D_R_O,
CK_R_O => CK_R_O,
CK_SC_O => CK_SC_O
);
-----------------------------------------
-- Differential Buffers
-----------------------------------------
-- For global (bussed) trigger
gtrig_ibuf : IBUFDS
generic map (
DIFF_TERM => true)
port map (
O => s_globaltrig_to_fpga,
I => lvds_globaltrig_to_fpga_p_i,
IB => lvds_globaltrig_to_fpga_n_i
);
gtrig_obuf : OBUFDS
port map (
I => s_globaltrig_from_fpga,
O => lvds_globaltrig_from_fpga_p_o,
OB => lvds_globaltrig_from_fpga_n_o
);
-- For "Or trigger" - input is "ORed" with local trigger then sent on
otrig_ibuf : IBUFDS
generic map (
DIFF_TERM => true)
port map (
O => s_otrig_to_fpga,
I => lvds_otrig_to_fpga_p_i,
IB => lvds_otrig_to_fpga_n_i
);
otrig_obuf : OBUFDS
port map (
I => s_otrig_from_fpga,
O => lvds_otrig_from_fpga_p_o,
OB => lvds_otrig_from_fpga_n_o
);
-- Differential Buffers for bussed clock
gclk_ibuf : IBUFGDS
generic map (
DIFF_TERM => true)
port map (
O => s_gclk_to_fpga,
I => lvds_gclk_to_fpga_p_i,
IB => lvds_gclk_to_fpga_n_i
);
gclk_obuf : OBUFDS
port map (
I => s_gclk_from_fpga,
O => lvds_gclk_from_fpga_p_o,
OB => lvds_gclk_from_fpga_n_o
);
-- FIXME - dummy bodge for now, connect input to output
p_register_data: process (s_gclk_to_fpga) is
begin -- process p_register_data
if rising_edge(s_gclk_to_fpga) then
s_otrig_from_fpga <= s_otrig_to_fpga;
s_gclk_from_fpga <= s_otrig_to_fpga;
end if;
end process p_register_data;
--FIXME this doesn't make much sense but drive to global clock and trigger
enable_gclk_drive_o <= '1';
enable_globaltrig_drive_o <= '1';
-- N.B. connect any GPIO disconnected, unused gpio pins to '0' to stop them being optimized away
gpio(0) <= ADC_DAV_I;
gpio(1) <= OUT_ADC_I;
gpio(2) <= s_ADC_DAV_d1;
gpio(3) <= s_OUT_ADC_d1;
gpio(4) <= si57x_clk;
gpio(5) <= '0';
-- gpio(6) <= uart_txd;
-- uart_rxd <= gpio(7);
gpio(6) <= '0';
s_gpio_trigger <= gpio(7);
-- FIXME - buffer input clock signal to avoid optimiziation
cmp_si57x_buffer : IBUFGDS
generic map(
DIFF_TERM => true,
IBUF_LOW_PWR => true,
IOSTANDARD => "DEFAULT")
port map (
O => si57x_clk,
I => si57x_clk_p_i ,
IB => si57x_clk_n_i
);
sfp_rate_select_b(0) <= '1'; --! Connect high for full rate.
sfp_rate_select_b(1) <= '1';
-----------------------------------------------------------------------------
-- IPBus interface
-----------------------------------------------------------------------------
IPBusInterface_inst : entity work.IPBusInterfaceGTP
GENERIC MAP (
NUM_EXT_SLAVES => c_NMAROC_SLAVES+2, --! Total number of IPBus slave busses = number in MAROC plus one for External IO
BUILD_SIMULATED_ETHERNET => BUILD_SIMULATED_ETHERNET
)
PORT MAP (
-- dedicated clock to GTP tile.
gtp_clkp => fpga_pll_ref_clk_123_p_i,
gtp_clkn => fpga_pll_ref_clk_123_n_i,
-- Serial I/O to GTP on Spartan-6
gtp_txp => sfp_txp_o,
gtp_txn => sfp_txn_o,
gtp_rxp => sfp_rxp_i,
gtp_rxn => sfp_rxn_i,
sfp_los => sfp_los_i(1),
-- SFP control lines.
sfp_scl_o => sfp_scl_o(1),
sfp_scl_i => sfp_scl_i(1),
sfp_sda_o => sfp_sda_o(1),
sfp_sda_i => sfp_sda_i(1),
sfp_det_i => sfp_mod_def0_b(1),
-- SATA connector
gtp_aux_txp => sata_txp_o,
gtp_aux_txn => sata_txn_o,
gtp_aux_rxp => sata_rxp_i,
gtp_aux_rxn => sata_rxn_i,
ipbr_i => s_ipb_rbus,
sysclk_i => clk_125m_pllref,
clocks_locked_o => leds_o(2),
pkt_rx_led_o => leds_o(1),
pkt_tx_led_o => leds_o(0),
ipb_clk_o => s_ipb_clk,
ipb_rst_o => s_ipb_rst,
ipbw_o => s_ipb_wbus,
onehz_o => leds_o(3),
phy_rstb_o => s_phy_rstb,
dip_switch_i => dip_switch_i,
clk_logic_xtal_o => s_clk_logic_xtal
);
leds_o(4) <= sfp_los_i(1);
-- Tidy up....
-- Left over signals from White Rabbit
--leds_o(0) <= '0';
--leds_o(1) <= '0';
sfp_tx_disable_o(0) <= '0';
-- SFP control signals for IPBus SFP
sfp_mod_def1_b(1) <= '0' when sfp_scl_o(1) = '0' else 'Z';
sfp_mod_def2_b(1) <= '0' when sfp_sda_o(1) = '0' else 'Z';
sfp_scl_i(1) <= sfp_mod_def1_b(1);
sfp_sda_i(1) <= sfp_mod_def2_b(1);
sfp_tx_disable_o(1) <= '0';
-----------------------------------------------------------------------------
-- expansionIO_inst :
-----------------------------------------------------------------------------
ExpansionIO_inst : entity work.ExpansionIO
port map (
-- IPBus
ipbus_clk_i => s_ipb_clk,
ipbus_reset_i => s_ipb_rst,
ipbus_wbus_i => s_ipb_wbus(c_NMAROC_SLAVES),
ipbus_rbus_o => s_ipb_rbus(c_NMAROC_SLAVES),
-- Data....
lvds_left_data_p_b => lvds_left_data_p_b,
lvds_left_data_n_b => lvds_left_data_n_b,
lvds_left_clk_p_b => lvds_left_clk_p_b,
lvds_left_clk_n_b => lvds_left_clk_n_b,
lvds_right_data_p_b => lvds_right_data_p_b ,
lvds_right_data_n_b => lvds_right_data_n_b ,
lvds_right_clk_p_b => lvds_right_clk_p_b,
lvds_right_clk_n_b => lvds_right_clk_n_b
);
-----------------------------------------------------------------------------
-- I2C master
-----------------------------------------------------------------------------
i2cMaster_inst: entity work.i2c_master
PORT MAP (
i2c_scl_i => ipb_scl_i,
i2c_sda_i => ipb_sda_i,
ipbus_clk_i => s_ipb_clk,
ipbus_i => s_ipb_wbus(c_NMAROC_SLAVES+1),
ipbus_reset_i => s_ipb_rst,
i2c_scl_enb_o => ipb_scl_o,
i2c_sda_enb_o => ipb_sda_o,
ipbus_o => s_ipb_rbus(c_NMAROC_SLAVES+1)
);
end rtl;
--=============================================================================
--! @file pc049a_top.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture work. pc049a_top.rtl
--
--! @brief Top level for single-MAROC eval board simple-design. No White Rabbit\n
--! \n
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 6/10/2016
--
--! @version v0.1
--
--! @details
--! Includes Maroc IPBus slaves and IPBus core.
--! LEDs:
--! LED(2) - IPBus clocks locked. ( should be on )
--! LED(3) - One Hz heart-beat ( should strobe at 1Hz)
--! LED(4) - LOS for IPBus SFP ( should be off )
--!
--! <b>Dependencies:</b>\n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by:</b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
--! @todo <next thing to do> \n
--! <another thing to do> \n
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
-- Packages for White Rabbit
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.wr_xilinx_pkg.all;
use work.etherbone_pkg.all;
-- Packages for IPBus
LIBRARY work;
USE work.ipbus.all;
USE work.emac_hostbus_decl.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.wishbone_pkg.all;
entity pc049a_top is
generic
(
BUILD_SIMULATED_ETHERNET : integer := 0 --! set to 1 to build with simulated Ethernet interface using Modelsim FLI
);
port
(
-- Global ports
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_125m_pllref_p_i , clk_125m_pllref_n_i : in std_logic; -- 125 MHz PLL reference
fpga_pll_ref_clk_101_p_i , fpga_pll_ref_clk_101_n_i : in std_logic; -- Dedicated clock for Xilinx GTP transceiver
fpga_pll_ref_clk_123_p_i , fpga_pll_ref_clk_123_n_i : in std_logic; -- Dedicated clock for Xilinx GTP transceiver
si57x_clk_p_i , si57x_clk_n_i : in std_logic ; -- clock from si570 programmable oscillator. Default = 100MHz
si57x_oe_o : out std_logic := '1'; -- Chip enable for SI570
-- General Purpose Interface
GPIO : inout std_logic_vector(7 downto 0);
-- Push buttons
button1_i : in std_logic := 'H';
button2_i : in std_logic := 'H';
-- LEDs and DIP switch
leds_o : out std_logic_vector(4 downto 0);
dip_switch_i : in std_logic_vector(3 downto 0);
-- SPI interface for DACs that tune VCXO frequencies
pll25dac_sclk_o : out std_logic := '0';
pll25dac_din_o : out std_logic := '0';
pll25dac1_sync_n_o : out std_logic := '1';
pll25dac2_sync_n_o : out std_logic := '1';
-- I2C bus
fpga_scl_b : inout std_logic;
fpga_sda_b : inout std_logic;
one_wire_b : inout std_logic; -- 1-Wire interface to DS18B20
-------------------------------------------------------------------------
-- SFP pins.
-------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_b : in std_logic_vector(1 downto 0); -- sfp detect
sfp_mod_def1_b : inout std_logic_vector(1 downto 0); -- scl
sfp_mod_def2_b : inout std_logic_vector(1 downto 0); -- sda
sfp_rate_select_b : inout std_logic_vector(1 downto 0);
sfp_tx_fault_i : in std_logic_vector(1 downto 0);
sfp_tx_disable_o : out std_logic_vector(1 downto 0);
sfp_los_i : in std_logic_vector(1 downto 0);
-------------------------------------------------------------------------
-- eSATA pins. White Rabbit=0 , IPBus=1
-------------------------------------------------------------------------
sata_txp_o : out std_logic;
sata_txn_o : out std_logic;
sata_rxp_i : in std_logic;
sata_rxn_i : in std_logic;
-----------------------------------------
--UART
-----------------------------------------
-- uart_rxd_i : in std_logic;
-- uart_txd_o : out std_logic;
-----------------------------------------
-- MAROC connections
-----------------------------------------
CK_40M_P_O,CK_40M_N_O : out STD_LOGIC;
HOLD2_O: out STD_LOGIC;
HOLD1_O: out STD_LOGIC;
OR_I: in STD_LOGIC_VECTOR(2 downto 1);
MAROC_TRIGGER_I: in std_logic_vector(63 downto 0);
EN_OTAQ_O: out STD_LOGIC;
CTEST_O: out STD_LOGIC_VECTOR(5 downto 0); -- 4-bit R/2R DAC
ADC_DAV_I: in STD_LOGIC;
OUT_ADC_I: in STD_LOGIC;
START_ADC_N_O: out STD_LOGIC;
RST_ADC_N_O: out STD_LOGIC;
RST_SC_N_O: out STD_LOGIC;
Q_SC_I: in STD_LOGIC;
D_SC_O: out STD_LOGIC;
RST_R_N_O: out STD_LOGIC;
Q_R_I: in STD_LOGIC;
D_R_O: out STD_LOGIC;
CK_R_O: out STD_LOGIC;
CK_SC_O: out STD_LOGIC;
-----------------------------------------
-- Expansion Connectors
-----------------------------------------
-- fixed direction for now....
-- Data on left connector
lvds_left_data_p_b, lvds_left_data_n_b: out std_logic_vector(15 downto 0);
lvds_left_clk_p_b,lvds_left_clk_n_b: in std_logic;
-- Data on right connector
lvds_right_data_p_b,lvds_right_data_n_b: out std_logic_vector(15 downto 0);
lvds_right_clk_p_b,lvds_right_clk_n_b: in std_logic;
-- Global trigger lines
lvds_globaltrig_from_fpga_p_o: out std_logic;
lvds_globaltrig_from_fpga_n_o: out std_logic;
enable_globaltrig_drive_o: out std_logic;
lvds_globaltrig_to_fpga_p_i: in std_logic;
lvds_globaltrig_to_fpga_n_i: in std_logic;
-- "OR trigger" lines
lvds_otrig_from_fpga_p_o: out std_logic;
lvds_otrig_from_fpga_n_o: out std_logic;
lvds_otrig_to_fpga_p_i: in std_logic;
lvds_otrig_to_fpga_n_i: in std_logic;
-- Global clock lines
lvds_gclk_from_fpga_p_o: out std_logic;
lvds_gclk_from_fpga_n_o: out std_logic;
enable_gclk_drive_o: out std_logic;
lvds_gclk_to_fpga_p_i: in std_logic;
lvds_gclk_to_fpga_n_i: in std_logic
);
end pc049a_top;
architecture rtl of pc049a_top is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component spec_reset_gen
port (
clk_sys_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic);
end component;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_BAR0_APERTURE : integer := 20;
constant c_CSR_WB_SLAVES_NB : integer := 1;
constant c_DMA_WB_SLAVES_NB : integer := 1;
constant c_DMA_WB_ADDR_WIDTH : integer := 26;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal s_globaltrig_to_fpga, s_globaltrig_from_fpga : std_logic;
signal s_otrig_to_fpga , s_otrig_from_fpga : std_logic;
signal s_gclk_to_fpga , s_gclk_from_fpga : std_logic;
-- Dedicated clock for GTP transceiver
signal gtp_dedicated_clk : std_logic_vector(1 downto 0);
-- P2L colck PLL status
signal p2l_pll_locked : std_logic;
-- Reset
signal rst_a : std_logic;
-- DMA wishbone bus
--signal dma_adr : std_logic_vector(31 downto 0);
--signal dma_dat_i : std_logic_vector((32*c_DMA_WB_SLAVES_NB)-1 downto 0);
--signal dma_dat_o : std_logic_vector(31 downto 0);
--signal dma_sel : std_logic_vector(3 downto 0);
--signal dma_cyc : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
--signal dma_stb : std_logic;
--signal dma_we : std_logic;
--signal dma_ack : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
--signal dma_stall : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal ram_we : std_logic_vector(0 downto 0);
signal ddr_dma_adr : std_logic_vector(29 downto 0);
-- SPI
signal spi_slave_select : std_logic_vector(7 downto 0);
signal pllout_clk_sys : std_logic;
signal pllout_clk_dmtd : std_logic;
signal pllout_clk_fb_pllref : std_logic;
signal pllout_clk_fb_dmtd : std_logic;
signal si57x_clk : std_logic;
signal clk_20m_vcxo_buf : std_logic;
signal clk_125m_pllref : std_logic;
signal clk_sys : std_logic;
signal clk_dmtd : std_logic;
signal dac_rst_n : std_logic;
signal led_divider : unsigned(23 downto 0);
--! I2C signals from white rabbit core.
signal wrc_scl_o : std_logic := '1'; --! By default, don't drive from WRC.
signal wrc_scl_i : std_logic := '1'; --! ... ie. set high.
signal wrc_sda_o : std_logic;
signal wrc_sda_i : std_logic;
--! I2C signals from IPBus.
signal ipb_scl_o : std_logic := '1'; --! By default, don't drive from IPBus
signal ipb_scl_i : std_logic := '1'; --! ... ie. set high.
signal ipb_sda_o : std_logic;
signal ipb_sda_i : std_logic;
signal sfp_scl_o : std_logic_vector(1 downto 0) := ( others => '0' );
signal sfp_scl_i : std_logic_vector(1 downto 0);
signal sfp_sda_o : std_logic_vector(1 downto 0);
signal sfp_sda_i : std_logic_vector(1 downto 0);
--! White Rabbit Signals
signal dio : std_logic_vector(3 downto 0);
signal dac_hpll_load_p1 : std_logic;
signal dac_dpll_load_p1 : std_logic;
signal dac_hpll_data : std_logic_vector(15 downto 0);
signal dac_dpll_data : std_logic_vector(15 downto 0);
signal pps : std_logic;
signal pps_led : std_logic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_k : std_logic;
-- signal phy_tx_k : std_logic_vector(1 downto 0);
signal phy_tx_disparity : std_logic;
signal phy_tx_enc_err : std_logic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_rx_rbclk : std_logic;
signal phy_rx_k : std_logic;
-- signal phy_rx_k : std_logic_vector(1 downto 0);
signal phy_rx_enc_err : std_logic;
signal phy_rx_bitslide : std_logic_vector(3 downto 0);
signal phy_rst : std_logic;
signal phy_loopen : std_logic;
signal dio_in : std_logic_vector(4 downto 0);
signal dio_out : std_logic_vector(4 downto 0);
signal dio_clk : std_logic;
signal local_reset_n : std_logic;
signal button1_synced : std_logic_vector(2 downto 0);
signal genum_wb_out : t_wishbone_master_out;
signal genum_wb_in : t_wishbone_master_in;
signal genum_csr_ack_i : std_logic;
signal wrc_slave_i : t_wishbone_slave_in;
signal wrc_slave_o : t_wishbone_slave_out;
signal owr_en : std_logic_vector(1 downto 0);
signal owr_i : std_logic_vector(1 downto 0);
signal wb_adr : std_logic_vector(31 downto 0); --c_BAR0_APERTURE-priv_log2_ceil(c_CSR_WB_SLAVES_NB+1)-1 downto 0);
signal etherbone_rst_n : std_logic;
signal etherbone_src_out : t_wrf_source_out;
signal etherbone_src_in : t_wrf_source_in;
signal etherbone_snk_out : t_wrf_sink_out;
signal etherbone_snk_in : t_wrf_sink_in;
signal etherbone_wb_out : t_wishbone_master_out;
signal etherbone_wb_in : t_wishbone_master_in;
signal etherbone_cfg_in : t_wishbone_slave_in;
signal etherbone_cfg_out : t_wishbone_slave_out;
constant c_NMAROC_SLAVES : integer := 6;
-- expansion IO block has one IPBus slave. I2C has another
constant c_NSLAVES : positive := c_NMAROC_SLAVES+2; -- number of IPBus slaves in system
signal s_ipb_clk : std_logic;
signal s_ipb_wbus : ipb_wbus_array(c_NSLAVES-1 downto 0);
signal s_ipb_rbus : ipb_rbus_array(c_NSLAVES-1 downto 0);
signal s_ipb_rst : std_logic := '0';
signal s_phy_rstb : std_logic;
signal s_clk_logic_xtal : std_logic;
-- Signals that used to be connected at the top level...
signal uart_rxd , uart_txd : std_logic;
-- FIXME Move to separate process
signal s_ADC_DAV_d1, s_ADC_DAV_d2: STD_LOGIC;
signal s_OUT_ADC_d1, s_OUT_ADC_d2: STD_LOGIC;
attribute shreg_extract : string; -- Don't want synchronizer registers optimized to SRL16
attribute shreg_extract of s_ADC_DAV_d1: signal is "no";
attribute shreg_extract of s_ADC_DAV_d2: signal is "no";
attribute shreg_extract of s_OUT_ADC_d1: signal is "no";
attribute shreg_extract of s_OUT_ADC_d2: signal is "no";
-- trigger on GPIO connector
signal s_gpio_trigger: STD_LOGIC;
begin
-- Leave the White Rabit SFP I2C bus and the one-wire bus floating.
sfp_mod_def1_b(0) <= '1';
sfp_mod_def2_b(0) <= '1';
one_wire_b <= '1';
cmp_clk_vcxo : BUFG
port map (
O => clk_20m_vcxo_buf,
I => clk_20m_vcxo_i);
cmp_pllrefclk_buf : IBUFGDS
generic map (
DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n buffer input (connect directly to top-level port)
);
------------------------------------------------------------------------------
-- Active high reset
------------------------------------------------------------------------------
--process(clk_sys)
--begin
-- if rising_edge(clk_sys) then
-- led_divider <= led_divider + 1;
-- end if;
--end process;
-- Drive I2C lines.
fpga_scl_b <= '0' when ((ipb_scl_o = '0') ) else 'Z';
fpga_sda_b <= '0' when ((ipb_sda_o = '0' )) else 'Z';
ipb_scl_i <= fpga_scl_b;
ipb_sda_i <= fpga_sda_b;
cmp_clk_sys_buf : BUFG
port map (
O => clk_sys,
I => pllout_clk_sys);
cmp_clk_dmtd_buf : BUFG
port map (
O => clk_dmtd,
I => pllout_clk_dmtd);
si57x_oe_o <= '1';
-------------------------------------------------------------------------
-- Instantiate MAROC interface
-------------------------------------------------------------------------
-- FIXME - s_ipb_rst should be connected to something sensible...
-- BODGE BODGE
p_register_adc_data: process (s_ipb_clk) is
begin -- process p_register_data
if falling_edge(s_ipb_clk) then -- falling clock edge
s_ADC_DAV_d1 <= ADC_DAV_I;
s_OUT_ADC_d1 <= OUT_ADC_I;
end if;
if rising_edge(s_ipb_clk) then -- rising clock edge
s_ADC_DAV_d2 <= s_ADC_DAV_d1;
s_OUT_ADC_d2 <= s_OUT_ADC_d1;
end if;
end process p_register_adc_data;
-- BODGE BODGE - put down in MAROC interface
maroc: entity work.marocInterface
generic map (
g_NSLAVES => c_NMAROC_SLAVES) -- number of IPBus slaves inside the maroc interface.
port map (
-- Interface to IPBus
ipb_clk_i => s_ipb_clk,
ipb_in => s_ipb_wbus(c_NMAROC_SLAVES-1 downto 0),
ipb_out => s_ipb_rbus(c_NMAROC_SLAVES-1 downto 0),
rst_i => s_ipb_rst,
-- fast clock
clk_fast_i => clk_125m_pllref,
-- Trigger signals
external_Trigger_i => s_globaltrig_to_fpga,
gpio_Trigger_i => s_gpio_trigger,
trigger_o => s_globaltrig_from_fpga,
-- Pins connected to MAROC
CK_40M_P_O => CK_40M_P_O,
CK_40M_N_O => CK_40M_N_O,
HOLD2_O => HOLD2_O,
HOLD1_O => HOLD1_O,
OR_I => OR_I,
MAROC_TRIGGER_I => MAROC_TRIGGER_I,
EN_OTAQ_O => EN_OTAQ_O,
CTEST_O => CTEST_O,
ADC_DAV_I => s_ADC_DAV_d2 , -- ADC_DAV_I,
OUT_ADC_I => s_OUT_ADC_d2 , -- OUT_ADC_I,
START_ADC_N_O => START_ADC_N_O,
RST_ADC_N_O => RST_ADC_N_O,
RST_SC_N_O => RST_SC_N_O,
Q_SC_I => Q_SC_I,
D_SC_O => D_SC_O,
RST_R_N_O => RST_R_N_O,
Q_R_I => Q_R_I,
D_R_O => D_R_O,
CK_R_O => CK_R_O,
CK_SC_O => CK_SC_O
);
-----------------------------------------
-- Differential Buffers
-----------------------------------------
-- For global (bussed) trigger
gtrig_ibuf : IBUFDS
generic map (
DIFF_TERM => true)
port map (
O => s_globaltrig_to_fpga,
I => lvds_globaltrig_to_fpga_p_i,
IB => lvds_globaltrig_to_fpga_n_i
);
gtrig_obuf : OBUFDS
port map (
I => s_globaltrig_from_fpga,
O => lvds_globaltrig_from_fpga_p_o,
OB => lvds_globaltrig_from_fpga_n_o
);
-- For "Or trigger" - input is "ORed" with local trigger then sent on
otrig_ibuf : IBUFDS
generic map (
DIFF_TERM => true)
port map (
O => s_otrig_to_fpga,
I => lvds_otrig_to_fpga_p_i,
IB => lvds_otrig_to_fpga_n_i
);
otrig_obuf : OBUFDS
port map (
I => s_otrig_from_fpga,
O => lvds_otrig_from_fpga_p_o,
OB => lvds_otrig_from_fpga_n_o
);
-- Differential Buffers for bussed clock
gclk_ibuf : IBUFGDS
generic map (
DIFF_TERM => true)
port map (
O => s_gclk_to_fpga,
I => lvds_gclk_to_fpga_p_i,
IB => lvds_gclk_to_fpga_n_i
);
gclk_obuf : OBUFDS
port map (
I => s_gclk_from_fpga,
O => lvds_gclk_from_fpga_p_o,
OB => lvds_gclk_from_fpga_n_o
);
-- FIXME - dummy bodge for now, connect input to output
p_register_data: process (s_gclk_to_fpga) is
begin -- process p_register_data
if rising_edge(s_gclk_to_fpga) then
s_otrig_from_fpga <= s_otrig_to_fpga;
s_gclk_from_fpga <= s_otrig_to_fpga;
end if;
end process p_register_data;
--FIXME this doesn't make much sense but drive to global clock and trigger
enable_gclk_drive_o <= '1';
enable_globaltrig_drive_o <= '1';
-- N.B. connect any GPIO disconnected, unused gpio pins to '0' to stop them being optimized away
gpio(0) <= ADC_DAV_I;
gpio(1) <= OUT_ADC_I;
gpio(2) <= s_ADC_DAV_d1;
gpio(3) <= s_OUT_ADC_d1;
gpio(4) <= si57x_clk;
gpio(5) <= '0';
-- gpio(6) <= uart_txd;
-- uart_rxd <= gpio(7);
gpio(6) <= '0';
s_gpio_trigger <= gpio(7);
-- FIXME - buffer input clock signal to avoid optimiziation
cmp_si57x_buffer : IBUFGDS
generic map(
DIFF_TERM => true,
IBUF_LOW_PWR => true,
IOSTANDARD => "DEFAULT")
port map (
O => si57x_clk,
I => si57x_clk_p_i ,
IB => si57x_clk_n_i
);
sfp_rate_select_b(0) <= '1'; --! Connect high for full rate.
sfp_rate_select_b(1) <= '1';
-----------------------------------------------------------------------------
-- IPBus interface
-----------------------------------------------------------------------------
IPBusInterface_inst : entity work.IPBusInterfaceGTP
GENERIC MAP (
NUM_EXT_SLAVES => c_NMAROC_SLAVES+2, --! Total number of IPBus slave busses = number in MAROC plus one for External IO
BUILD_SIMULATED_ETHERNET => BUILD_SIMULATED_ETHERNET
)
PORT MAP (
-- dedicated clock to GTP tile.
gtp_clkp => fpga_pll_ref_clk_123_p_i,
gtp_clkn => fpga_pll_ref_clk_123_n_i,
-- Serial I/O to GTP on Spartan-6
gtp_txp => sfp_txp_o,
gtp_txn => sfp_txn_o,
gtp_rxp => sfp_rxp_i,
gtp_rxn => sfp_rxn_i,
sfp_los => sfp_los_i(1),
-- SFP control lines.
sfp_scl_o => sfp_scl_o(1),
sfp_scl_i => sfp_scl_i(1),
sfp_sda_o => sfp_sda_o(1),
sfp_sda_i => sfp_sda_i(1),
sfp_det_i => sfp_mod_def0_b(1),
-- SATA connector
gtp_aux_txp => sata_txp_o,
gtp_aux_txn => sata_txn_o,
gtp_aux_rxp => sata_rxp_i,
gtp_aux_rxn => sata_rxn_i,
ipbr_i => s_ipb_rbus,
sysclk_i => clk_125m_pllref,
clocks_locked_o => leds_o(2),
ipb_clk_o => s_ipb_clk,
ipb_rst_o => s_ipb_rst,
ipbw_o => s_ipb_wbus,
onehz_o => leds_o(3),
phy_rstb_o => s_phy_rstb,
dip_switch_i => dip_switch_i,
clk_logic_xtal_o => s_clk_logic_xtal
);
leds_o(4) <= sfp_los_i(1);
-- Tidy up....
-- Left over signals from White Rabbit
leds_o(0) <= '0';
leds_o(1) <= '0';
sfp_tx_disable_o(0) <= '0';
-- SFP control signals for IPBus SFP
sfp_mod_def1_b(1) <= '0' when sfp_scl_o(1) = '0' else 'Z';
sfp_mod_def2_b(1) <= '0' when sfp_sda_o(1) = '0' else 'Z';
sfp_scl_i(1) <= sfp_mod_def1_b(1);
sfp_sda_i(1) <= sfp_mod_def2_b(1);
sfp_tx_disable_o(1) <= '0';
-----------------------------------------------------------------------------
-- expansionIO_inst :
-----------------------------------------------------------------------------
ExpansionIO_inst : entity work.ExpansionIO
port map (
-- IPBus
ipbus_clk_i => s_ipb_clk,
ipbus_reset_i => s_ipb_rst,
ipbus_wbus_i => s_ipb_wbus(c_NMAROC_SLAVES),
ipbus_rbus_o => s_ipb_rbus(c_NMAROC_SLAVES),
-- Data....
lvds_left_data_p_b => lvds_left_data_p_b,
lvds_left_data_n_b => lvds_left_data_n_b,
lvds_left_clk_p_b => lvds_left_clk_p_b,
lvds_left_clk_n_b => lvds_left_clk_n_b,
lvds_right_data_p_b => lvds_right_data_p_b ,
lvds_right_data_n_b => lvds_right_data_n_b ,
lvds_right_clk_p_b => lvds_right_clk_p_b,
lvds_right_clk_n_b => lvds_right_clk_n_b
);
-----------------------------------------------------------------------------
-- I2C master
-----------------------------------------------------------------------------
i2cMaster_inst: entity work.i2c_master
PORT MAP (
i2c_scl_i => ipb_scl_i,
i2c_sda_i => ipb_sda_i,
ipbus_clk_i => s_ipb_clk,
ipbus_i => s_ipb_wbus(c_NMAROC_SLAVES+1),
ipbus_reset_i => s_ipb_rst,
i2c_scl_enb_o => ipb_scl_o,
i2c_sda_enb_o => ipb_sda_o,
ipbus_o => s_ipb_rbus(c_NMAROC_SLAVES+1)
);
end rtl;
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