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- MarocConfiguration.py  - passes configuration file name to MarocSC object and reads from configuration file.

- MarocHistograms.py - replaced print statements with logger.info / logger.debug

- MarocSC.py - debugged so can now read flags, parameters and register values from configuration file.

- takeMarocData.py - added command line switch to set configuration file name



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MarocConfiguration - class that writes to registers in FPGA , including register that controls interface to MAROC slow control. Reads data to write to slow control from CSV file.

takeMarocData.py - passes number of events to readout thread. Passes file name to recording thread. Waits for threads to finish before exiting

MarocRecording.py - eventually sorted out how to record to a ROOT file. Inefficient at the moment. 

MarocSC.py - started to add ability to store register values in CSV file as well as contents of MAROC SC registers.

MarocHistogrammingThread.py,MarocReadoutThread.py,MarocRecordingThread.py,MarocUnpackingThread.py - when readout thread reaches event limit it passes a "special" event along processing pipeline that causes threads to exit.

MarocRunControlThread.py - beginnings of a run-control thread. Not used at the moment.



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takeMarocData - multi-threaded top level script to take data.

MarocReadoutThread , MarocHistogrammingThread , MarocRecordingThread - classes that inherit from Threading class



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Some documentation changes

Changed Slow control shift register to have optional reset before shifting data.
( Still at least one bug - doesn't store data shifted out of MAROC correctly )

Added register stages to risingEdgeDetect




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* marocInterface_rtl.vhd - detects the falling edge of status from marocADC
* circuit to detect falling edge of status hdl/fallingEdgeDetect_rtl.vhd



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Edited pc049a_top.vhd in order to only build the IPBus ( not the White Rabbit ) cores by default. Reduces power dissipation and keeps chip cooler.



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* Took pictures of assembled boards.

* Exported netlist from Circuit schematic.

* Changed clocks to be 31.25MHz IPBus clock.

* General tidying. Unfortunately, latest design doesn't respond to "ping"....



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Changing clearanges to get ground pins on DIN connectors connected to ground planes on layers 7 , 10

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* Started to construct top level schematic

* Added some block diagrams




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