fmc_masterfip_csr

FMC masterFIP core registers

Wishbone slave for FMC masterFIP core

1. Memory map summary
2. HDL symbol
3. Register description
3.1. rstn
3.2. id
3.3. dbg
3.4. adc
3.5. ext sync
3.6. ext sync pulses cnt
3.7. bus speed
3.8. macrocycle lgth
3.9. turnaround lgth
3.10. silence lgth
3.11. macrocycle time cnt
3.12. macrocycles number cnt
3.13. turnaround time cnt
3.14. silence time cnt
3.15. tx ctrl
3.16. tx status
3.17. fieldrive wdgn
3.18. fieldrive txer cnt
3.19. fieldrive txer tstamp
3.20. rx ctrl
3.21. rx status
3.22. rx status current byte index
3.23. rx data ctrl byte
3.24. rx data reg1
3.25. rx data reg2
3.26. rx data reg3
3.27. rx data reg4
3.28. rx data reg5
3.29. rx data reg6
3.30. rx data reg7
3.31. rx data reg8
3.32. rx data reg9
3.33. rx data reg10
3.34. rx data reg11
3.35. rx data reg12
3.36. rx data reg13
3.37. rx data reg14
3.38. rx data reg15
3.39. rx data reg16
3.40. rx data reg17
3.41. rx data reg18
3.42. rx data reg19
3.43. rx data reg20
3.44. rx data reg21
3.45. rx data reg22
3.46. rx data reg23
3.47. rx data reg24
3.48. rx data reg25
3.49. rx data reg26
3.50. rx data reg27
3.51. rx data reg28
3.52. rx data reg29
3.53. rx data reg30
3.54. rx data reg31
3.55. rx data reg32
3.56. rx data reg33
3.57. rx data reg34
3.58. rx data reg35
3.59. rx data reg36
3.60. rx data reg37
3.61. rx data reg38
3.62. rx data reg39
3.63. rx data reg40
3.64. rx data reg41
3.65. rx data reg42
3.66. rx data reg43
3.67. rx data reg44
3.68. rx data reg45
3.69. rx data reg46
3.70. rx data reg47
3.71. rx data reg48
3.72. rx data reg49
3.73. rx data reg50
3.74. rx data reg51
3.75. rx data reg52
3.76. rx data reg53
3.77. rx data reg54
3.78. rx data reg55
3.79. rx data reg56
3.80. rx data reg57
3.81. rx data reg58
3.82. rx data reg59
3.83. rx data reg60
3.84. rx data reg61
3.85. rx data reg62
3.86. rx data reg63
3.87. rx data reg64
3.88. rx data reg65
3.89. rx data reg66
3.90. rx data reg67
3.91. tx ctrl byte
3.92. tx data reg1
3.93. tx data reg2
3.94. tx data reg3
3.95. tx data reg4
3.96. tx data reg5
3.97. tx data reg6
3.98. tx data reg7
3.99. tx data reg8
3.100. tx data reg9
3.101. tx data reg10
3.102. tx data reg11
3.103. tx data reg12
3.104. tx data reg13
3.105. tx data reg14
3.106. tx data reg15
3.107. tx data reg16
3.108. tx data reg17
3.109. tx data reg18
3.110. tx data reg19
3.111. tx data reg20
3.112. tx data reg21
3.113. tx data reg22
3.114. tx data reg23
3.115. tx data reg24
3.116. tx data reg25
3.117. tx data reg26
3.118. tx data reg27
3.119. tx data reg28
3.120. tx data reg29
3.121. tx data reg30
3.122. tx data reg31
3.123. tx data reg32
3.124. tx data reg33
3.125. tx data reg34
3.126. tx data reg35
3.127. tx data reg36
3.128. tx data reg37
3.129. tx data reg38
3.130. tx data reg39
3.131. tx data reg40
3.132. tx data reg41
3.133. tx data reg42
3.134. tx data reg43
3.135. tx data reg44
3.136. tx data reg45
3.137. tx data reg46
3.138. tx data reg47
3.139. tx data reg48
3.140. tx data reg49
3.141. tx data reg50
3.142. tx data reg51
3.143. tx data reg52
3.144. tx data reg53
3.145. tx data reg54
3.146. tx data reg55
3.147. tx data reg56
3.148. tx data reg57
3.149. tx data reg58
3.150. tx data reg59
3.151. tx data reg60
3.152. tx data reg61
3.153. tx data reg62
3.154. tx data reg63
3.155. tx data reg64
3.156. tx data reg65
3.157. tx data reg66
3.158. tx data reg67

1. Memory map summary

H/W Address	Type	Name	VHDL/Verilog prefix	C prefix
0x0	REG	rstn	mf_rstn	RSTN
0x1	REG	id	mf_id	ID
0x2	REG	dbg	mf_dbg	DBG
0x3	REG	adc	mf_adc	ADC
0x4	REG	ext sync	mf_ext_sync	EXT_SYNC
0x5	REG	ext sync pulses cnt	mf_ext_sync_p_cnt	EXT_SYNC_P_CNT
0x6	REG	bus speed	mf_speed	SPEED
0x7	REG	macrocycle lgth	mf_macrocyc	MACROCYC
0x8	REG	turnaround lgth	mf_turnar	TURNAR
0x9	REG	silence lgth	mf_silen	SILEN
0xa	REG	macrocycle time cnt	mf_macrocyc_time_cnt	MACROCYC_TIME_CNT
0xb	REG	macrocycles number cnt	mf_macrocyc_num_cnt	MACROCYC_NUM_CNT
0xc	REG	turnaround time cnt	mf_turnar_time_cnt	TURNAR_TIME_CNT
0xd	REG	silence time cnt	mf_silen_time_cnt	SILEN_TIME_CNT
0xe	REG	tx ctrl	mf_tx_ctrl	TX_CTRL
0xf	REG	tx status	mf_tx_stat	TX_STAT
0x10	REG	fieldrive wdgn	mf_fd_wdgn	FD_WDGN
0x11	REG	fieldrive txer cnt	mf_fd_txer_cnt	FD_TXER_CNT
0x12	REG	fieldrive txer tstamp	mf_fd_txer_tstamp	FD_TXER_TSTAMP
0x13	REG	rx ctrl	mf_rx_ctrl	RX_CTRL
0x14	REG	rx status	mf_rx_stat	RX_STAT
0x15	REG	rx status current byte index	mf_rx_stat_curr_byte_indx	RX_STAT_CURR_BYTE_INDX
0x16	REG	rx data ctrl byte	mf_rx_data_ctrl	RX_DATA_CTRL
0x17	REG	rx data reg1	mf_rx_data_reg1	RX_DATA_REG1
0x18	REG	rx data reg2	mf_rx_data_reg2	RX_DATA_REG2
0x19	REG	rx data reg3	mf_rx_data_reg3	RX_DATA_REG3
0x1a	REG	rx data reg4	mf_rx_data_reg4	RX_DATA_REG4
0x1b	REG	rx data reg5	mf_rx_data_reg5	RX_DATA_REG5
0x1c	REG	rx data reg6	mf_rx_data_reg6	RX_DATA_REG6
0x1d	REG	rx data reg7	mf_rx_data_reg7	RX_DATA_REG7
0x1e	REG	rx data reg8	mf_rx_data_reg8	RX_DATA_REG8
0x1f	REG	rx data reg9	mf_rx_data_reg9	RX_DATA_REG9
0x20	REG	rx data reg10	mf_rx_data_reg10	RX_DATA_REG10
0x21	REG	rx data reg11	mf_rx_data_reg11	RX_DATA_REG11
0x22	REG	rx data reg12	mf_rx_data_reg12	RX_DATA_REG12
0x23	REG	rx data reg13	mf_rx_data_reg13	RX_DATA_REG13
0x24	REG	rx data reg14	mf_rx_data_reg14	RX_DATA_REG14
0x25	REG	rx data reg15	mf_rx_data_reg15	RX_DATA_REG15
0x26	REG	rx data reg16	mf_rx_data_reg16	RX_DATA_REG16
0x27	REG	rx data reg17	mf_rx_data_reg17	RX_DATA_REG17
0x28	REG	rx data reg18	mf_rx_data_reg18	RX_DATA_REG18
0x29	REG	rx data reg19	mf_rx_data_reg19	RX_DATA_REG19
0x2a	REG	rx data reg20	mf_rx_data_reg20	RX_DATA_REG20
0x2b	REG	rx data reg21	mf_rx_data_reg21	RX_DATA_REG21
0x2c	REG	rx data reg22	mf_rx_data_reg22	RX_DATA_REG22
0x2d	REG	rx data reg23	mf_rx_data_reg23	RX_DATA_REG23
0x2e	REG	rx data reg24	mf_rx_data_reg24	RX_DATA_REG24
0x2f	REG	rx data reg25	mf_rx_data_reg25	RX_DATA_REG25
0x30	REG	rx data reg26	mf_rx_data_reg26	RX_DATA_REG26
0x31	REG	rx data reg27	mf_rx_data_reg27	RX_DATA_REG27
0x32	REG	rx data reg28	mf_rx_data_reg28	RX_DATA_REG28
0x33	REG	rx data reg29	mf_rx_data_reg29	RX_DATA_REG29
0x34	REG	rx data reg30	mf_rx_data_reg30	RX_DATA_REG30
0x35	REG	rx data reg31	mf_rx_data_reg31	RX_DATA_REG31
0x36	REG	rx data reg32	mf_rx_data_reg32	RX_DATA_REG32
0x37	REG	rx data reg33	mf_rx_data_reg33	RX_DATA_REG33
0x38	REG	rx data reg34	mf_rx_data_reg34	RX_DATA_REG34
0x39	REG	rx data reg35	mf_rx_data_reg35	RX_DATA_REG35
0x3a	REG	rx data reg36	mf_rx_data_reg36	RX_DATA_REG36
0x3b	REG	rx data reg37	mf_rx_data_reg37	RX_DATA_REG37
0x3c	REG	rx data reg38	mf_rx_data_reg38	RX_DATA_REG38
0x3d	REG	rx data reg39	mf_rx_data_reg39	RX_DATA_REG39
0x3e	REG	rx data reg40	mf_rx_data_reg40	RX_DATA_REG40
0x3f	REG	rx data reg41	mf_rx_data_reg41	RX_DATA_REG41
0x40	REG	rx data reg42	mf_rx_data_reg42	RX_DATA_REG42
0x41	REG	rx data reg43	mf_rx_data_reg43	RX_DATA_REG43
0x42	REG	rx data reg44	mf_rx_data_reg44	RX_DATA_REG44
0x43	REG	rx data reg45	mf_rx_data_reg45	RX_DATA_REG45
0x44	REG	rx data reg46	mf_rx_data_reg46	RX_DATA_REG46
0x45	REG	rx data reg47	mf_rx_data_reg47	RX_DATA_REG47
0x46	REG	rx data reg48	mf_rx_data_reg48	RX_DATA_REG48
0x47	REG	rx data reg49	mf_rx_data_reg49	RX_DATA_REG49
0x48	REG	rx data reg50	mf_rx_data_reg50	RX_DATA_REG50
0x49	REG	rx data reg51	mf_rx_data_reg51	RX_DATA_REG51
0x4a	REG	rx data reg52	mf_rx_data_reg52	RX_DATA_REG52
0x4b	REG	rx data reg53	mf_rx_data_reg53	RX_DATA_REG53
0x4c	REG	rx data reg54	mf_rx_data_reg54	RX_DATA_REG54
0x4d	REG	rx data reg55	mf_rx_data_reg55	RX_DATA_REG55
0x4e	REG	rx data reg56	mf_rx_data_reg56	RX_DATA_REG56
0x4f	REG	rx data reg57	mf_rx_data_reg57	RX_DATA_REG57
0x50	REG	rx data reg58	mf_rx_data_reg58	RX_DATA_REG58
0x51	REG	rx data reg59	mf_rx_data_reg59	RX_DATA_REG59
0x52	REG	rx data reg60	mf_rx_data_reg60	RX_DATA_REG60
0x53	REG	rx data reg61	mf_rx_data_reg61	RX_DATA_REG61
0x54	REG	rx data reg62	mf_rx_data_reg62	RX_DATA_REG62
0x55	REG	rx data reg63	mf_rx_data_reg63	RX_DATA_REG63
0x56	REG	rx data reg64	mf_rx_data_reg64	RX_DATA_REG64
0x57	REG	rx data reg65	mf_rx_data_reg65	RX_DATA_REG65
0x58	REG	rx data reg66	mf_rx_data_reg66	RX_DATA_REG66
0x59	REG	rx data reg67	mf_rx_data_reg67	RX_DATA_REG67
0x5a	REG	tx ctrl byte	mf_tx_data_ctrl	TX_DATA_CTRL
0x5b	REG	tx data reg1	mf_tx_data_reg1	TX_DATA_REG1
0x5c	REG	tx data reg2	mf_tx_data_reg2	TX_DATA_REG2
0x5d	REG	tx data reg3	mf_tx_data_reg3	TX_DATA_REG3
0x5e	REG	tx data reg4	mf_tx_data_reg4	TX_DATA_REG4
0x5f	REG	tx data reg5	mf_tx_data_reg5	TX_DATA_REG5
0x60	REG	tx data reg6	mf_tx_data_reg6	TX_DATA_REG6
0x61	REG	tx data reg7	mf_tx_data_reg7	TX_DATA_REG7
0x62	REG	tx data reg8	mf_tx_data_reg8	TX_DATA_REG8
0x63	REG	tx data reg9	mf_tx_data_reg9	TX_DATA_REG9
0x64	REG	tx data reg10	mf_tx_data_reg10	TX_DATA_REG10
0x65	REG	tx data reg11	mf_tx_data_reg11	TX_DATA_REG11
0x66	REG	tx data reg12	mf_tx_data_reg12	TX_DATA_REG12
0x67	REG	tx data reg13	mf_tx_data_reg13	TX_DATA_REG13
0x68	REG	tx data reg14	mf_tx_data_reg14	TX_DATA_REG14
0x69	REG	tx data reg15	mf_tx_data_reg15	TX_DATA_REG15
0x6a	REG	tx data reg16	mf_tx_data_reg16	TX_DATA_REG16
0x6b	REG	tx data reg17	mf_tx_data_reg17	TX_DATA_REG17
0x6c	REG	tx data reg18	mf_tx_data_reg18	TX_DATA_REG18
0x6d	REG	tx data reg19	mf_tx_data_reg19	TX_DATA_REG19
0x6e	REG	tx data reg20	mf_tx_data_reg20	TX_DATA_REG20
0x6f	REG	tx data reg21	mf_tx_data_reg21	TX_DATA_REG21
0x70	REG	tx data reg22	mf_tx_data_reg22	TX_DATA_REG22
0x71	REG	tx data reg23	mf_tx_data_reg23	TX_DATA_REG23
0x72	REG	tx data reg24	mf_tx_data_reg24	TX_DATA_REG24
0x73	REG	tx data reg25	mf_tx_data_reg25	TX_DATA_REG25
0x74	REG	tx data reg26	mf_tx_data_reg26	TX_DATA_REG26
0x75	REG	tx data reg27	mf_tx_data_reg27	TX_DATA_REG27
0x76	REG	tx data reg28	mf_tx_data_reg28	TX_DATA_REG28
0x77	REG	tx data reg29	mf_tx_data_reg29	TX_DATA_REG29
0x78	REG	tx data reg30	mf_tx_data_reg30	TX_DATA_REG30
0x79	REG	tx data reg31	mf_tx_data_reg31	TX_DATA_REG31
0x7a	REG	tx data reg32	mf_tx_data_reg32	TX_DATA_REG32
0x7b	REG	tx data reg33	mf_tx_data_reg33	TX_DATA_REG33
0x7c	REG	tx data reg34	mf_tx_data_reg34	TX_DATA_REG34
0x7d	REG	tx data reg35	mf_tx_data_reg35	TX_DATA_REG35
0x7e	REG	tx data reg36	mf_tx_data_reg36	TX_DATA_REG36
0x7f	REG	tx data reg37	mf_tx_data_reg37	TX_DATA_REG37
0x80	REG	tx data reg38	mf_tx_data_reg38	TX_DATA_REG38
0x81	REG	tx data reg39	mf_tx_data_reg39	TX_DATA_REG39
0x82	REG	tx data reg40	mf_tx_data_reg40	TX_DATA_REG40
0x83	REG	tx data reg41	mf_tx_data_reg41	TX_DATA_REG41
0x84	REG	tx data reg42	mf_tx_data_reg42	TX_DATA_REG42
0x85	REG	tx data reg43	mf_tx_data_reg43	TX_DATA_REG43
0x86	REG	tx data reg44	mf_tx_data_reg44	TX_DATA_REG44
0x87	REG	tx data reg45	mf_tx_data_reg45	TX_DATA_REG45
0x88	REG	tx data reg46	mf_tx_data_reg46	TX_DATA_REG46
0x89	REG	tx data reg47	mf_tx_data_reg47	TX_DATA_REG47
0x8a	REG	tx data reg48	mf_tx_data_reg48	TX_DATA_REG48
0x8b	REG	tx data reg49	mf_tx_data_reg49	TX_DATA_REG49
0x8c	REG	tx data reg50	mf_tx_data_reg50	TX_DATA_REG50
0x8d	REG	tx data reg51	mf_tx_data_reg51	TX_DATA_REG51
0x8e	REG	tx data reg52	mf_tx_data_reg52	TX_DATA_REG52
0x8f	REG	tx data reg53	mf_tx_data_reg53	TX_DATA_REG53
0x90	REG	tx data reg54	mf_tx_data_reg54	TX_DATA_REG54
0x91	REG	tx data reg55	mf_tx_data_reg55	TX_DATA_REG55
0x92	REG	tx data reg56	mf_tx_data_reg56	TX_DATA_REG56
0x93	REG	tx data reg57	mf_tx_data_reg57	TX_DATA_REG57
0x94	REG	tx data reg58	mf_tx_data_reg58	TX_DATA_REG58
0x95	REG	tx data reg59	mf_tx_data_reg59	TX_DATA_REG59
0x96	REG	tx data reg60	mf_tx_data_reg60	TX_DATA_REG60
0x97	REG	tx data reg61	mf_tx_data_reg61	TX_DATA_REG61
0x98	REG	tx data reg62	mf_tx_data_reg62	TX_DATA_REG62
0x99	REG	tx data reg63	mf_tx_data_reg63	TX_DATA_REG63
0x9a	REG	tx data reg64	mf_tx_data_reg64	TX_DATA_REG64
0x9b	REG	tx data reg65	mf_tx_data_reg65	TX_DATA_REG65
0x9c	REG	tx data reg66	mf_tx_data_reg66	TX_DATA_REG66
0x9d	REG	tx data reg67	mf_tx_data_reg67	TX_DATA_REG67

2. HDL symbol

→	rst_n_i	rstn:
→	clk_sys_i	mf_rstn_core_o	→
⇒	wb_adr_i[7:0]	mf_rstn_fd_o	→
⇒	wb_dat_i[31:0]	mf_rstn_lock_o[15:0]	⇒
⇐	wb_dat_o[31:0]	mf_rstn_lock_wr_o	→
→	wb_cyc_i
⇒	wb_sel_i[3:0]	id:
→	wb_stb_i
→	wb_we_i	dbg:
←	wb_ack_o	mf_dbg_o[31:0]	⇒
←	wb_stall_o
		adc:
		mf_adc_1v8_shdn_n_o	→
		mf_adc_m5v_shdn_n_o	→
		mf_adc_5v_en_n_o	→
		mf_adc_prim_conn_n_o	→
		mf_adc_sec_conn_n_o	→

		ext sync:
		mf_ext_sync_term_en_o	→
		mf_ext_sync_dir_o	→
		mf_ext_sync_oe_o	→
		mf_ext_sync_tst_n_o	→
		mf_ext_sync_p_cnt_rst_o	→

		ext sync pulses cnt:
		mf_ext_sync_p_cnt_i[31:0]	⇐

		bus speed:
		mf_speed_i[1:0]	⇐

		macrocycle lgth:
		mf_macrocyc_lgth_o[30:0]	⇒
		mf_macrocyc_start_o	→

		turnaround lgth:
		mf_turnar_lgth_o[30:0]	⇒
		mf_turnar_start_o	→

		silence lgth:
		mf_silen_lgth_o[30:0]	⇒
		mf_silen_start_o	→

		macrocycle time cnt:
		mf_macrocyc_time_cnt_i[30:0]	⇐

		macrocycles number cnt:
		mf_macrocyc_num_cnt_i[31:0]	⇐

		turnaround time cnt:
		mf_turnar_time_cnt_i[30:0]	⇐

		silence time cnt:
		mf_silen_time_cnt_i[30:0]	⇐

		tx ctrl:
		mf_tx_ctrl_rst_o	→
		mf_tx_ctrl_start_o	→
		mf_tx_ctrl_bytes_num_o[15:0]	⇒

		tx status:
		mf_tx_stat_stop_i	←
		mf_tx_stat_ena_i	←
		mf_tx_stat_curr_byte_indx_i[15:0]	⇐

		fieldrive wdgn:
		mf_fd_wdgn_tstamp_i[30:0]	⇐
		mf_fd_wdgn_act_i	←

		fieldrive txer cnt:
		mf_fd_txer_cnt_i[31:0]	⇐

		fieldrive txer tstamp:
		mf_fd_txer_tstamp_i[30:0]	⇐

		rx ctrl:
		mf_rx_ctrl_rst_o	→

		rx status:
		mf_rx_stat_pream_ok_i	←
		mf_rx_stat_frame_ok_i	←
		mf_rx_stat_frame_crc_err_i	←
		mf_rx_stat_bytes_num_i[15:0]	⇐

		rx status current byte index:
		mf_rx_stat_curr_byte_indx_i[15:0]	⇐

		rx data ctrl byte:
		mf_rx_data_ctrl_i[7:0]	⇐

		rx data reg1:
		mf_rx_data_reg1_i[31:0]	⇐

		rx data reg2:
		mf_rx_data_reg2_i[31:0]	⇐

		rx data reg3:
		mf_rx_data_reg3_i[31:0]	⇐

		rx data reg4:
		mf_rx_data_reg4_i[31:0]	⇐

		rx data reg5:
		mf_rx_data_reg5_i[31:0]	⇐

		rx data reg6:
		mf_rx_data_reg6_i[31:0]	⇐

		rx data reg7:
		mf_rx_data_reg7_i[31:0]	⇐

		rx data reg8:
		mf_rx_data_reg8_i[31:0]	⇐

		rx data reg9:
		mf_rx_data_reg9_i[31:0]	⇐

		rx data reg10:
		mf_rx_data_reg10_i[31:0]	⇐

		rx data reg11:
		mf_rx_data_reg11_i[31:0]	⇐

		rx data reg12:
		mf_rx_data_reg12_i[31:0]	⇐

		rx data reg13:
		mf_rx_data_reg13_i[31:0]	⇐

		rx data reg14:
		mf_rx_data_reg14_i[31:0]	⇐

		rx data reg15:
		mf_rx_data_reg15_i[31:0]	⇐

		rx data reg16:
		mf_rx_data_reg16_i[31:0]	⇐

		rx data reg17:
		mf_rx_data_reg17_i[31:0]	⇐

		rx data reg18:
		mf_rx_data_reg18_i[31:0]	⇐

		rx data reg19:
		mf_rx_data_reg19_i[31:0]	⇐

		rx data reg20:
		mf_rx_data_reg20_i[31:0]	⇐

		rx data reg21:
		mf_rx_data_reg21_i[31:0]	⇐

		rx data reg22:
		mf_rx_data_reg22_i[31:0]	⇐

		rx data reg23:
		mf_rx_data_reg23_i[31:0]	⇐

		rx data reg24:
		mf_rx_data_reg24_i[31:0]	⇐

		rx data reg25:
		mf_rx_data_reg25_i[31:0]	⇐

		rx data reg26:
		mf_rx_data_reg26_i[31:0]	⇐

		rx data reg27:
		mf_rx_data_reg27_i[31:0]	⇐

		rx data reg28:
		mf_rx_data_reg28_i[31:0]	⇐

		rx data reg29:
		mf_rx_data_reg29_i[31:0]	⇐

		rx data reg30:
		mf_rx_data_reg30_i[31:0]	⇐

		rx data reg31:
		mf_rx_data_reg31_i[31:0]	⇐

		rx data reg32:
		mf_rx_data_reg32_i[31:0]	⇐

		rx data reg33:
		mf_rx_data_reg33_i[31:0]	⇐

		rx data reg34:
		mf_rx_data_reg34_i[31:0]	⇐

		rx data reg35:
		mf_rx_data_reg35_i[31:0]	⇐

		rx data reg36:
		mf_rx_data_reg36_i[31:0]	⇐

		rx data reg37:
		mf_rx_data_reg37_i[31:0]	⇐

		rx data reg38:
		mf_rx_data_reg38_i[31:0]	⇐

		rx data reg39:
		mf_rx_data_reg39_i[31:0]	⇐

		rx data reg40:
		mf_rx_data_reg40_i[31:0]	⇐

		rx data reg41:
		mf_rx_data_reg41_i[31:0]	⇐

		rx data reg42:
		mf_rx_data_reg42_i[31:0]	⇐

		rx data reg43:
		mf_rx_data_reg43_i[31:0]	⇐

		rx data reg44:
		mf_rx_data_reg44_i[31:0]	⇐

		rx data reg45:
		mf_rx_data_reg45_i[31:0]	⇐

		rx data reg46:
		mf_rx_data_reg46_i[31:0]	⇐

		rx data reg47:
		mf_rx_data_reg47_i[31:0]	⇐

		rx data reg48:
		mf_rx_data_reg48_i[31:0]	⇐

		rx data reg49:
		mf_rx_data_reg49_i[31:0]	⇐

		rx data reg50:
		mf_rx_data_reg50_i[31:0]	⇐

		rx data reg51:
		mf_rx_data_reg51_i[31:0]	⇐

		rx data reg52:
		mf_rx_data_reg52_i[31:0]	⇐

		rx data reg53:
		mf_rx_data_reg53_i[31:0]	⇐

		rx data reg54:
		mf_rx_data_reg54_i[31:0]	⇐

		rx data reg55:
		mf_rx_data_reg55_i[31:0]	⇐

		rx data reg56:
		mf_rx_data_reg56_i[31:0]	⇐

		rx data reg57:
		mf_rx_data_reg57_i[31:0]	⇐

		rx data reg58:
		mf_rx_data_reg58_i[31:0]	⇐

		rx data reg59:
		mf_rx_data_reg59_i[31:0]	⇐

		rx data reg60:
		mf_rx_data_reg60_i[31:0]	⇐

		rx data reg61:
		mf_rx_data_reg61_i[31:0]	⇐

		rx data reg62:
		mf_rx_data_reg62_i[31:0]	⇐

		rx data reg63:
		mf_rx_data_reg63_i[31:0]	⇐

		rx data reg64:
		mf_rx_data_reg64_i[31:0]	⇐

		rx data reg65:
		mf_rx_data_reg65_i[31:0]	⇐

		rx data reg66:
		mf_rx_data_reg66_i[31:0]	⇐

		rx data reg67:
		mf_rx_data_reg67_i[31:0]	⇐

		tx ctrl byte:
		mf_tx_data_ctrl_o[7:0]	⇒

		tx data reg1:
		mf_tx_data_reg1_o[31:0]	⇒

		tx data reg2:
		mf_tx_data_reg2_o[31:0]	⇒

		tx data reg3:
		mf_tx_data_reg3_o[31:0]	⇒

		tx data reg4:
		mf_tx_data_reg4_o[31:0]	⇒

		tx data reg5:
		mf_tx_data_reg5_o[31:0]	⇒

		tx data reg6:
		mf_tx_data_reg6_o[31:0]	⇒

		tx data reg7:
		mf_tx_data_reg7_o[31:0]	⇒

		tx data reg8:
		mf_tx_data_reg8_o[31:0]	⇒

		tx data reg9:
		mf_tx_data_reg9_o[31:0]	⇒

		tx data reg10:
		mf_tx_data_reg10_o[31:0]	⇒

		tx data reg11:
		mf_tx_data_reg11_o[31:0]	⇒

		tx data reg12:
		mf_tx_data_reg12_o[31:0]	⇒

		tx data reg13:
		mf_tx_data_reg13_o[31:0]	⇒

		tx data reg14:
		mf_tx_data_reg14_o[31:0]	⇒

		tx data reg15:
		mf_tx_data_reg15_o[31:0]	⇒

		tx data reg16:
		mf_tx_data_reg16_o[31:0]	⇒

		tx data reg17:
		mf_tx_data_reg17_o[31:0]	⇒

		tx data reg18:
		mf_tx_data_reg18_o[31:0]	⇒

		tx data reg19:
		mf_tx_data_reg19_o[31:0]	⇒

		tx data reg20:
		mf_tx_data_reg20_o[31:0]	⇒

		tx data reg21:
		mf_tx_data_reg21_o[31:0]	⇒

		tx data reg22:
		mf_tx_data_reg22_o[31:0]	⇒

		tx data reg23:
		mf_tx_data_reg23_o[31:0]	⇒

		tx data reg24:
		mf_tx_data_reg24_o[31:0]	⇒

		tx data reg25:
		mf_tx_data_reg25_o[31:0]	⇒

		tx data reg26:
		mf_tx_data_reg26_o[31:0]	⇒

		tx data reg27:
		mf_tx_data_reg27_o[31:0]	⇒

		tx data reg28:
		mf_tx_data_reg28_o[31:0]	⇒

		tx data reg29:
		mf_tx_data_reg29_o[31:0]	⇒

		tx data reg30:
		mf_tx_data_reg30_o[31:0]	⇒

		tx data reg31:
		mf_tx_data_reg31_o[31:0]	⇒

		tx data reg32:
		mf_tx_data_reg32_o[31:0]	⇒

		tx data reg33:
		mf_tx_data_reg33_o[31:0]	⇒

		tx data reg34:
		mf_tx_data_reg34_o[31:0]	⇒

		tx data reg35:
		mf_tx_data_reg35_o[31:0]	⇒

		tx data reg36:
		mf_tx_data_reg36_o[31:0]	⇒

		tx data reg37:
		mf_tx_data_reg37_o[31:0]	⇒

		tx data reg38:
		mf_tx_data_reg38_o[31:0]	⇒

		tx data reg39:
		mf_tx_data_reg39_o[31:0]	⇒

		tx data reg40:
		mf_tx_data_reg40_o[31:0]	⇒

		tx data reg41:
		mf_tx_data_reg41_o[31:0]	⇒

		tx data reg42:
		mf_tx_data_reg42_o[31:0]	⇒

		tx data reg43:
		mf_tx_data_reg43_o[31:0]	⇒

		tx data reg44:
		mf_tx_data_reg44_o[31:0]	⇒

		tx data reg45:
		mf_tx_data_reg45_o[31:0]	⇒

		tx data reg46:
		mf_tx_data_reg46_o[31:0]	⇒

		tx data reg47:
		mf_tx_data_reg47_o[31:0]	⇒

		tx data reg48:
		mf_tx_data_reg48_o[31:0]	⇒

		tx data reg49:
		mf_tx_data_reg49_o[31:0]	⇒

		tx data reg50:
		mf_tx_data_reg50_o[31:0]	⇒

		tx data reg51:
		mf_tx_data_reg51_o[31:0]	⇒

		tx data reg52:
		mf_tx_data_reg52_o[31:0]	⇒

		tx data reg53:
		mf_tx_data_reg53_o[31:0]	⇒

		tx data reg54:
		mf_tx_data_reg54_o[31:0]	⇒

		tx data reg55:
		mf_tx_data_reg55_o[31:0]	⇒

		tx data reg56:
		mf_tx_data_reg56_o[31:0]	⇒

		tx data reg57:
		mf_tx_data_reg57_o[31:0]	⇒

		tx data reg58:
		mf_tx_data_reg58_o[31:0]	⇒

		tx data reg59:
		mf_tx_data_reg59_o[31:0]	⇒

		tx data reg60:
		mf_tx_data_reg60_o[31:0]	⇒

		tx data reg61:
		mf_tx_data_reg61_o[31:0]	⇒

		tx data reg62:
		mf_tx_data_reg62_o[31:0]	⇒

		tx data reg63:
		mf_tx_data_reg63_o[31:0]	⇒

		tx data reg64:
		mf_tx_data_reg64_o[31:0]	⇒

		tx data reg65:
		mf_tx_data_reg65_o[31:0]	⇒

		tx data reg66:
		mf_tx_data_reg66_o[31:0]	⇒

		tx data reg67:
		mf_tx_data_reg67_o[31:0]	⇒

3. Register description

3.1. rstn

HW prefix:	mf_rstn
HW address:	0x0
C prefix:	RSTN
C offset:	0x0

software reset of the masterFIP core; active low; there is also an unlock word provided to prevent resetting the core by accidentally accessing this register.

31	30	29	28	27	26	25	24
LOCK[15:8]

23	22	21	20	19	18	17	16
LOCK[7:0]

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	-	-	-	-	-	FD	CORE

CORE [read/write]: reset of the masterFIP core
write 0: masterFIP core is held in reset
write 1: normal core operation
FD [read/write]: reset of the fieldrive chip (FD_RSTN)
write 0: fieldrive is held in reset
write 1: normal fieldrive operation
LOCK [write-only]: reset magic value
Protection field - the state of the rst line will
only be updated if lock is written with 0xcafe together with the new state of the reset line.

3.2. id

HW prefix:	mf_id
HW address:	0x1
C prefix:	ID
C offset:	0x4

constant identification value: COOOFFEE

31	30	29	28	27	26	25	24
ID[31:24]

23	22	21	20	19	18	17	16
ID[23:16]

15	14	13	12	11	10	9	8
ID[15:8]

7	6	5	4	3	2	1	0
ID[7:0]

ID [read-only]: an id value
equal to 0xc000ffee for the moment

3.3. dbg

HW prefix:	mf_dbg
HW address:	0x2
C prefix:	DBG
C offset:	0x8

for debugging purposes; used to pass signals to front panel LEDs

31	30	29	28	27	26	25	24
DBG[31:24]

23	22	21	20	19	18	17	16
DBG[23:16]

15	14	13	12	11	10	9	8
DBG[15:8]

7	6	5	4	3	2	1	0
DBG[7:0]

DBG [read/write]: debugging

3.4. adc

HW prefix:	mf_adc
HW address:	0x3
C prefix:	ADC
C offset:	0xc

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	SEC_CONN_N	PRIM_CONN_N

7	6	5	4	3	2	1	0
-	-	-	-	-	5V_EN_N	M5V_SHDN_N	1V8_SHDN_N

1V8_SHDN_N [read/write]: 1v8_shdn_n
write 0: disable the ADC 1V8
write 1: enable the ADC 1V8
M5V_SHDN_N [read/write]: m5v_shdn_n
write 0: disable the ADC M5V
write 1: enable the ADC M5V
5V_EN_N [read/write]: 5v_en_n
write 0: enable the ADC 5V
write 1: disable the ADC 5V
PRIM_CONN_N [read/write]: prim_conn_n
write 0: connect the ADC to the primary side of the FieldTR (bus side)
write 1: disconnect the ADC from the primary side of the FieldTR (bus side)
SEC_CONN_N [read/write]: sec_conn_n
write 0: connect the ADC to the secondary side of the FieldTR (FielDrive side)
write 1: disconnect the ADC from the secondary side of the FieldTR (FielDrive side)

3.5. ext sync

HW prefix:	mf_ext_sync
HW address:	0x4
C prefix:	EXT_SYNC
C offset:	0x10

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	P_CNT_RST

7	6	5	4	3	2	1	0
-	-	-	-	TST_N	OE	DIR	TERM_EN

TERM_EN [read/write]: termination enable
write 0: disable 50ohms termination of the external sync pulse
write 1: enable 50ohms termination of the external sync pulse
DIR [read/write]: transceiver direction
write 0: normal operation
write 1: test mode where a pulse from the FPGA can be output to the front panel LEMO connector
OE [read/write]: transceiver output enable
write 0: normal operation, the external sync pulse arrives to the FPGA
write 1: the external sync pulse does not arrive to the FPGA
TST_N [read/write]: test pulse
emulate a pulse
P_CNT_RST [read/write]: pulses counter reset
resets the pulses counter

3.6. ext sync pulses cnt

HW prefix:	mf_ext_sync_p_cnt
HW address:	0x5
C prefix:	EXT_SYNC_P_CNT
C offset:	0x14

31	30	29	28	27	26	25	24
EXT_SYNC_P_CNT[31:24]

23	22	21	20	19	18	17	16
EXT_SYNC_P_CNT[23:16]

15	14	13	12	11	10	9	8
EXT_SYNC_P_CNT[15:8]

7	6	5	4	3	2	1	0
EXT_SYNC_P_CNT[7:0]

EXT_SYNC_P_CNT [read-only]: ext_sync_p_cnt
number of ext sync pulses

3.7. bus speed

HW prefix:	mf_speed
HW address:	0x6
C prefix:	SPEED
C offset:	0x18

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	-	-	-	-	-	SPEED[1:0]

SPEED [read-only]: speed
WorldFIP speed: 00: 31.25Kbps
01: 1Mbps
10: 2.5 Mbps
11: 5 Mbps

3.8. macrocycle lgth

HW prefix:	mf_macrocyc
HW address:	0x7
C prefix:	MACROCYC
C offset:	0x1c

31	30	29	28	27	26	25	24
START	LGTH[30:24]

23	22	21	20	19	18	17	16
LGTH[23:16]

15	14	13	12	11	10	9	8
LGTH[15:8]

7	6	5	4	3	2	1	0
LGTH[7:0]

LGTH [read/write]: macrocycle lgth
duration of the macrocycle in number of 10ns-clk-ticks
START [read/write]: macrocycle cnt start
initiates the counting of the macrocycle counter

3.9. turnaround lgth

HW prefix:	mf_turnar
HW address:	0x8
C prefix:	TURNAR
C offset:	0x20

31	30	29	28	27	26	25	24
START	LGTH[30:24]

23	22	21	20	19	18	17	16
LGTH[23:16]

15	14	13	12	11	10	9	8
LGTH[15:8]

7	6	5	4	3	2	1	0
LGTH[7:0]

LGTH [read/write]: turnaround time
turnaround time (i.e. time between two frames sent by the masterFIP) in number of 10ns-clk-ticks
START [read/write]: turnaround cnt start
initiates the counting of the turnaround counter

3.10. silence lgth

HW prefix:	mf_silen
HW address:	0x9
C prefix:	SILEN
C offset:	0x24

31	30	29	28	27	26	25	24
START	LGTH[30:24]

23	22	21	20	19	18	17	16
LGTH[23:16]

15	14	13	12	11	10	9	8
LGTH[15:8]

7	6	5	4	3	2	1	0
LGTH[7:0]

LGTH [read/write]: silence time
silence time (i.e. time that the masterFIP waits for a response frame) number of 10ns-clk-ticks
START [read/write]: silence cnt start
initiates the counting of the silence counter

3.11. macrocycle time cnt

HW prefix:	mf_macrocyc_time_cnt
HW address:	0xa
C prefix:	MACROCYC_TIME_CNT
C offset:	0x28

31	30	29	28	27	26	25	24
-	MACROCYC_TIME_CNT[30:24]

23	22	21	20	19	18	17	16
MACROCYC_TIME_CNT[23:16]

15	14	13	12	11	10	9	8
MACROCYC_TIME_CNT[15:8]

7	6	5	4	3	2	1	0
MACROCYC_TIME_CNT[7:0]

MACROCYC_TIME_CNT [read-only]: macrocycle time counter
current value of the macrocycle time counter

3.12. macrocycles number cnt

HW prefix:	mf_macrocyc_num_cnt
HW address:	0xb
C prefix:	MACROCYC_NUM_CNT
C offset:	0x2c

31	30	29	28	27	26	25	24
MACROCYC_NUM_CNT[31:24]

23	22	21	20	19	18	17	16
MACROCYC_NUM_CNT[23:16]

15	14	13	12	11	10	9	8
MACROCYC_NUM_CNT[15:8]

7	6	5	4	3	2	1	0
MACROCYC_NUM_CNT[7:0]

MACROCYC_NUM_CNT [read-only]: number of macrocycles
amount of macrocycles that have been counted so far

3.13. turnaround time cnt

HW prefix:	mf_turnar_time_cnt
HW address:	0xc
C prefix:	TURNAR_TIME_CNT
C offset:	0x30

31	30	29	28	27	26	25	24
-	TURNAR_TIME_CNT[30:24]

23	22	21	20	19	18	17	16
TURNAR_TIME_CNT[23:16]

15	14	13	12	11	10	9	8
TURNAR_TIME_CNT[15:8]

7	6	5	4	3	2	1	0
TURNAR_TIME_CNT[7:0]

TURNAR_TIME_CNT [read-only]: turnaround time counter
current value of the turnaround time counter

3.14. silence time cnt

HW prefix:	mf_silen_time_cnt
HW address:	0xd
C prefix:	SILEN_TIME_CNT
C offset:	0x34

31	30	29	28	27	26	25	24
-	SILEN_TIME_CNT[30:24]

23	22	21	20	19	18	17	16
SILEN_TIME_CNT[23:16]

15	14	13	12	11	10	9	8
SILEN_TIME_CNT[15:8]

7	6	5	4	3	2	1	0
SILEN_TIME_CNT[7:0]

SILEN_TIME_CNT [read-only]: silence time counter
current value of the silence time counter

3.15. tx ctrl

HW prefix:	mf_tx_ctrl
HW address:	0xe
C prefix:	TX_CTRL
C offset:	0x38

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
BYTES_NUM[15:8]

15	14	13	12	11	10	9	8
BYTES_NUM[7:0]

7	6	5	4	3	2	1	0
-	-	-	-	-	-	START	RST

RST [read/write]: tx rst
write 0: normal serializer operation
write 1: serializer is held in reset
START [read/write]: tx strt
initiates the serializer to send a frame
BYTES_NUM [read/write]: tx number of bytes
number of bytes to serialize; the masterFIP_core samples this upon the tx_strt;
note that the max WorldFIP frame size = 263 bytes (without preamble, CRC, postamble)

3.16. tx status

HW prefix:	mf_tx_stat
HW address:	0xf
C prefix:	TX_STAT
C offset:	0x3c

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	CURR_BYTE_INDX[15:15]

23	22	21	20	19	18	17	16
CURR_BYTE_INDX[14:7]

15	14	13	12	11	10	9	8
CURR_BYTE_INDX[6:0]							ENA

7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	STOP

STOP [read-only]: tx ended
indication that the serializer finished the delivery of a frame
the bit stays active until a rstn_core or a tx_ctrl_rst or a tx_ctrl_strt
ENA [read-only]: tx enable
fieldrive fd_txena signal;
read 0: masterFIP serializer is inactive
read 1: masterFIP serializer is active putting bits to the bus
CURR_BYTE_INDX [read-only]: tx status current byte index
index of the current byte being serialized;
the counting starts from 0 after the preamble...

3.17. fieldrive wdgn

HW prefix:	mf_fd_wdgn
HW address:	0x10
C prefix:	FD_WDGN
C offset:	0x40

31	30	29	28	27	26	25	24
ACT	TSTAMP[30:24]

23	22	21	20	19	18	17	16
TSTAMP[23:16]

15	14	13	12	11	10	9	8
TSTAMP[15:8]

7	6	5	4	3	2	1	0
TSTAMP[7:0]

TSTAMP [read-only]: fd_wdgn_tstamp
timestamp of the moment in the macrocycle when the fd_wdgn
was activated.
The field is automatically cleared upon a new macrocycle or
upon a rstn_fd or rstn_core
ACT [read-only]: fd_wdg_act
read 1: the fd_wdgn has been activated
read 0: no problemo
Note that if triggered, the fd_wdgn stays active until a fd_rstn

3.18. fieldrive txer cnt

HW prefix:	mf_fd_txer_cnt
HW address:	0x11
C prefix:	FD_TXER_CNT
C offset:	0x44

31	30	29	28	27	26	25	24
FD_TXER_CNT[31:24]

23	22	21	20	19	18	17	16
FD_TXER_CNT[23:16]

15	14	13	12	11	10	9	8
FD_TXER_CNT[15:8]

7	6	5	4	3	2	1	0
FD_TXER_CNT[7:0]

FD_TXER_CNT [read-only]: fd_txer_cnt
counter of the number of fd_txer rising edges that appear in this
current macrocycle.
The field is automatically cleared upon a new macrocycle or
upon a rstn_fd or rstn_core

3.19. fieldrive txer tstamp

HW prefix:	mf_fd_txer_tstamp
HW address:	0x12
C prefix:	FD_TXER_TSTAMP
C offset:	0x48

31	30	29	28	27	26	25	24
-	FD_TXER_TSTAMP[30:24]

23	22	21	20	19	18	17	16
FD_TXER_TSTAMP[23:16]

15	14	13	12	11	10	9	8
FD_TXER_TSTAMP[15:8]

7	6	5	4	3	2	1	0
FD_TXER_TSTAMP[7:0]

FD_TXER_TSTAMP [read-only]: fd_txer_tstamp
timestamp of the last moment in the macrocycle when the fd_txer
was activated.
The field is automatically cleared upon a new macrocycle or
upon a rstn_fd or rstn_core

3.20. rx ctrl

HW prefix:	mf_rx_ctrl
HW address:	0x13
C prefix:	RX_CTRL
C offset:	0x4c

active high reset of the deserializer

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
-	-	-	-	-	-	-	RST

RST [read/write]: rx rst
write 0: normal deserializer operation
write 1: deserializer is held in reset
note that the deserialiser is automatically hw reset when the serializer is active

3.21. rx status

HW prefix:	mf_rx_stat
HW address:	0x14
C prefix:	RX_STAT
C offset:	0x50

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
BYTES_NUM[15:8]

15	14	13	12	11	10	9	8
BYTES_NUM[7:0]

7	6	5	4	3	2	1	0
-	-	-	-	-	FRAME_CRC_ERR	FRAME_OK	PREAM_OK

PREAM_OK [read-only]: rx preamble detected
indication that the deserializer has detected a preamble;
the bit stays active until a reset of the deserializer (this takes place
automatically upon the activation of the serializer, or upon a rx_ctrl_rst
or upon a core_rstn)
FRAME_OK [read-only]: rx frame ok
indication that the deserializer has finished with the reception of a complete frame;
the preamble, CRC and postambe of the frame are all ok
the bit stays high until a reset of the deserializer (this takes place
automatically upon the activation of the serializer, or upon a rx_ctrl_rst
or upon a rstn_core)
FRAME_CRC_ERR [read-only]: rx frame crc error
indication that the deserializer has detected a frame with CRC error
the bit stays high until a reset of the deserializer (this takes place
automatically upon the activation of the serializer, or upon a rx_rst)
BYTES_NUM [read-only]: rx number of data bytes
number of bytes that have been received by the deserializer upon the rx_frame_ok activation
note that the max WorldFIP frame size = 263 bytes (without preamble, CRC, postamble)

3.22. rx status current byte index

HW prefix:	mf_rx_stat_curr_byte_indx
HW address:	0x15
C prefix:	RX_STAT_CURR_BYTE_INDX
C offset:	0x54

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
RX_STAT_CURR_BYTE_INDX[15:8]

7	6	5	4	3	2	1	0
RX_STAT_CURR_BYTE_INDX[7:0]

RX_STAT_CURR_BYTE_INDX [read-only]: current byte index
index of the current byte being deserialized;
the counting starts from 0 after the preamble and
it also includes the CRC and postamble bytes

3.23. rx data ctrl byte

HW prefix:	mf_rx_data_ctrl
HW address:	0x16
C prefix:	RX_DATA_CTRL
C offset:	0x58

contains the 8-bits of the control field of a received frame

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
RX_DATA_CTRL[7:0]

RX_DATA_CTRL [read-only]: rx data ctrl byte
contains the 8-bits of the control field of a received frame

3.24. rx data reg1

HW prefix:	mf_rx_data_reg1
HW address:	0x17
C prefix:	RX_DATA_REG1
C offset:	0x5c

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG1[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG1[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG1[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG1[7:0]

RX_DATA_REG1 [read-only]: reg 1
1st 32-bit word

3.25. rx data reg2

HW prefix:	mf_rx_data_reg2
HW address:	0x18
C prefix:	RX_DATA_REG2
C offset:	0x60

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG2[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG2[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG2[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG2[7:0]

RX_DATA_REG2 [read-only]: reg2
2nd 32-bit word

3.26. rx data reg3

HW prefix:	mf_rx_data_reg3
HW address:	0x19
C prefix:	RX_DATA_REG3
C offset:	0x64

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG3[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG3[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG3[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG3[7:0]

RX_DATA_REG3 [read-only]: reg3
3rd 32-bit word

3.27. rx data reg4

HW prefix:	mf_rx_data_reg4
HW address:	0x1a
C prefix:	RX_DATA_REG4
C offset:	0x68

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG4[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG4[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG4[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG4[7:0]

RX_DATA_REG4 [read-only]: reg4
4th 32-bit word

3.28. rx data reg5

HW prefix:	mf_rx_data_reg5
HW address:	0x1b
C prefix:	RX_DATA_REG5
C offset:	0x6c

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG5[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG5[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG5[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG5[7:0]

RX_DATA_REG5 [read-only]: reg5
5th 32-bit word

3.29. rx data reg6

HW prefix:	mf_rx_data_reg6
HW address:	0x1c
C prefix:	RX_DATA_REG6
C offset:	0x70

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG6[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG6[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG6[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG6[7:0]

RX_DATA_REG6 [read-only]: reg6
6th 32-bit word

3.30. rx data reg7

HW prefix:	mf_rx_data_reg7
HW address:	0x1d
C prefix:	RX_DATA_REG7
C offset:	0x74

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG7[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG7[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG7[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG7[7:0]

RX_DATA_REG7 [read-only]: reg7
7th 32-bit word

3.31. rx data reg8

HW prefix:	mf_rx_data_reg8
HW address:	0x1e
C prefix:	RX_DATA_REG8
C offset:	0x78

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG8[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG8[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG8[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG8[7:0]

RX_DATA_REG8 [read-only]: reg8
8th 32-bit word

3.32. rx data reg9

HW prefix:	mf_rx_data_reg9
HW address:	0x1f
C prefix:	RX_DATA_REG9
C offset:	0x7c

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG9[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG9[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG9[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG9[7:0]

RX_DATA_REG9 [read-only]: reg9
9th 32-bit word

3.33. rx data reg10

HW prefix:	mf_rx_data_reg10
HW address:	0x20
C prefix:	RX_DATA_REG10
C offset:	0x80

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG10[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG10[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG10[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG10[7:0]

RX_DATA_REG10 [read-only]: reg10
10th 32-bit word

3.34. rx data reg11

HW prefix:	mf_rx_data_reg11
HW address:	0x21
C prefix:	RX_DATA_REG11
C offset:	0x84

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG11[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG11[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG11[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG11[7:0]

RX_DATA_REG11 [read-only]: reg11
11th 32-bit word

3.35. rx data reg12

HW prefix:	mf_rx_data_reg12
HW address:	0x22
C prefix:	RX_DATA_REG12
C offset:	0x88

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG12[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG12[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG12[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG12[7:0]

RX_DATA_REG12 [read-only]: reg12
12th 32-bit word

3.36. rx data reg13

HW prefix:	mf_rx_data_reg13
HW address:	0x23
C prefix:	RX_DATA_REG13
C offset:	0x8c

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG13[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG13[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG13[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG13[7:0]

RX_DATA_REG13 [read-only]: reg13
13th 32-bit word

3.37. rx data reg14

HW prefix:	mf_rx_data_reg14
HW address:	0x24
C prefix:	RX_DATA_REG14
C offset:	0x90

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG14[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG14[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG14[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG14[7:0]

RX_DATA_REG14 [read-only]: reg14
14th 32-bit word

3.38. rx data reg15

HW prefix:	mf_rx_data_reg15
HW address:	0x25
C prefix:	RX_DATA_REG15
C offset:	0x94

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG15[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG15[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG15[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG15[7:0]

RX_DATA_REG15 [read-only]: reg15
15th 32-bit word

3.39. rx data reg16

HW prefix:	mf_rx_data_reg16
HW address:	0x26
C prefix:	RX_DATA_REG16
C offset:	0x98

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG16[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG16[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG16[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG16[7:0]

RX_DATA_REG16 [read-only]: reg16
16th 32-bit word

3.40. rx data reg17

HW prefix:	mf_rx_data_reg17
HW address:	0x27
C prefix:	RX_DATA_REG17
C offset:	0x9c

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG17[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG17[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG17[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG17[7:0]

RX_DATA_REG17 [read-only]: reg17
17th 32-bit word

3.41. rx data reg18

HW prefix:	mf_rx_data_reg18
HW address:	0x28
C prefix:	RX_DATA_REG18
C offset:	0xa0

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG18[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG18[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG18[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG18[7:0]

RX_DATA_REG18 [read-only]: reg18
18th 32-bit word

3.42. rx data reg19

HW prefix:	mf_rx_data_reg19
HW address:	0x29
C prefix:	RX_DATA_REG19
C offset:	0xa4

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG19[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG19[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG19[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG19[7:0]

RX_DATA_REG19 [read-only]: reg19
19th 32-bit word

3.43. rx data reg20

HW prefix:	mf_rx_data_reg20
HW address:	0x2a
C prefix:	RX_DATA_REG20
C offset:	0xa8

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG20[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG20[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG20[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG20[7:0]

RX_DATA_REG20 [read-only]: reg20
20th 32-bit word

3.44. rx data reg21

HW prefix:	mf_rx_data_reg21
HW address:	0x2b
C prefix:	RX_DATA_REG21
C offset:	0xac

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG21[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG21[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG21[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG21[7:0]

RX_DATA_REG21 [read-only]: reg21
21th 32-bit word

3.45. rx data reg22

HW prefix:	mf_rx_data_reg22
HW address:	0x2c
C prefix:	RX_DATA_REG22
C offset:	0xb0

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG22[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG22[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG22[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG22[7:0]

RX_DATA_REG22 [read-only]: reg22
22th 32-bit word

3.46. rx data reg23

HW prefix:	mf_rx_data_reg23
HW address:	0x2d
C prefix:	RX_DATA_REG23
C offset:	0xb4

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG23[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG23[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG23[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG23[7:0]

RX_DATA_REG23 [read-only]: reg23
23th 32-bit word

3.47. rx data reg24

HW prefix:	mf_rx_data_reg24
HW address:	0x2e
C prefix:	RX_DATA_REG24
C offset:	0xb8

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG24[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG24[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG24[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG24[7:0]

RX_DATA_REG24 [read-only]: reg24
24th 32-bit word

3.48. rx data reg25

HW prefix:	mf_rx_data_reg25
HW address:	0x2f
C prefix:	RX_DATA_REG25
C offset:	0xbc

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG25[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG25[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG25[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG25[7:0]

RX_DATA_REG25 [read-only]: reg25
25th 32-bit word

3.49. rx data reg26

HW prefix:	mf_rx_data_reg26
HW address:	0x30
C prefix:	RX_DATA_REG26
C offset:	0xc0

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG26[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG26[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG26[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG26[7:0]

RX_DATA_REG26 [read-only]: reg26
26th 32-bit word

3.50. rx data reg27

HW prefix:	mf_rx_data_reg27
HW address:	0x31
C prefix:	RX_DATA_REG27
C offset:	0xc4

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG27[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG27[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG27[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG27[7:0]

RX_DATA_REG27 [read-only]: reg27
27th 32-bit word

3.51. rx data reg28

HW prefix:	mf_rx_data_reg28
HW address:	0x32
C prefix:	RX_DATA_REG28
C offset:	0xc8

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG28[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG28[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG28[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG28[7:0]

RX_DATA_REG28 [read-only]: reg28
28th 32-bit word

3.52. rx data reg29

HW prefix:	mf_rx_data_reg29
HW address:	0x33
C prefix:	RX_DATA_REG29
C offset:	0xcc

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG29[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG29[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG29[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG29[7:0]

RX_DATA_REG29 [read-only]: reg29
29th 32-bit word

3.53. rx data reg30

HW prefix:	mf_rx_data_reg30
HW address:	0x34
C prefix:	RX_DATA_REG30
C offset:	0xd0

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG30[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG30[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG30[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG30[7:0]

RX_DATA_REG30 [read-only]: reg30
30th 32-bit word

3.54. rx data reg31

HW prefix:	mf_rx_data_reg31
HW address:	0x35
C prefix:	RX_DATA_REG31
C offset:	0xd4

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG31[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG31[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG31[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG31[7:0]

RX_DATA_REG31 [read-only]: reg31
31th 32-bit word

3.55. rx data reg32

HW prefix:	mf_rx_data_reg32
HW address:	0x36
C prefix:	RX_DATA_REG32
C offset:	0xd8

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG32[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG32[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG32[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG32[7:0]

RX_DATA_REG32 [read-only]: reg32
32th 32-bit word

3.56. rx data reg33

HW prefix:	mf_rx_data_reg33
HW address:	0x37
C prefix:	RX_DATA_REG33
C offset:	0xdc

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG33[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG33[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG33[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG33[7:0]

RX_DATA_REG33 [read-only]: reg 33
33rd 32-bit word

3.57. rx data reg34

HW prefix:	mf_rx_data_reg34
HW address:	0x38
C prefix:	RX_DATA_REG34
C offset:	0xe0

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG34[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG34[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG34[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG34[7:0]

RX_DATA_REG34 [read-only]: reg34
34th 32-bit word

3.58. rx data reg35

HW prefix:	mf_rx_data_reg35
HW address:	0x39
C prefix:	RX_DATA_REG35
C offset:	0xe4

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG35[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG35[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG35[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG35[7:0]

RX_DATA_REG35 [read-only]: reg35
35th 32-bit word

3.59. rx data reg36

HW prefix:	mf_rx_data_reg36
HW address:	0x3a
C prefix:	RX_DATA_REG36
C offset:	0xe8

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG36[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG36[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG36[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG36[7:0]

RX_DATA_REG36 [read-only]: reg36
36th 32-bit word

3.60. rx data reg37

HW prefix:	mf_rx_data_reg37
HW address:	0x3b
C prefix:	RX_DATA_REG37
C offset:	0xec

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG37[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG37[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG37[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG37[7:0]

RX_DATA_REG37 [read-only]: reg37
37th 32-bit word

3.61. rx data reg38

HW prefix:	mf_rx_data_reg38
HW address:	0x3c
C prefix:	RX_DATA_REG38
C offset:	0xf0

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG38[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG38[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG38[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG38[7:0]

RX_DATA_REG38 [read-only]: reg38
38th 32-bit word

3.62. rx data reg39

HW prefix:	mf_rx_data_reg39
HW address:	0x3d
C prefix:	RX_DATA_REG39
C offset:	0xf4

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG39[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG39[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG39[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG39[7:0]

RX_DATA_REG39 [read-only]: reg39
39th 32-bit word

3.63. rx data reg40

HW prefix:	mf_rx_data_reg40
HW address:	0x3e
C prefix:	RX_DATA_REG40
C offset:	0xf8

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG40[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG40[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG40[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG40[7:0]

RX_DATA_REG40 [read-only]: reg40
40th 32-bit word

3.64. rx data reg41

HW prefix:	mf_rx_data_reg41
HW address:	0x3f
C prefix:	RX_DATA_REG41
C offset:	0xfc

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG41[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG41[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG41[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG41[7:0]

RX_DATA_REG41 [read-only]: reg41
41th 32-bit word

3.65. rx data reg42

HW prefix:	mf_rx_data_reg42
HW address:	0x40
C prefix:	RX_DATA_REG42
C offset:	0x100

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG42[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG42[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG42[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG42[7:0]

RX_DATA_REG42 [read-only]: reg42
42nd 32-bit word

3.66. rx data reg43

HW prefix:	mf_rx_data_reg43
HW address:	0x41
C prefix:	RX_DATA_REG43
C offset:	0x104

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG43[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG43[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG43[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG43[7:0]

RX_DATA_REG43 [read-only]: reg43
43rd 32-bit word

3.67. rx data reg44

HW prefix:	mf_rx_data_reg44
HW address:	0x42
C prefix:	RX_DATA_REG44
C offset:	0x108

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG44[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG44[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG44[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG44[7:0]

RX_DATA_REG44 [read-only]: reg44
44th 32-bit word

3.68. rx data reg45

HW prefix:	mf_rx_data_reg45
HW address:	0x43
C prefix:	RX_DATA_REG45
C offset:	0x10c

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG45[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG45[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG45[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG45[7:0]

RX_DATA_REG45 [read-only]: reg45
45th 32-bit word

3.69. rx data reg46

HW prefix:	mf_rx_data_reg46
HW address:	0x44
C prefix:	RX_DATA_REG46
C offset:	0x110

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG46[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG46[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG46[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG46[7:0]

RX_DATA_REG46 [read-only]: reg46
46th 32-bit word

3.70. rx data reg47

HW prefix:	mf_rx_data_reg47
HW address:	0x45
C prefix:	RX_DATA_REG47
C offset:	0x114

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG47[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG47[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG47[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG47[7:0]

RX_DATA_REG47 [read-only]: reg47
47th 32-bit word

3.71. rx data reg48

HW prefix:	mf_rx_data_reg48
HW address:	0x46
C prefix:	RX_DATA_REG48
C offset:	0x118

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG48[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG48[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG48[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG48[7:0]

RX_DATA_REG48 [read-only]: reg48
48th 32-bit word

3.72. rx data reg49

HW prefix:	mf_rx_data_reg49
HW address:	0x47
C prefix:	RX_DATA_REG49
C offset:	0x11c

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG49[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG49[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG49[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG49[7:0]

RX_DATA_REG49 [read-only]: reg49
49th 32-bit word

3.73. rx data reg50

HW prefix:	mf_rx_data_reg50
HW address:	0x48
C prefix:	RX_DATA_REG50
C offset:	0x120

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG50[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG50[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG50[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG50[7:0]

RX_DATA_REG50 [read-only]: reg50
50th 32-bit word

3.74. rx data reg51

HW prefix:	mf_rx_data_reg51
HW address:	0x49
C prefix:	RX_DATA_REG51
C offset:	0x124

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG51[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG51[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG51[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG51[7:0]

RX_DATA_REG51 [read-only]: reg51
51st 32-bit word

3.75. rx data reg52

HW prefix:	mf_rx_data_reg52
HW address:	0x4a
C prefix:	RX_DATA_REG52
C offset:	0x128

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG52[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG52[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG52[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG52[7:0]

RX_DATA_REG52 [read-only]: reg52
52nd 32-bit word

3.76. rx data reg53

HW prefix:	mf_rx_data_reg53
HW address:	0x4b
C prefix:	RX_DATA_REG53
C offset:	0x12c

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG53[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG53[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG53[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG53[7:0]

RX_DATA_REG53 [read-only]: reg53
53rd 32-bit word

3.77. rx data reg54

HW prefix:	mf_rx_data_reg54
HW address:	0x4c
C prefix:	RX_DATA_REG54
C offset:	0x130

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG54[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG54[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG54[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG54[7:0]

RX_DATA_REG54 [read-only]: reg54
54th 32-bit word

3.78. rx data reg55

HW prefix:	mf_rx_data_reg55
HW address:	0x4d
C prefix:	RX_DATA_REG55
C offset:	0x134

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG55[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG55[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG55[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG55[7:0]

RX_DATA_REG55 [read-only]: reg55
55th 32-bit word

3.79. rx data reg56

HW prefix:	mf_rx_data_reg56
HW address:	0x4e
C prefix:	RX_DATA_REG56
C offset:	0x138

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG56[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG56[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG56[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG56[7:0]

RX_DATA_REG56 [read-only]: reg56
56th 32-bit word

3.80. rx data reg57

HW prefix:	mf_rx_data_reg57
HW address:	0x4f
C prefix:	RX_DATA_REG57
C offset:	0x13c

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG57[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG57[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG57[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG57[7:0]

RX_DATA_REG57 [read-only]: reg57
57th 32-bit word

3.81. rx data reg58

HW prefix:	mf_rx_data_reg58
HW address:	0x50
C prefix:	RX_DATA_REG58
C offset:	0x140

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG58[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG58[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG58[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG58[7:0]

RX_DATA_REG58 [read-only]: reg58
58th 32-bit word

3.82. rx data reg59

HW prefix:	mf_rx_data_reg59
HW address:	0x51
C prefix:	RX_DATA_REG59
C offset:	0x144

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG59[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG59[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG59[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG59[7:0]

RX_DATA_REG59 [read-only]: reg59
59th 32-bit word

3.83. rx data reg60

HW prefix:	mf_rx_data_reg60
HW address:	0x52
C prefix:	RX_DATA_REG60
C offset:	0x148

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG60[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG60[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG60[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG60[7:0]

RX_DATA_REG60 [read-only]: reg60
60th 32-bit word

3.84. rx data reg61

HW prefix:	mf_rx_data_reg61
HW address:	0x53
C prefix:	RX_DATA_REG61
C offset:	0x14c

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG61[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG61[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG61[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG61[7:0]

RX_DATA_REG61 [read-only]: reg61
61st 32-bit word

3.85. rx data reg62

HW prefix:	mf_rx_data_reg62
HW address:	0x54
C prefix:	RX_DATA_REG62
C offset:	0x150

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG62[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG62[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG62[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG62[7:0]

RX_DATA_REG62 [read-only]: reg62
62nd 32-bit word

3.86. rx data reg63

HW prefix:	mf_rx_data_reg63
HW address:	0x55
C prefix:	RX_DATA_REG63
C offset:	0x154

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG63[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG63[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG63[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG63[7:0]

RX_DATA_REG63 [read-only]: reg63
63rd 32-bit word

3.87. rx data reg64

HW prefix:	mf_rx_data_reg64
HW address:	0x56
C prefix:	RX_DATA_REG64
C offset:	0x158

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG64[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG64[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG64[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG64[7:0]

RX_DATA_REG64 [read-only]: reg64
64th 32-bit word

3.88. rx data reg65

HW prefix:	mf_rx_data_reg65
HW address:	0x57
C prefix:	RX_DATA_REG65
C offset:	0x15c

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG65[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG65[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG65[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG65[7:0]

RX_DATA_REG65 [read-only]: reg65
65th 32-bit word

3.89. rx data reg66

HW prefix:	mf_rx_data_reg66
HW address:	0x58
C prefix:	RX_DATA_REG66
C offset:	0x160

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG66[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG66[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG66[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG66[7:0]

RX_DATA_REG66 [read-only]: reg66
66th 32-bit word

3.90. rx data reg67

HW prefix:	mf_rx_data_reg67
HW address:	0x59
C prefix:	RX_DATA_REG67
C offset:	0x164

32 bits of the received frame

31	30	29	28	27	26	25	24
RX_DATA_REG67[31:24]

23	22	21	20	19	18	17	16
RX_DATA_REG67[23:16]

15	14	13	12	11	10	9	8
RX_DATA_REG67[15:8]

7	6	5	4	3	2	1	0
RX_DATA_REG67[7:0]

RX_DATA_REG67 [read-only]: reg67
67th 32-bit word

3.91. tx ctrl byte

HW prefix:	mf_tx_data_ctrl
HW address:	0x5a
C prefix:	TX_DATA_CTRL
C offset:	0x168

contains the 8-bits of the control field of a frame to transmit

31	30	29	28	27	26	25	24
-	-	-	-	-	-	-	-

23	22	21	20	19	18	17	16
-	-	-	-	-	-	-	-

15	14	13	12	11	10	9	8
-	-	-	-	-	-	-	-

7	6	5	4	3	2	1	0
TX_DATA_CTRL[7:0]

TX_DATA_CTRL [read/write]: tx ctrl byte
contains the 8-bits of the control field of a frame to transmit

3.92. tx data reg1

HW prefix:	mf_tx_data_reg1
HW address:	0x5b
C prefix:	TX_DATA_REG1
C offset:	0x16c

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG1[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG1[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG1[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG1[7:0]

TX_DATA_REG1 [read/write]: reg1
1st 32-bit word

3.93. tx data reg2

HW prefix:	mf_tx_data_reg2
HW address:	0x5c
C prefix:	TX_DATA_REG2
C offset:	0x170

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG2[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG2[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG2[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG2[7:0]

TX_DATA_REG2 [read/write]: reg2
2nd 32-bit word

3.94. tx data reg3

HW prefix:	mf_tx_data_reg3
HW address:	0x5d
C prefix:	TX_DATA_REG3
C offset:	0x174

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG3[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG3[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG3[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG3[7:0]

TX_DATA_REG3 [read/write]: reg3
3rd 32-bit word

3.95. tx data reg4

HW prefix:	mf_tx_data_reg4
HW address:	0x5e
C prefix:	TX_DATA_REG4
C offset:	0x178

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG4[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG4[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG4[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG4[7:0]

TX_DATA_REG4 [read/write]: reg4
4th 32-bit word

3.96. tx data reg5

HW prefix:	mf_tx_data_reg5
HW address:	0x5f
C prefix:	TX_DATA_REG5
C offset:	0x17c

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG5[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG5[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG5[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG5[7:0]

TX_DATA_REG5 [read/write]: reg5
5th 32-bit word

3.97. tx data reg6

HW prefix:	mf_tx_data_reg6
HW address:	0x60
C prefix:	TX_DATA_REG6
C offset:	0x180

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG6[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG6[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG6[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG6[7:0]

TX_DATA_REG6 [read/write]: reg6
6th 32-bit word

3.98. tx data reg7

HW prefix:	mf_tx_data_reg7
HW address:	0x61
C prefix:	TX_DATA_REG7
C offset:	0x184

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG7[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG7[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG7[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG7[7:0]

TX_DATA_REG7 [read/write]: reg7
7th 32-bit word

3.99. tx data reg8

HW prefix:	mf_tx_data_reg8
HW address:	0x62
C prefix:	TX_DATA_REG8
C offset:	0x188

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG8[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG8[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG8[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG8[7:0]

TX_DATA_REG8 [read/write]: reg8
8th 32-bit word

3.100. tx data reg9

HW prefix:	mf_tx_data_reg9
HW address:	0x63
C prefix:	TX_DATA_REG9
C offset:	0x18c

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG9[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG9[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG9[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG9[7:0]

TX_DATA_REG9 [read/write]: reg9
9th 32-bit word

3.101. tx data reg10

HW prefix:	mf_tx_data_reg10
HW address:	0x64
C prefix:	TX_DATA_REG10
C offset:	0x190

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG10[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG10[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG10[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG10[7:0]

TX_DATA_REG10 [read/write]: reg10
10th 32-bit word

3.102. tx data reg11

HW prefix:	mf_tx_data_reg11
HW address:	0x65
C prefix:	TX_DATA_REG11
C offset:	0x194

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG11[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG11[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG11[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG11[7:0]

TX_DATA_REG11 [read/write]: reg11
11th 32-bit word

3.103. tx data reg12

HW prefix:	mf_tx_data_reg12
HW address:	0x66
C prefix:	TX_DATA_REG12
C offset:	0x198

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG12[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG12[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG12[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG12[7:0]

TX_DATA_REG12 [read/write]: reg12
12th 32-bit word

3.104. tx data reg13

HW prefix:	mf_tx_data_reg13
HW address:	0x67
C prefix:	TX_DATA_REG13
C offset:	0x19c

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG13[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG13[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG13[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG13[7:0]

TX_DATA_REG13 [read/write]: reg13
13th 32-bit word

3.105. tx data reg14

HW prefix:	mf_tx_data_reg14
HW address:	0x68
C prefix:	TX_DATA_REG14
C offset:	0x1a0

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG14[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG14[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG14[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG14[7:0]

TX_DATA_REG14 [read/write]: reg14
14th 32-bit word

3.106. tx data reg15

HW prefix:	mf_tx_data_reg15
HW address:	0x69
C prefix:	TX_DATA_REG15
C offset:	0x1a4

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG15[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG15[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG15[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG15[7:0]

TX_DATA_REG15 [read/write]: reg15
15th 32-bit word

3.107. tx data reg16

HW prefix:	mf_tx_data_reg16
HW address:	0x6a
C prefix:	TX_DATA_REG16
C offset:	0x1a8

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG16[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG16[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG16[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG16[7:0]

TX_DATA_REG16 [read/write]: reg16
16th 32-bit word

3.108. tx data reg17

HW prefix:	mf_tx_data_reg17
HW address:	0x6b
C prefix:	TX_DATA_REG17
C offset:	0x1ac

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG17[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG17[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG17[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG17[7:0]

TX_DATA_REG17 [read/write]: reg17
17th 32-bit word

3.109. tx data reg18

HW prefix:	mf_tx_data_reg18
HW address:	0x6c
C prefix:	TX_DATA_REG18
C offset:	0x1b0

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG18[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG18[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG18[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG18[7:0]

TX_DATA_REG18 [read/write]: reg18
18th 32-bit word

3.110. tx data reg19

HW prefix:	mf_tx_data_reg19
HW address:	0x6d
C prefix:	TX_DATA_REG19
C offset:	0x1b4

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG19[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG19[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG19[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG19[7:0]

TX_DATA_REG19 [read/write]: reg19
19th 32-bit word

3.111. tx data reg20

HW prefix:	mf_tx_data_reg20
HW address:	0x6e
C prefix:	TX_DATA_REG20
C offset:	0x1b8

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG20[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG20[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG20[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG20[7:0]

TX_DATA_REG20 [read/write]: reg20
20th 32-bit word

3.112. tx data reg21

HW prefix:	mf_tx_data_reg21
HW address:	0x6f
C prefix:	TX_DATA_REG21
C offset:	0x1bc

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG21[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG21[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG21[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG21[7:0]

TX_DATA_REG21 [read/write]: reg21
21th 32-bit word

3.113. tx data reg22

HW prefix:	mf_tx_data_reg22
HW address:	0x70
C prefix:	TX_DATA_REG22
C offset:	0x1c0

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG22[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG22[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG22[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG22[7:0]

TX_DATA_REG22 [read/write]: reg22
22th 32-bit word

3.114. tx data reg23

HW prefix:	mf_tx_data_reg23
HW address:	0x71
C prefix:	TX_DATA_REG23
C offset:	0x1c4

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG23[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG23[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG23[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG23[7:0]

TX_DATA_REG23 [read/write]: reg23
23th 32-bit word

3.115. tx data reg24

HW prefix:	mf_tx_data_reg24
HW address:	0x72
C prefix:	TX_DATA_REG24
C offset:	0x1c8

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG24[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG24[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG24[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG24[7:0]

TX_DATA_REG24 [read/write]: reg24
24th 32-bit word

3.116. tx data reg25

HW prefix:	mf_tx_data_reg25
HW address:	0x73
C prefix:	TX_DATA_REG25
C offset:	0x1cc

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG25[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG25[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG25[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG25[7:0]

TX_DATA_REG25 [read/write]: reg25
25th 32-bit word

3.117. tx data reg26

HW prefix:	mf_tx_data_reg26
HW address:	0x74
C prefix:	TX_DATA_REG26
C offset:	0x1d0

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG26[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG26[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG26[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG26[7:0]

TX_DATA_REG26 [read/write]: reg26
26th 32-bit word

3.118. tx data reg27

HW prefix:	mf_tx_data_reg27
HW address:	0x75
C prefix:	TX_DATA_REG27
C offset:	0x1d4

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG27[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG27[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG27[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG27[7:0]

TX_DATA_REG27 [read/write]: reg27
27th 32-bit word

3.119. tx data reg28

HW prefix:	mf_tx_data_reg28
HW address:	0x76
C prefix:	TX_DATA_REG28
C offset:	0x1d8

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG28[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG28[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG28[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG28[7:0]

TX_DATA_REG28 [read/write]: reg28
28th 32-bit word

3.120. tx data reg29

HW prefix:	mf_tx_data_reg29
HW address:	0x77
C prefix:	TX_DATA_REG29
C offset:	0x1dc

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG29[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG29[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG29[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG29[7:0]

TX_DATA_REG29 [read/write]: reg29
29th 32-bit word

3.121. tx data reg30

HW prefix:	mf_tx_data_reg30
HW address:	0x78
C prefix:	TX_DATA_REG30
C offset:	0x1e0

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG30[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG30[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG30[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG30[7:0]

TX_DATA_REG30 [read/write]: reg30
30th 32-bit word

3.122. tx data reg31

HW prefix:	mf_tx_data_reg31
HW address:	0x79
C prefix:	TX_DATA_REG31
C offset:	0x1e4

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG31[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG31[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG31[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG31[7:0]

TX_DATA_REG31 [read/write]: reg31
31th 32-bit word

3.123. tx data reg32

HW prefix:	mf_tx_data_reg32
HW address:	0x7a
C prefix:	TX_DATA_REG32
C offset:	0x1e8

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG32[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG32[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG32[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG32[7:0]

TX_DATA_REG32 [read/write]: reg32
32th 32-bit word

3.124. tx data reg33

HW prefix:	mf_tx_data_reg33
HW address:	0x7b
C prefix:	TX_DATA_REG33
C offset:	0x1ec

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG33[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG33[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG33[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG33[7:0]

TX_DATA_REG33 [read/write]: reg 33
33rd 32-bit word

3.125. tx data reg34

HW prefix:	mf_tx_data_reg34
HW address:	0x7c
C prefix:	TX_DATA_REG34
C offset:	0x1f0

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG34[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG34[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG34[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG34[7:0]

TX_DATA_REG34 [read/write]: reg34
34th 32-bit word

3.126. tx data reg35

HW prefix:	mf_tx_data_reg35
HW address:	0x7d
C prefix:	TX_DATA_REG35
C offset:	0x1f4

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG35[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG35[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG35[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG35[7:0]

TX_DATA_REG35 [read/write]: reg35
35th 32-bit word

3.127. tx data reg36

HW prefix:	mf_tx_data_reg36
HW address:	0x7e
C prefix:	TX_DATA_REG36
C offset:	0x1f8

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG36[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG36[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG36[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG36[7:0]

TX_DATA_REG36 [read/write]: reg36
36th 32-bit word

3.128. tx data reg37

HW prefix:	mf_tx_data_reg37
HW address:	0x7f
C prefix:	TX_DATA_REG37
C offset:	0x1fc

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG37[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG37[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG37[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG37[7:0]

TX_DATA_REG37 [read/write]: reg37
37th 32-bit word

3.129. tx data reg38

HW prefix:	mf_tx_data_reg38
HW address:	0x80
C prefix:	TX_DATA_REG38
C offset:	0x200

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG38[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG38[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG38[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG38[7:0]

TX_DATA_REG38 [read/write]: reg38
38th 32-bit word

3.130. tx data reg39

HW prefix:	mf_tx_data_reg39
HW address:	0x81
C prefix:	TX_DATA_REG39
C offset:	0x204

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG39[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG39[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG39[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG39[7:0]

TX_DATA_REG39 [read/write]: reg39
39th 32-bit word

3.131. tx data reg40

HW prefix:	mf_tx_data_reg40
HW address:	0x82
C prefix:	TX_DATA_REG40
C offset:	0x208

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG40[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG40[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG40[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG40[7:0]

TX_DATA_REG40 [read/write]: reg40
40th 32-bit word

3.132. tx data reg41

HW prefix:	mf_tx_data_reg41
HW address:	0x83
C prefix:	TX_DATA_REG41
C offset:	0x20c

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG41[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG41[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG41[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG41[7:0]

TX_DATA_REG41 [read/write]: reg41
41th 32-bit word

3.133. tx data reg42

HW prefix:	mf_tx_data_reg42
HW address:	0x84
C prefix:	TX_DATA_REG42
C offset:	0x210

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG42[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG42[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG42[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG42[7:0]

TX_DATA_REG42 [read/write]: reg42
42nd 32-bit word

3.134. tx data reg43

HW prefix:	mf_tx_data_reg43
HW address:	0x85
C prefix:	TX_DATA_REG43
C offset:	0x214

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG43[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG43[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG43[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG43[7:0]

TX_DATA_REG43 [read/write]: reg43
43rd 32-bit word

3.135. tx data reg44

HW prefix:	mf_tx_data_reg44
HW address:	0x86
C prefix:	TX_DATA_REG44
C offset:	0x218

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG44[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG44[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG44[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG44[7:0]

TX_DATA_REG44 [read/write]: reg44
44th 32-bit word

3.136. tx data reg45

HW prefix:	mf_tx_data_reg45
HW address:	0x87
C prefix:	TX_DATA_REG45
C offset:	0x21c

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG45[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG45[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG45[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG45[7:0]

TX_DATA_REG45 [read/write]: reg45
45th 32-bit word

3.137. tx data reg46

HW prefix:	mf_tx_data_reg46
HW address:	0x88
C prefix:	TX_DATA_REG46
C offset:	0x220

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG46[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG46[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG46[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG46[7:0]

TX_DATA_REG46 [read/write]: reg46
46th 32-bit word

3.138. tx data reg47

HW prefix:	mf_tx_data_reg47
HW address:	0x89
C prefix:	TX_DATA_REG47
C offset:	0x224

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG47[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG47[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG47[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG47[7:0]

TX_DATA_REG47 [read/write]: reg47
47th 32-bit word

3.139. tx data reg48

HW prefix:	mf_tx_data_reg48
HW address:	0x8a
C prefix:	TX_DATA_REG48
C offset:	0x228

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG48[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG48[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG48[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG48[7:0]

TX_DATA_REG48 [read/write]: reg48
48th 32-bit word

3.140. tx data reg49

HW prefix:	mf_tx_data_reg49
HW address:	0x8b
C prefix:	TX_DATA_REG49
C offset:	0x22c

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG49[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG49[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG49[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG49[7:0]

TX_DATA_REG49 [read/write]: reg49
49th 32-bit word

3.141. tx data reg50

HW prefix:	mf_tx_data_reg50
HW address:	0x8c
C prefix:	TX_DATA_REG50
C offset:	0x230

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG50[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG50[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG50[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG50[7:0]

TX_DATA_REG50 [read/write]: reg50
50th 32-bit word

3.142. tx data reg51

HW prefix:	mf_tx_data_reg51
HW address:	0x8d
C prefix:	TX_DATA_REG51
C offset:	0x234

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG51[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG51[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG51[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG51[7:0]

TX_DATA_REG51 [read/write]: reg51
51st 32-bit word

3.143. tx data reg52

HW prefix:	mf_tx_data_reg52
HW address:	0x8e
C prefix:	TX_DATA_REG52
C offset:	0x238

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG52[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG52[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG52[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG52[7:0]

TX_DATA_REG52 [read/write]: reg52
52nd 32-bit word

3.144. tx data reg53

HW prefix:	mf_tx_data_reg53
HW address:	0x8f
C prefix:	TX_DATA_REG53
C offset:	0x23c

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG53[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG53[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG53[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG53[7:0]

TX_DATA_REG53 [read/write]: reg53
53rd 32-bit word

3.145. tx data reg54

HW prefix:	mf_tx_data_reg54
HW address:	0x90
C prefix:	TX_DATA_REG54
C offset:	0x240

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG54[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG54[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG54[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG54[7:0]

TX_DATA_REG54 [read/write]: reg54
54th 32-bit word

3.146. tx data reg55

HW prefix:	mf_tx_data_reg55
HW address:	0x91
C prefix:	TX_DATA_REG55
C offset:	0x244

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG55[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG55[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG55[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG55[7:0]

TX_DATA_REG55 [read/write]: reg55
55th 32-bit word

3.147. tx data reg56

HW prefix:	mf_tx_data_reg56
HW address:	0x92
C prefix:	TX_DATA_REG56
C offset:	0x248

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG56[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG56[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG56[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG56[7:0]

TX_DATA_REG56 [read/write]: reg56
56th 32-bit word

3.148. tx data reg57

HW prefix:	mf_tx_data_reg57
HW address:	0x93
C prefix:	TX_DATA_REG57
C offset:	0x24c

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG57[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG57[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG57[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG57[7:0]

TX_DATA_REG57 [read/write]: reg57
57th 32-bit word

3.149. tx data reg58

HW prefix:	mf_tx_data_reg58
HW address:	0x94
C prefix:	TX_DATA_REG58
C offset:	0x250

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG58[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG58[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG58[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG58[7:0]

TX_DATA_REG58 [read/write]: reg58
58th 32-bit word

3.150. tx data reg59

HW prefix:	mf_tx_data_reg59
HW address:	0x95
C prefix:	TX_DATA_REG59
C offset:	0x254

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG59[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG59[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG59[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG59[7:0]

TX_DATA_REG59 [read/write]: reg59
59th 32-bit word

3.151. tx data reg60

HW prefix:	mf_tx_data_reg60
HW address:	0x96
C prefix:	TX_DATA_REG60
C offset:	0x258

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG60[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG60[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG60[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG60[7:0]

TX_DATA_REG60 [read/write]: reg60
60th 32-bit word

3.152. tx data reg61

HW prefix:	mf_tx_data_reg61
HW address:	0x97
C prefix:	TX_DATA_REG61
C offset:	0x25c

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG61[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG61[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG61[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG61[7:0]

TX_DATA_REG61 [read/write]: reg61
61st 32-bit word

3.153. tx data reg62

HW prefix:	mf_tx_data_reg62
HW address:	0x98
C prefix:	TX_DATA_REG62
C offset:	0x260

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG62[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG62[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG62[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG62[7:0]

TX_DATA_REG62 [read/write]: reg62
62nd 32-bit word

3.154. tx data reg63

HW prefix:	mf_tx_data_reg63
HW address:	0x99
C prefix:	TX_DATA_REG63
C offset:	0x264

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG63[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG63[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG63[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG63[7:0]

TX_DATA_REG63 [read/write]: reg63
63rd 32-bit word

3.155. tx data reg64

HW prefix:	mf_tx_data_reg64
HW address:	0x9a
C prefix:	TX_DATA_REG64
C offset:	0x268

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG64[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG64[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG64[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG64[7:0]

TX_DATA_REG64 [read/write]: reg64
64th 32-bit word

3.156. tx data reg65

HW prefix:	mf_tx_data_reg65
HW address:	0x9b
C prefix:	TX_DATA_REG65
C offset:	0x26c

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG65[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG65[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG65[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG65[7:0]

TX_DATA_REG65 [read/write]: reg65
65th 32-bit word

3.157. tx data reg66

HW prefix:	mf_tx_data_reg66
HW address:	0x9c
C prefix:	TX_DATA_REG66
C offset:	0x270

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG66[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG66[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG66[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG66[7:0]

TX_DATA_REG66 [read/write]: reg66
66th 32-bit word

3.158. tx data reg67

HW prefix:	mf_tx_data_reg67
HW address:	0x9d
C prefix:	TX_DATA_REG67
C offset:	0x274

32 bits of the received frame

31	30	29	28	27	26	25	24
TX_DATA_REG67[31:24]

23	22	21	20	19	18	17	16
TX_DATA_REG67[23:16]

15	14	13	12	11	10	9	8
TX_DATA_REG67[15:8]

7	6	5	4	3	2	1	0
TX_DATA_REG67[7:0]

TX_DATA_REG67 [read/write]: reg67
67th 32-bit word

fmc_masterfip_csr

FMC masterFIP core registers

Contents: