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MasterFIP - Gateware
Commit 100564c7 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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changed macrocycle counter reloading

parent 936d742a
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rtl/fmc_masterFIP_core.vhd
View file @ 100564c7
......@@ -227,8 +227,10 @@ architecture rtl of fmc_masterFIP_core is
-- config
signal speed : std_logic_vector(1 downto 0);
-- ext pulse
signal ext_sync_p, ext_sync_oe : std_logic;
signal ext_sync, ext_sync_p, ext_sync_oe : std_logic;
signal ext_sync_p_cnt_rst : std_logic;
signal macroc_close_to_end : std_logic;
signal ext_sync_safe_p, ext_sync_filt : std_logic;
signal ext_sync_p_cnt : std_logic_vector(g_width-1 downto 0);
-- counters
signal macrocyc_load_p, turnar_load_p : std_logic;
......@@ -260,8 +262,7 @@ architecture rtl of fmc_masterFIP_core is
signal tmp_id : std_logic_vector(63 downto 0);
signal onewire_read_p, pps_is_zero : std_logic;
signal pps_load_p : std_logic;
-- ext_sync
signal ext_sync, ext_sync_filt : std_logic;
-- chipscope
-- component chipscope_ila
......@@ -377,7 +378,7 @@ begin
-- counter of the number of rising edges
cmp_ext_sync_p_cnt:incr_counter
generic map(g_counter_lgth => 32) -- for the fastest macrocycle of 20ms, the counter
-- can keep counting for > 2.5 years
-- can keep counting for 2.7 years
port map
(clk_i => clk_i,
counter_incr_i => ext_sync_p,
......@@ -390,15 +391,13 @@ begin
---------------------------------------------------------------------------------------------------
-- MACROCYCLE COUNTER --
---------------------------------------------------------------------------------------------------
-- Regarding synchronisation, the masterFIP application can work in two modes:
-- using an internal counter that counts each macrocycle based on the local oscillator, or
-- using the ext_sync pulse to signal the beginning of each macrocycle. There is also the option
-- that when the external pulse does not arrive, the internal counter takes over the synchronisation.
-- In an application where the external synchronization pulse is expected for every macrocycle,
-- the macrocyc_lgth is set by the sw application slightly larger than the external synchronization
-- period; therefore the macrocycle counter should not be reaching zero; if it reaches zero,
-- it would mean that the external synchronization pulse did not arrive in time and a new
-- macrocycle (slightly longer) will start automatically based on this internal counter.
-- Regarding synchronisation, the masterFIP application can work in three modes:
-- 1) using an internal counter that counts each macrocycle based on the SPEC local oscillator;
-- this mode is active based on the state of the transceiver signal ext_sync_ctrl_oe_n_o.
-- 2) using the ext_sync pulse to signal the beginning of each macrocycle
-- 3) using the ext_sync pulse to signal the beginning of each macrocycle together with an input
-- from the processor indicating that all the periodic traffic has been completed and the processor
-- is ready to start a new macrocycle.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- counter counting the macrocycle time;
......@@ -415,13 +414,15 @@ begin
-- -- -- -- -- -- -- -- -- -- --
reg_to_mt.macrocyc_time_cnt_i <= macrocyc_cnt;
macrocyc_load_p <= macrocyc_cnt_zero_p or reg_from_mt.macrocyc_start_o or ext_sync_p;
macrocyc_load_p <= macrocyc_cnt_zero_p or reg_from_mt.macrocyc_start_o when reg_from_mt.ext_sync_ctrl_oe_n_o = '1' -- internal counting
else ext_sync_p when reg_from_mt.ext_sync_ctrl_oe_n_o = '0' and reg_from_mt.ext_sync_ctrl_opt_o = '0' -- pure external control
else ext_sync_p and reg_from_mt.ext_sync_ctrl_safe_wind_o; -- macrocycle restart, based on macrocycle execution
-- note: macrocyc_start_o is a monostable, 1-clk-tick-long pulse
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- counter counting the number of macrocycles;
-- being a 32-bit counter, for the fastest application of 20 ms macrocycle, the counter can
-- keep counting for 994 days; when it fills up it would restart from 0.
-- keep counting for 2.7 years; when it fills up it would restart from 0.
cmp_macrocycles_cnt:incr_counter
generic map(g_counter_lgth => g_width)
port map
......@@ -835,8 +836,8 @@ begin
leds_o(1) <= not reg_from_mt.led_rx_err_o;
leds_o(2) <= not reg_from_mt.led_tx_act_o;
leds_o(3) <= not reg_from_mt.led_tx_err_o;
leds_o(4) <= not reg_from_mt.led_ext_sync_act_o when reg_from_mt.led_ext_sync_used_o = '1' else '0';
leds_o(5) <= not reg_from_mt.led_ext_sync_err_o when reg_from_mt.led_ext_sync_used_o = '1' else '0';
leds_o(4) <= not reg_from_mt.led_ext_sync_act_o when reg_from_mt.ext_sync_ctrl_oe_n_o = '0' else '0';
leds_o(5) <= not reg_from_mt.led_ext_sync_err_o when reg_from_mt.ext_sync_ctrl_oe_n_o = '0' else '0';
leds_o(7 downto 6) <= "00"; -- not used
leds_o(31 downto 8) <= reg_from_mt.led_dbg_o;
......
rtl/masterfip_wbgen2_csr.vhd
View file @ 100564c7
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_csr.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 02/09/17 10:52:07
-- Created : 04/12/17 12:25:04
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
......@@ -45,7 +45,6 @@ signal masterfip_led_rx_act_int : std_logic ;
signal masterfip_led_rx_err_int : std_logic ;
signal masterfip_led_tx_act_int : std_logic ;
signal masterfip_led_tx_err_int : std_logic ;
signal masterfip_led_ext_sync_used_int : std_logic ;
signal masterfip_led_ext_sync_act_int : std_logic ;
signal masterfip_led_ext_sync_err_int : std_logic ;
signal masterfip_led_dbg_int : std_logic_vector(23 downto 0);
......@@ -53,6 +52,8 @@ signal masterfip_ext_sync_ctrl_term_en_int : std_logic ;
signal masterfip_ext_sync_ctrl_dir_int : std_logic ;
signal masterfip_ext_sync_ctrl_oe_n_int : std_logic ;
signal masterfip_ext_sync_ctrl_p_cnt_rst_int : std_logic ;
signal masterfip_ext_sync_ctrl_opt_int : std_logic ;
signal masterfip_ext_sync_ctrl_safe_wind_int : std_logic ;
signal masterfip_macrocyc_lgth_int : std_logic_vector(30 downto 0);
signal masterfip_macrocyc_start_dly0 : std_logic ;
signal masterfip_macrocyc_start_int : std_logic ;
......@@ -170,7 +171,6 @@ begin
masterfip_led_rx_err_int <= '0';
masterfip_led_tx_act_int <= '0';
masterfip_led_tx_err_int <= '0';
masterfip_led_ext_sync_used_int <= '0';
masterfip_led_ext_sync_act_int <= '0';
masterfip_led_ext_sync_err_int <= '0';
masterfip_led_dbg_int <= "000000000000000000000000";
......@@ -178,6 +178,8 @@ begin
masterfip_ext_sync_ctrl_dir_int <= '0';
masterfip_ext_sync_ctrl_oe_n_int <= '0';
masterfip_ext_sync_ctrl_p_cnt_rst_int <= '0';
masterfip_ext_sync_ctrl_opt_int <= '0';
masterfip_ext_sync_ctrl_safe_wind_int <= '0';
masterfip_macrocyc_lgth_int <= "0000000000000000000000000000000";
masterfip_macrocyc_start_int <= '0';
masterfip_turnar_lgth_int <= "0000000000000000000000000000000";
......@@ -329,19 +331,18 @@ begin
masterfip_led_rx_err_int <= wrdata_reg(1);
masterfip_led_tx_act_int <= wrdata_reg(2);
masterfip_led_tx_err_int <= wrdata_reg(3);
masterfip_led_ext_sync_used_int <= wrdata_reg(4);
masterfip_led_ext_sync_act_int <= wrdata_reg(5);
masterfip_led_ext_sync_err_int <= wrdata_reg(6);
masterfip_led_ext_sync_act_int <= wrdata_reg(4);
masterfip_led_ext_sync_err_int <= wrdata_reg(5);
masterfip_led_dbg_int <= wrdata_reg(31 downto 8);
end if;
rddata_reg(0) <= masterfip_led_rx_act_int;
rddata_reg(1) <= masterfip_led_rx_err_int;
rddata_reg(2) <= masterfip_led_tx_act_int;
rddata_reg(3) <= masterfip_led_tx_err_int;
rddata_reg(4) <= masterfip_led_ext_sync_used_int;
rddata_reg(5) <= masterfip_led_ext_sync_act_int;
rddata_reg(6) <= masterfip_led_ext_sync_err_int;
rddata_reg(4) <= masterfip_led_ext_sync_act_int;
rddata_reg(5) <= masterfip_led_ext_sync_err_int;
rddata_reg(31 downto 8) <= masterfip_led_dbg_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
......@@ -385,11 +386,15 @@ begin
masterfip_ext_sync_ctrl_dir_int <= wrdata_reg(1);
masterfip_ext_sync_ctrl_oe_n_int <= wrdata_reg(2);
masterfip_ext_sync_ctrl_p_cnt_rst_int <= wrdata_reg(8);
masterfip_ext_sync_ctrl_opt_int <= wrdata_reg(16);
masterfip_ext_sync_ctrl_safe_wind_int <= wrdata_reg(24);
end if;
rddata_reg(0) <= masterfip_ext_sync_ctrl_term_en_int;
rddata_reg(1) <= masterfip_ext_sync_ctrl_dir_int;
rddata_reg(2) <= masterfip_ext_sync_ctrl_oe_n_int;
rddata_reg(8) <= masterfip_ext_sync_ctrl_p_cnt_rst_int;
rddata_reg(16) <= masterfip_ext_sync_ctrl_opt_int;
rddata_reg(24) <= masterfip_ext_sync_ctrl_safe_wind_int;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
......@@ -402,7 +407,6 @@ begin
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
......@@ -410,7 +414,6 @@ begin
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
......@@ -1715,8 +1718,6 @@ begin
regs_o.led_tx_act_o <= masterfip_led_tx_act_int;
-- tx err red led
regs_o.led_tx_err_o <= masterfip_led_tx_err_int;
-- write 1 to indicate that the ext sync is used
regs_o.led_ext_sync_used_o <= masterfip_led_ext_sync_used_int;
-- ext sync act green led
regs_o.led_ext_sync_act_o <= masterfip_led_ext_sync_act_int;
-- ext sync err red led
......@@ -1734,6 +1735,10 @@ begin
regs_o.ext_sync_ctrl_oe_n_o <= masterfip_ext_sync_ctrl_oe_n_int;
-- pulses counter reset
regs_o.ext_sync_ctrl_p_cnt_rst_o <= masterfip_ext_sync_ctrl_p_cnt_rst_int;
-- counting options
regs_o.ext_sync_ctrl_opt_o <= masterfip_ext_sync_ctrl_opt_int;
-- safe window
regs_o.ext_sync_ctrl_safe_wind_o <= masterfip_ext_sync_ctrl_safe_wind_int;
-- ext_sync_p_cnt
-- WorldFIP speed, hard-wired on the FMC
-- macrocycle lgth
......
rtl/masterfip_wbgen2_pkg.vhd
View file @ 100564c7
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 02/09/17 10:52:07
-- Created : 04/12/17 12:25:04
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
......@@ -216,7 +216,6 @@ package masterfip_wbgen2_pkg is
led_rx_err_o : std_logic;
led_tx_act_o : std_logic;
led_tx_err_o : std_logic;
led_ext_sync_used_o : std_logic;
led_ext_sync_act_o : std_logic;
led_ext_sync_err_o : std_logic;
led_dbg_o : std_logic_vector(23 downto 0);
......@@ -224,6 +223,8 @@ package masterfip_wbgen2_pkg is
ext_sync_ctrl_dir_o : std_logic;
ext_sync_ctrl_oe_n_o : std_logic;
ext_sync_ctrl_p_cnt_rst_o : std_logic;
ext_sync_ctrl_opt_o : std_logic;
ext_sync_ctrl_safe_wind_o : std_logic;
macrocyc_lgth_o : std_logic_vector(30 downto 0);
macrocyc_start_o : std_logic;
turnar_lgth_o : std_logic_vector(30 downto 0);
......@@ -311,7 +312,6 @@ package masterfip_wbgen2_pkg is
led_rx_err_o => '0',
led_tx_act_o => '0',
led_tx_err_o => '0',
led_ext_sync_used_o => '0',
led_ext_sync_act_o => '0',
led_ext_sync_err_o => '0',
led_dbg_o => (others => '0'),
......@@ -319,6 +319,8 @@ package masterfip_wbgen2_pkg is
ext_sync_ctrl_dir_o => '0',
ext_sync_ctrl_oe_n_o => '0',
ext_sync_ctrl_p_cnt_rst_o => '0',
ext_sync_ctrl_opt_o => '0',
ext_sync_ctrl_safe_wind_o => '0',
macrocyc_lgth_o => (others => '0'),
macrocyc_start_o => '0',
turnar_lgth_o => (others => '0'),
......
rtl/wbgen/build_from_wb.sh 0 → 100644
View file @ 100564c7
#!/bin/bash
wbgen2 -V master_wbgen2_csr.vhd -H record -p master_wbgen2_pkg.vhd -s defines -C master_wbgen2_csr.h -D master_wbgen2_csr.html master_csr.wb
echo ""
echo "Moving WB generated files to the following locations..."
echo ""
mv -v ./master_wbgen2_csr.vhd ../.
mv -v ./master_wbgen2_pkg.vhd ../.
rtl/wbgen/masterfip_csr.wb
View file @ 100564c7
......@@ -91,13 +91,6 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "write 1 to indicate that the ext sync is used";
prefix = "ext_sync_used";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "ext sync act green led";
prefix = "ext_sync_act";
......@@ -115,6 +108,7 @@ peripheral {
field {
name = "dbg";
prefix = "dbg";
description = "bit 8 is connected to TP3; bit 9 is connected to TP4";
size = 24;
align = 8;
type = SLV;
......@@ -203,9 +197,8 @@ peripheral {
field {
name = "transceiver output enable negative logic";
prefix = "oe_n";
description = "write 0: normal operation, the external sync pulse arrives to the FPGA\
write 1: the external sync pulse does not arrive to the FPGA\
WARNING: this bit is hard-wired in the HDL top to 0";
description = "write 0: normal operation, the external sync pulse arrives to the FPGA and controls the macrocycle counter\
write 1: the external sync pulse is disabled; the macrocycle counting is based on internal counters";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -219,7 +212,33 @@ peripheral {
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
field {
name = "counting options";
prefix = "opt";
description = "0: external pulse resets the macrocycle counter whenever it arrives\
1: external pulse resets the macrocycle counter, only when it arrives in a window as expected by the\
processor and the macrocycle configuration. In this option for example if a macrocycle is set at 20 ms\
but a pulse arrives every 10 ms by mistake, then one every 2 pulses will be ignored.\
Note that the ext_sync_p_cnt will be counting in any case all the incoming pulses, so the error will\
be reported, but the macrocycle will run smoothly at 20 ms";
type = BIT;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "safe window";
prefix = "safe_wind";
description = "0: processor busy with periodic traffic; reception of a new external pulse is NOT safe\
1: processor ready for a new external pulse; macrocycle periodic part has been played";
type = BIT;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
......@@ -229,7 +248,7 @@ peripheral {
field {
name = "ext_sync_p_cnt";
description = "number of ext sync pulses since the application startup OR a rst_core OR a ext_sync_p_cnt_rst;\
for the fastest macrocycle of 20ms, the counter can keep counting for up to >2.5 years.";
for the fastest macrocycle of 20ms, the counter can keep counting for up to 2.7 years.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -310,7 +329,7 @@ peripheral {
field {
name = "number of macrocycles";
description = "amount of macrocycles that have been counted since the application startup OR a rst_core;\
for the fastest macrocycle of 20ms, the counter can keep counting for up to >2.5 years.";
for the fastest macrocycle of 20ms, the counter can keep counting for up to 2.7 years.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......
rtl/wbgen/masterfip_wbgen2_csr.h
View file @ 100564c7
......@@ -3,7 +3,7 @@
* File : masterfip_wbgen2_csr.h
* Author : auto-generated by wbgen2 from masterfip_csr.wb
* Created : 02/09/17 10:52:07
* Created : 04/12/17 12:25:05
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
......@@ -55,14 +55,11 @@
/* definitions for field: tx err red led in reg: leds and debug */
#define MASTERFIP_LED_TX_ERR WBGEN2_GEN_MASK(3, 1)
/* definitions for field: write 1 to indicate that the ext sync is used in reg: leds and debug */
#define MASTERFIP_LED_EXT_SYNC_USED WBGEN2_GEN_MASK(4, 1)
/* definitions for field: ext sync act green led in reg: leds and debug */
#define MASTERFIP_LED_EXT_SYNC_ACT WBGEN2_GEN_MASK(5, 1)
#define MASTERFIP_LED_EXT_SYNC_ACT WBGEN2_GEN_MASK(4, 1)
/* definitions for field: ext sync err red led in reg: leds and debug */
#define MASTERFIP_LED_EXT_SYNC_ERR WBGEN2_GEN_MASK(6, 1)
#define MASTERFIP_LED_EXT_SYNC_ERR WBGEN2_GEN_MASK(5, 1)
/* definitions for field: dbg in reg: leds and debug */
#define MASTERFIP_LED_DBG_MASK WBGEN2_GEN_MASK(8, 24)
......@@ -90,6 +87,12 @@
/* definitions for field: pulses counter reset in reg: ext sync ctrl */
#define MASTERFIP_EXT_SYNC_CTRL_P_CNT_RST WBGEN2_GEN_MASK(8, 1)
/* definitions for field: counting options in reg: ext sync ctrl */
#define MASTERFIP_EXT_SYNC_CTRL_OPT WBGEN2_GEN_MASK(16, 1)
/* definitions for field: safe window in reg: ext sync ctrl */
#define MASTERFIP_EXT_SYNC_CTRL_SAFE_WIND WBGEN2_GEN_MASK(24, 1)
/* definitions for register: ext sync pulses cnt */
/* definitions for register: bus speed */
......
rtl/wbgen/masterfip_wbgen2_csr.html
View file @ 100564c7
......@@ -3169,23 +3169,6 @@ masterfip_led_tx_err_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
masterfip_led_ext_sync_used_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
masterfip_led_ext_sync_act_o
......@@ -3489,6 +3472,40 @@ masterfip_ext_sync_ctrl_p_cnt_rst_o
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
masterfip_ext_sync_ctrl_opt_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
masterfip_ext_sync_ctrl_safe_wind_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -12336,6 +12353,9 @@ DBG[7:0]
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
EXT_SYNC_ERR
</td>
......@@ -12343,9 +12363,6 @@ EXT_SYNC_ERR
EXT_SYNC_ACT
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
EXT_SYNC_USED
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TX_ERR
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
......@@ -12373,9 +12390,6 @@ TX_ACT
TX_ERR
</b>[<i>read/write</i>]: tx err red led
<li><b>
EXT_SYNC_USED
</b>[<i>read/write</i>]: write 1 to indicate that the ext sync is used
<li><b>
EXT_SYNC_ACT
</b>[<i>read/write</i>]: ext sync act green led
<li><b>
......@@ -12384,6 +12398,7 @@ EXT_SYNC_ERR
<li><b>
DBG
</b>[<i>read/write</i>]: dbg
<br>bit 8 is connected to TP3; bit 9 is connected to TP4
</ul>
<a name="DS1820_TEMPER"></a>
<h3><a name="sect_3_4">3.4. fmc temperature</a></h3>
......@@ -13250,8 +13265,8 @@ EXT_SYNC_CTRL
<td class="td_unused">
-
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
SAFE_WIND
</td>
</tr>
</table>
......@@ -13304,8 +13319,8 @@ EXT_SYNC_CTRL
<td class="td_unused">
-
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
OPT
</td>
</tr>
</table>
......@@ -13429,11 +13444,19 @@ DIR
<li><b>
OE_N
</b>[<i>read/write</i>]: transceiver output enable negative logic
<br>write 0: normal operation, the external sync pulse arrives to the FPGA<br> write 1: the external sync pulse does not arrive to the FPGA<br> WARNING: this bit is hard-wired in the HDL top to 0
<br>write 0: normal operation, the external sync pulse arrives to the FPGA and controls the macrocycle counter<br> write 1: the external sync pulse is disabled; the macrocycle counting is based on internal counters
<li><b>
P_CNT_RST
</b>[<i>read/write</i>]: pulses counter reset
<br>resets the pulses counter
<li><b>
OPT
</b>[<i>read/write</i>]: counting options
<br>0: external pulse resets the macrocycle counter whenever it arrives<br> 1: external pulse resets the macrocycle counter, only when it arrives in a window as expected by the<br> processor and the macrocycle configuration. In this option for example if a macrocycle is set at 20 ms<br> but a pulse arrives every 10 ms by mistake, then one every 2 pulses will be ignored.<br> Note that the ext_sync_p_cnt will be counting in any case all the incoming pulses, so the error will<br> be reported, but the macrocycle will run smoothly at 20 ms
<li><b>
SAFE_WIND
</b>[<i>read/write</i>]: safe window
<br>0: processor busy with periodic traffic; reception of a new external pulse is NOT safe<br> 1: processor ready for a new external pulse; macrocycle periodic part has been played
</ul>
<a name="EXT_SYNC_P_CNT"></a>
<h3><a name="sect_3_8">3.8. ext sync pulses cnt</a></h3>
......@@ -13691,7 +13714,7 @@ EXT_SYNC_P_CNT[7:0]
<li><b>
EXT_SYNC_P_CNT
</b>[<i>read-only</i>]: ext_sync_p_cnt
<br>number of ext sync pulses since the application startup OR a rst_core OR a ext_sync_p_cnt_rst;<br> for the fastest macrocycle of 20ms, the counter can keep counting for up to >2.5 years.
<br>number of ext sync pulses since the application startup OR a rst_core OR a ext_sync_p_cnt_rst;<br> for the fastest macrocycle of 20ms, the counter can keep counting for up to 2.7 years.
</ul>
<a name="SPEED"></a>
<h3><a name="sect_3_9">3.9. bus speed</a></h3>
......@@ -14727,7 +14750,7 @@ MACROCYC_NUM_CNT[7:0]
<li><b>
MACROCYC_NUM_CNT
</b>[<i>read-only</i>]: number of macrocycles
<br>amount of macrocycles that have been counted since the application startup OR a rst_core;<br> for the fastest macrocycle of 20ms, the counter can keep counting for up to >2.5 years.
<br>amount of macrocycles that have been counted since the application startup OR a rst_core;<br> for the fastest macrocycle of 20ms, the counter can keep counting for up to 2.7 years.
</ul>
<a name="TURNAR"></a>
<h3><a name="sect_3_13">3.13. turnaround lgth</a></h3>
......
syn/spec/spec_masterfip_mt.par
View file @ 100564c7
Release 14.7 par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PCBE13457:: Wed Mar 29 14:40:51 2017
PCBE13457:: Wed Apr 12 12:39:20 2017
par -w -intstyle ise -ol high -mt off spec_masterfip_mt_map.ncd
spec_masterfip_mt.ncd spec_masterfip_mt.pcf
......@@ -10,6 +10,20 @@ spec_masterfip_mt.ncd spec_masterfip_mt.pcf
Constraints file: spec_masterfip_mt.pcf.
Loading device for application Rf_Device from file '6slx45t.nph' in environment C:\EDA\Xilinx\14.7\ISE_DS\ISE\.
"spec_masterfip_mt" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -3
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to
'2112@lxlicen01,2112@lxlicen02,2112@lxlicen03'.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to ';1702@lxlicen08'.
INFO:Security:54 - 'xc6slx45t' is a WebPack part.
WARNING:Security:43 - No license file was found in the standard Xilinx license directory.
WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your license support version '2017.04' for ISE expires in 18 days after which you will not qualify
for Xilinx software updates or new releases.
----------------------------------------------------------------------
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
......@@ -22,16 +36,16 @@ Device speed data version: "PRODUCTION 1.23 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 12,630 out of 54,576 23%
Number used as Flip Flops: 12,628
Number of Slice Registers: 12,635 out of 54,576 23%
Number used as Flip Flops: 12,633
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 2
Number of Slice LUTs: 15,771 out of 27,288 57%
Number used as logic: 12,467 out of 27,288 45%
Number using O6 output only: 10,336
Number using O5 output only: 395
Number using O5 and O6: 1,736
Number of Slice LUTs: 15,741 out of 27,288 57%
Number used as logic: 12,500 out of 27,288 45%
Number using O6 output only: 10,376
Number using O5 output only: 393
Number using O5 and O6: 1,731
Number used as ROM: 0
Number used as Memory: 2,828 out of 6,408 44%
Number used as Dual Port RAM: 2,828
......@@ -40,18 +54,18 @@ Slice Logic Utilization:
Number using O5 and O6: 32
Number used as Single Port RAM: 0
Number used as Shift Register: 0
Number used exclusively as route-thrus: 476
Number with same-slice register load: 448
Number with same-slice carry load: 28
Number used exclusively as route-thrus: 413
Number with same-slice register load: 384
Number with same-slice carry load: 29
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 5,512 out of 6,822 80%
Number of occupied Slices: 5,480 out of 6,822 80%
Number of MUXCYs used: 1,452 out of 13,644 10%
Number of LUT Flip Flop pairs used: 19,206
Number with an unused Flip Flop: 7,648 out of 19,206 39%
Number with an unused LUT: 3,435 out of 19,206 17%
Number of fully used LUT-FF pairs: 8,123 out of 19,206 42%
Number of LUT Flip Flop pairs used: 19,263
Number with an unused Flip Flop: 7,657 out of 19,263 39%
Number with an unused LUT: 3,522 out of 19,263 18%
Number of fully used LUT-FF pairs: 8,084 out of 19,263 41%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
......@@ -124,103 +138,107 @@ WARNING:Par:288 - The signal l_wr_rdy_i<0>_IBUF has no load. PAR will not attem
WARNING:Par:288 - The signal l_wr_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem13_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem10_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem9_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem22_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem12_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem11_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem12_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem14_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem19_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem15_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem22_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem16_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem21_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem6_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem3_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem20_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem31_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem28_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem32_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem27_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem21_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem24_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem19_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem4_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem15_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem26_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem16_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem19_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem14_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem7_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem17_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem5_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem29_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem8_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem28_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem19_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem27_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem32_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem23_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem20_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem24_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem43_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem20_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem44_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem6_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem5_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem22_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem18_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem21_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem10_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem8_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem20_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem10_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem9_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem17_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem18_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem11_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem2_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem18_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem10_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem17_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem30_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem23_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem25_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem3_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem43_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem22_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem4_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem21_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem3_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem3_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem7_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem7_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem8_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem4_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem15_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem12_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMB_DPO
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem31_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMC_DPO
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem29_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem30_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem14_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem18_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem11_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem25_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem12_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem7_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMB_DPO
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem26_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMC_DPO
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem44_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMB_DPO
has no load. PAR will not attempt to route this signal.
......@@ -228,50 +246,48 @@ WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_w
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem15_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem13_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem8_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem6_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem1_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem5_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem9_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem16_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem5_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem13_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem4_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem14_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem6_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem2_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem16_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem1_RAMD_O
has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 111392 unrouted; REAL time: 21 secs
Phase 1 : 111354 unrouted; REAL time: 20 secs
Phase 2 : 102625 unrouted; REAL time: 24 secs
Phase 2 : 102665 unrouted; REAL time: 23 secs
Phase 3 : 52201 unrouted; REAL time: 1 mins 7 secs
Phase 3 : 52819 unrouted; REAL time: 1 mins 5 secs
Phase 4 : 53520 unrouted; (Setup:0, Hold:7911, Component Switching Limit:0) REAL time: 1 mins 23 secs
Phase 4 : 55464 unrouted; (Setup:2990, Hold:8015, Component Switching Limit:0) REAL time: 1 mins 35 secs
Updating file: spec_masterfip_mt.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:7822, Component Switching Limit:0) REAL time: 6 mins 37 secs
Phase 5 : 0 unrouted; (Setup:8376, Hold:7012, Component Switching Limit:0) REAL time: 10 mins 39 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:7822, Component Switching Limit:0) REAL time: 6 mins 37 secs
Phase 6 : 0 unrouted; (Setup:3516, Hold:7012, Component Switching Limit:0) REAL time: 17 mins 53 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:7822, Component Switching Limit:0) REAL time: 6 mins 37 secs
Updating file: spec_masterfip_mt.ncd with current fully routed design.
Phase 7 : 0 unrouted; (Setup:3516, Hold:7012, Component Switching Limit:0) REAL time: 18 mins 53 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:7822, Component Switching Limit:0) REAL time: 6 mins 37 secs
Phase 8 : 0 unrouted; (Setup:3516, Hold:7012, Component Switching Limit:0) REAL time: 18 mins 53 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 mins 38 secs
Phase 9 : 0 unrouted; (Setup:3516, Hold:0, Component Switching Limit:0) REAL time: 18 mins 55 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 mins 44 secs
Total REAL time to Router completion: 6 mins 44 secs
Total CPU time to Router completion: 6 mins 53 secs
Phase 10 : 0 unrouted; (Setup:2991, Hold:0, Component Switching Limit:0) REAL time: 19 mins
Total REAL time to Router completion: 19 mins
Total CPU time to Router completion: 19 mins 18 secs
Partition Implementation Status
-------------------------------
......@@ -290,11 +306,11 @@ Generating Clock Report
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/clk_ | | | | | |
| sys | BUFGMUX_X2Y3| No | 4506 | 0.549 | 1.760 |
| sys | BUFGMUX_X2Y3| No | 4429 | 0.548 | 1.759 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/gen_ | | | | | |
|with_gennum.U_GN4124 | | | | | |
| _Core/sys_clk | BUFGMUX_X3Y13| No | 224 | 0.493 | 1.704 |
| _Core/sys_clk | BUFGMUX_X3Y13| No | 220 | 0.493 | 1.704 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/gen_ | | | | | |
|with_gennum.U_GN4124 | | | | | |
......@@ -309,7 +325,23 @@ the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Timing Score: 2991 (Setup: 2991, Hold: 0, Component Switching Limit: 0)
WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design.
Review the timing report using Timing Analyzer (In ISE select "Post-Place &
Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options
are set in the tools for timing closure.
Use the Xilinx "SmartXplorer" script to try special combinations of
options known to produce very good results.
Visit the Xilinx technical support web at http://support.xilinx.com and go to
either "Troubleshoot->Tech Tips->Timing & Constraints" or "
TechXclusives->Timing Closure" for tips and suggestions for meeting timing
in your design.
Number of Timing Constraints that were not applied: 6
......@@ -320,13 +352,13 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_pllout_clk_sys_0 = PER | SETUP | 0.031ns| 9.969ns| 0| 0
IOD TIMEGRP "cmp_mock_turtle_pllo | HOLD | 0.388ns| | 0| 0
* TS_cmp_mock_turtle_pllout_clk_sys_0 = PER | SETUP | -0.622ns| 10.622ns| 17| 2991
IOD TIMEGRP "cmp_mock_turtle_pllo | HOLD | 0.278ns| | 0| 0
ut_clk_sys_0" TS_clk_125m_pllref_n_i / 0. | | | | |
8 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_gen_with_gennum_U_GN41 | SETUP | 0.040ns| 4.960ns| 0| 0
24_Core_cmp_clk_in_rx_pllout_x1 = | HOLD | 0.126ns| | 0| 0
TS_cmp_mock_turtle_gen_with_gennum_U_GN41 | SETUP | 0.064ns| 4.936ns| 0| 0
24_Core_cmp_clk_in_rx_pllout_x1 = | HOLD | 0.086ns| | 0| 0
PERIOD TIMEGRP "cmp_mock_turtle_ | | | | |
gen_with_gennum_U_GN4124_Core_cmp_clk_in_ | | | | |
rx_pllout_x1" TS_cmp_mock_turtle_ | | | | |
......@@ -387,8 +419,8 @@ Derived Constraints for TS_clk_125m_pllref_n_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk_125m_pllref_n_i | 8.000ns| 3.334ns| 7.975ns| 0| 0| 0| 4832382|
| TS_cmp_mock_turtle_pllout_clk_| 10.000ns| 9.969ns| N/A| 0| 0| 4832382| 0|
|TS_clk_125m_pllref_n_i | 8.000ns| 3.334ns| 8.498ns| 0| 17| 0| 4836561|
| TS_cmp_mock_turtle_pllout_clk_| 10.000ns| 10.622ns| N/A| 17| 0| 4836561| 0|
| sys_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
......@@ -398,20 +430,20 @@ Derived Constraints for TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_U_Node_Template_U_GN4124_Cor| 5.000ns| 0.925ns| 4.960ns| 0| 0| 0| 4827|
|TS_U_Node_Template_U_GN4124_Cor| 5.000ns| 0.925ns| 4.936ns| 0| 0| 0| 4827|
|e_cmp_clk_in_P_clk | | | | | | | |
| TS_cmp_mock_turtle_gen_with_ge| 5.000ns| 2.800ns| 4.960ns| 0| 0| 0| 4827|
| TS_cmp_mock_turtle_gen_with_ge| 5.000ns| 2.800ns| 4.936ns| 0| 0| 0| 4827|
| nnum_U_GN4124_Core_cmp_clk_in_| | | | | | | |
| buf_P_clk | | | | | | | |
| TS_cmp_mock_turtle_gen_with_g| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| ennum_U_GN4124_Core_cmp_clk_i| | | | | | | |
| n_rx_pllout_xs_int | | | | | | | |
| TS_cmp_mock_turtle_gen_with_g| 5.000ns| 4.960ns| N/A| 0| 0| 4827| 0|
| TS_cmp_mock_turtle_gen_with_g| 5.000ns| 4.936ns| N/A| 0| 0| 4827| 0|
| ennum_U_GN4124_Core_cmp_clk_i| | | | | | | |
| n_rx_pllout_x1 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
1 constraint not met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
......@@ -425,17 +457,17 @@ All signals are completely routed.
WARNING:Par:283 - There are 71 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 6 mins 50 secs
Total CPU time to PAR completion: 6 mins 59 secs
Total REAL time to PAR completion: 19 mins 7 secs
Total CPU time to PAR completion: 19 mins 24 secs
Peak Memory Usage: 891 MB
Peak Memory Usage: 939 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Timing: Completed - 17 errors found.
Number of error messages: 0
Number of warning messages: 73
Number of warning messages: 74
Number of info messages: 1
Writing design to file spec_masterfip_mt.ncd
......
syn/spec/spec_masterfip_mt.syr
View file @ 100564c7
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syn/spec/spec_masterfip_mt.twr
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syn/spec/spec_masterfip_mt_map.mrp
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