Commit 100564c7 authored by Evangelia Gousiou's avatar Evangelia Gousiou

changed macrocycle counter reloading

parent 936d742a
......@@ -227,8 +227,10 @@ architecture rtl of fmc_masterFIP_core is
-- config
signal speed : std_logic_vector(1 downto 0);
-- ext pulse
signal ext_sync_p, ext_sync_oe : std_logic;
signal ext_sync, ext_sync_p, ext_sync_oe : std_logic;
signal ext_sync_p_cnt_rst : std_logic;
signal macroc_close_to_end : std_logic;
signal ext_sync_safe_p, ext_sync_filt : std_logic;
signal ext_sync_p_cnt : std_logic_vector(g_width-1 downto 0);
-- counters
signal macrocyc_load_p, turnar_load_p : std_logic;
......@@ -260,8 +262,7 @@ architecture rtl of fmc_masterFIP_core is
signal tmp_id : std_logic_vector(63 downto 0);
signal onewire_read_p, pps_is_zero : std_logic;
signal pps_load_p : std_logic;
-- ext_sync
signal ext_sync, ext_sync_filt : std_logic;
-- chipscope
-- component chipscope_ila
......@@ -377,7 +378,7 @@ begin
-- counter of the number of rising edges
cmp_ext_sync_p_cnt:incr_counter
generic map(g_counter_lgth => 32) -- for the fastest macrocycle of 20ms, the counter
-- can keep counting for > 2.5 years
-- can keep counting for 2.7 years
port map
(clk_i => clk_i,
counter_incr_i => ext_sync_p,
......@@ -390,15 +391,13 @@ begin
---------------------------------------------------------------------------------------------------
-- MACROCYCLE COUNTER --
---------------------------------------------------------------------------------------------------
-- Regarding synchronisation, the masterFIP application can work in two modes:
-- using an internal counter that counts each macrocycle based on the local oscillator, or
-- using the ext_sync pulse to signal the beginning of each macrocycle. There is also the option
-- that when the external pulse does not arrive, the internal counter takes over the synchronisation.
-- In an application where the external synchronization pulse is expected for every macrocycle,
-- the macrocyc_lgth is set by the sw application slightly larger than the external synchronization
-- period; therefore the macrocycle counter should not be reaching zero; if it reaches zero,
-- it would mean that the external synchronization pulse did not arrive in time and a new
-- macrocycle (slightly longer) will start automatically based on this internal counter.
-- Regarding synchronisation, the masterFIP application can work in three modes:
-- 1) using an internal counter that counts each macrocycle based on the SPEC local oscillator;
-- this mode is active based on the state of the transceiver signal ext_sync_ctrl_oe_n_o.
-- 2) using the ext_sync pulse to signal the beginning of each macrocycle
-- 3) using the ext_sync pulse to signal the beginning of each macrocycle together with an input
-- from the processor indicating that all the periodic traffic has been completed and the processor
-- is ready to start a new macrocycle.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- counter counting the macrocycle time;
......@@ -415,13 +414,15 @@ begin
-- -- -- -- -- -- -- -- -- -- --
reg_to_mt.macrocyc_time_cnt_i <= macrocyc_cnt;
macrocyc_load_p <= macrocyc_cnt_zero_p or reg_from_mt.macrocyc_start_o or ext_sync_p;
macrocyc_load_p <= macrocyc_cnt_zero_p or reg_from_mt.macrocyc_start_o when reg_from_mt.ext_sync_ctrl_oe_n_o = '1' -- internal counting
else ext_sync_p when reg_from_mt.ext_sync_ctrl_oe_n_o = '0' and reg_from_mt.ext_sync_ctrl_opt_o = '0' -- pure external control
else ext_sync_p and reg_from_mt.ext_sync_ctrl_safe_wind_o; -- macrocycle restart, based on macrocycle execution
-- note: macrocyc_start_o is a monostable, 1-clk-tick-long pulse
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- counter counting the number of macrocycles;
-- being a 32-bit counter, for the fastest application of 20 ms macrocycle, the counter can
-- keep counting for 994 days; when it fills up it would restart from 0.
-- keep counting for 2.7 years; when it fills up it would restart from 0.
cmp_macrocycles_cnt:incr_counter
generic map(g_counter_lgth => g_width)
port map
......@@ -835,8 +836,8 @@ begin
leds_o(1) <= not reg_from_mt.led_rx_err_o;
leds_o(2) <= not reg_from_mt.led_tx_act_o;
leds_o(3) <= not reg_from_mt.led_tx_err_o;
leds_o(4) <= not reg_from_mt.led_ext_sync_act_o when reg_from_mt.led_ext_sync_used_o = '1' else '0';
leds_o(5) <= not reg_from_mt.led_ext_sync_err_o when reg_from_mt.led_ext_sync_used_o = '1' else '0';
leds_o(4) <= not reg_from_mt.led_ext_sync_act_o when reg_from_mt.ext_sync_ctrl_oe_n_o = '0' else '0';
leds_o(5) <= not reg_from_mt.led_ext_sync_err_o when reg_from_mt.ext_sync_ctrl_oe_n_o = '0' else '0';
leds_o(7 downto 6) <= "00"; -- not used
leds_o(31 downto 8) <= reg_from_mt.led_dbg_o;
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_csr.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 02/09/17 10:52:07
-- Created : 04/12/17 12:25:04
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
......@@ -45,7 +45,6 @@ signal masterfip_led_rx_act_int : std_logic ;
signal masterfip_led_rx_err_int : std_logic ;
signal masterfip_led_tx_act_int : std_logic ;
signal masterfip_led_tx_err_int : std_logic ;
signal masterfip_led_ext_sync_used_int : std_logic ;
signal masterfip_led_ext_sync_act_int : std_logic ;
signal masterfip_led_ext_sync_err_int : std_logic ;
signal masterfip_led_dbg_int : std_logic_vector(23 downto 0);
......@@ -53,6 +52,8 @@ signal masterfip_ext_sync_ctrl_term_en_int : std_logic ;
signal masterfip_ext_sync_ctrl_dir_int : std_logic ;
signal masterfip_ext_sync_ctrl_oe_n_int : std_logic ;
signal masterfip_ext_sync_ctrl_p_cnt_rst_int : std_logic ;
signal masterfip_ext_sync_ctrl_opt_int : std_logic ;
signal masterfip_ext_sync_ctrl_safe_wind_int : std_logic ;
signal masterfip_macrocyc_lgth_int : std_logic_vector(30 downto 0);
signal masterfip_macrocyc_start_dly0 : std_logic ;
signal masterfip_macrocyc_start_int : std_logic ;
......@@ -170,7 +171,6 @@ begin
masterfip_led_rx_err_int <= '0';
masterfip_led_tx_act_int <= '0';
masterfip_led_tx_err_int <= '0';
masterfip_led_ext_sync_used_int <= '0';
masterfip_led_ext_sync_act_int <= '0';
masterfip_led_ext_sync_err_int <= '0';
masterfip_led_dbg_int <= "000000000000000000000000";
......@@ -178,6 +178,8 @@ begin
masterfip_ext_sync_ctrl_dir_int <= '0';
masterfip_ext_sync_ctrl_oe_n_int <= '0';
masterfip_ext_sync_ctrl_p_cnt_rst_int <= '0';
masterfip_ext_sync_ctrl_opt_int <= '0';
masterfip_ext_sync_ctrl_safe_wind_int <= '0';
masterfip_macrocyc_lgth_int <= "0000000000000000000000000000000";
masterfip_macrocyc_start_int <= '0';
masterfip_turnar_lgth_int <= "0000000000000000000000000000000";
......@@ -329,19 +331,18 @@ begin
masterfip_led_rx_err_int <= wrdata_reg(1);
masterfip_led_tx_act_int <= wrdata_reg(2);
masterfip_led_tx_err_int <= wrdata_reg(3);
masterfip_led_ext_sync_used_int <= wrdata_reg(4);
masterfip_led_ext_sync_act_int <= wrdata_reg(5);
masterfip_led_ext_sync_err_int <= wrdata_reg(6);
masterfip_led_ext_sync_act_int <= wrdata_reg(4);
masterfip_led_ext_sync_err_int <= wrdata_reg(5);
masterfip_led_dbg_int <= wrdata_reg(31 downto 8);
end if;
rddata_reg(0) <= masterfip_led_rx_act_int;
rddata_reg(1) <= masterfip_led_rx_err_int;
rddata_reg(2) <= masterfip_led_tx_act_int;
rddata_reg(3) <= masterfip_led_tx_err_int;
rddata_reg(4) <= masterfip_led_ext_sync_used_int;
rddata_reg(5) <= masterfip_led_ext_sync_act_int;
rddata_reg(6) <= masterfip_led_ext_sync_err_int;
rddata_reg(4) <= masterfip_led_ext_sync_act_int;
rddata_reg(5) <= masterfip_led_ext_sync_err_int;
rddata_reg(31 downto 8) <= masterfip_led_dbg_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
......@@ -385,11 +386,15 @@ begin
masterfip_ext_sync_ctrl_dir_int <= wrdata_reg(1);
masterfip_ext_sync_ctrl_oe_n_int <= wrdata_reg(2);
masterfip_ext_sync_ctrl_p_cnt_rst_int <= wrdata_reg(8);
masterfip_ext_sync_ctrl_opt_int <= wrdata_reg(16);
masterfip_ext_sync_ctrl_safe_wind_int <= wrdata_reg(24);
end if;
rddata_reg(0) <= masterfip_ext_sync_ctrl_term_en_int;
rddata_reg(1) <= masterfip_ext_sync_ctrl_dir_int;
rddata_reg(2) <= masterfip_ext_sync_ctrl_oe_n_int;
rddata_reg(8) <= masterfip_ext_sync_ctrl_p_cnt_rst_int;
rddata_reg(16) <= masterfip_ext_sync_ctrl_opt_int;
rddata_reg(24) <= masterfip_ext_sync_ctrl_safe_wind_int;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
......@@ -402,7 +407,6 @@ begin
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
......@@ -410,7 +414,6 @@ begin
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
......@@ -1715,8 +1718,6 @@ begin
regs_o.led_tx_act_o <= masterfip_led_tx_act_int;
-- tx err red led
regs_o.led_tx_err_o <= masterfip_led_tx_err_int;
-- write 1 to indicate that the ext sync is used
regs_o.led_ext_sync_used_o <= masterfip_led_ext_sync_used_int;
-- ext sync act green led
regs_o.led_ext_sync_act_o <= masterfip_led_ext_sync_act_int;
-- ext sync err red led
......@@ -1734,6 +1735,10 @@ begin
regs_o.ext_sync_ctrl_oe_n_o <= masterfip_ext_sync_ctrl_oe_n_int;
-- pulses counter reset
regs_o.ext_sync_ctrl_p_cnt_rst_o <= masterfip_ext_sync_ctrl_p_cnt_rst_int;
-- counting options
regs_o.ext_sync_ctrl_opt_o <= masterfip_ext_sync_ctrl_opt_int;
-- safe window
regs_o.ext_sync_ctrl_safe_wind_o <= masterfip_ext_sync_ctrl_safe_wind_int;
-- ext_sync_p_cnt
-- WorldFIP speed, hard-wired on the FMC
-- macrocycle lgth
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 02/09/17 10:52:07
-- Created : 04/12/17 12:25:04
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
......@@ -216,7 +216,6 @@ package masterfip_wbgen2_pkg is
led_rx_err_o : std_logic;
led_tx_act_o : std_logic;
led_tx_err_o : std_logic;
led_ext_sync_used_o : std_logic;
led_ext_sync_act_o : std_logic;
led_ext_sync_err_o : std_logic;
led_dbg_o : std_logic_vector(23 downto 0);
......@@ -224,6 +223,8 @@ package masterfip_wbgen2_pkg is
ext_sync_ctrl_dir_o : std_logic;
ext_sync_ctrl_oe_n_o : std_logic;
ext_sync_ctrl_p_cnt_rst_o : std_logic;
ext_sync_ctrl_opt_o : std_logic;
ext_sync_ctrl_safe_wind_o : std_logic;
macrocyc_lgth_o : std_logic_vector(30 downto 0);
macrocyc_start_o : std_logic;
turnar_lgth_o : std_logic_vector(30 downto 0);
......@@ -311,7 +312,6 @@ package masterfip_wbgen2_pkg is
led_rx_err_o => '0',
led_tx_act_o => '0',
led_tx_err_o => '0',
led_ext_sync_used_o => '0',
led_ext_sync_act_o => '0',
led_ext_sync_err_o => '0',
led_dbg_o => (others => '0'),
......@@ -319,6 +319,8 @@ package masterfip_wbgen2_pkg is
ext_sync_ctrl_dir_o => '0',
ext_sync_ctrl_oe_n_o => '0',
ext_sync_ctrl_p_cnt_rst_o => '0',
ext_sync_ctrl_opt_o => '0',
ext_sync_ctrl_safe_wind_o => '0',
macrocyc_lgth_o => (others => '0'),
macrocyc_start_o => '0',
turnar_lgth_o => (others => '0'),
......
#!/bin/bash
wbgen2 -V master_wbgen2_csr.vhd -H record -p master_wbgen2_pkg.vhd -s defines -C master_wbgen2_csr.h -D master_wbgen2_csr.html master_csr.wb
echo ""
echo "Moving WB generated files to the following locations..."
echo ""
mv -v ./master_wbgen2_csr.vhd ../.
mv -v ./master_wbgen2_pkg.vhd ../.
......@@ -91,13 +91,6 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "write 1 to indicate that the ext sync is used";
prefix = "ext_sync_used";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "ext sync act green led";
prefix = "ext_sync_act";
......@@ -115,6 +108,7 @@ peripheral {
field {
name = "dbg";
prefix = "dbg";
description = "bit 8 is connected to TP3; bit 9 is connected to TP4";
size = 24;
align = 8;
type = SLV;
......@@ -203,9 +197,8 @@ peripheral {
field {
name = "transceiver output enable negative logic";
prefix = "oe_n";
description = "write 0: normal operation, the external sync pulse arrives to the FPGA\
write 1: the external sync pulse does not arrive to the FPGA\
WARNING: this bit is hard-wired in the HDL top to 0";
description = "write 0: normal operation, the external sync pulse arrives to the FPGA and controls the macrocycle counter\
write 1: the external sync pulse is disabled; the macrocycle counting is based on internal counters";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -219,7 +212,33 @@ peripheral {
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
field {
name = "counting options";
prefix = "opt";
description = "0: external pulse resets the macrocycle counter whenever it arrives\
1: external pulse resets the macrocycle counter, only when it arrives in a window as expected by the\
processor and the macrocycle configuration. In this option for example if a macrocycle is set at 20 ms\
but a pulse arrives every 10 ms by mistake, then one every 2 pulses will be ignored.\
Note that the ext_sync_p_cnt will be counting in any case all the incoming pulses, so the error will\
be reported, but the macrocycle will run smoothly at 20 ms";
type = BIT;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "safe window";
prefix = "safe_wind";
description = "0: processor busy with periodic traffic; reception of a new external pulse is NOT safe\
1: processor ready for a new external pulse; macrocycle periodic part has been played";
type = BIT;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
......@@ -229,7 +248,7 @@ peripheral {
field {
name = "ext_sync_p_cnt";
description = "number of ext sync pulses since the application startup OR a rst_core OR a ext_sync_p_cnt_rst;\
for the fastest macrocycle of 20ms, the counter can keep counting for up to >2.5 years.";
for the fastest macrocycle of 20ms, the counter can keep counting for up to 2.7 years.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -310,7 +329,7 @@ peripheral {
field {
name = "number of macrocycles";
description = "amount of macrocycles that have been counted since the application startup OR a rst_core;\
for the fastest macrocycle of 20ms, the counter can keep counting for up to >2.5 years.";
for the fastest macrocycle of 20ms, the counter can keep counting for up to 2.7 years.";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......
......@@ -3,7 +3,7 @@
* File : masterfip_wbgen2_csr.h
* Author : auto-generated by wbgen2 from masterfip_csr.wb
* Created : 02/09/17 10:52:07
* Created : 04/12/17 12:25:05
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
......@@ -55,14 +55,11 @@
/* definitions for field: tx err red led in reg: leds and debug */
#define MASTERFIP_LED_TX_ERR WBGEN2_GEN_MASK(3, 1)
/* definitions for field: write 1 to indicate that the ext sync is used in reg: leds and debug */
#define MASTERFIP_LED_EXT_SYNC_USED WBGEN2_GEN_MASK(4, 1)
/* definitions for field: ext sync act green led in reg: leds and debug */
#define MASTERFIP_LED_EXT_SYNC_ACT WBGEN2_GEN_MASK(5, 1)
#define MASTERFIP_LED_EXT_SYNC_ACT WBGEN2_GEN_MASK(4, 1)
/* definitions for field: ext sync err red led in reg: leds and debug */
#define MASTERFIP_LED_EXT_SYNC_ERR WBGEN2_GEN_MASK(6, 1)
#define MASTERFIP_LED_EXT_SYNC_ERR WBGEN2_GEN_MASK(5, 1)
/* definitions for field: dbg in reg: leds and debug */
#define MASTERFIP_LED_DBG_MASK WBGEN2_GEN_MASK(8, 24)
......@@ -90,6 +87,12 @@
/* definitions for field: pulses counter reset in reg: ext sync ctrl */
#define MASTERFIP_EXT_SYNC_CTRL_P_CNT_RST WBGEN2_GEN_MASK(8, 1)
/* definitions for field: counting options in reg: ext sync ctrl */
#define MASTERFIP_EXT_SYNC_CTRL_OPT WBGEN2_GEN_MASK(16, 1)
/* definitions for field: safe window in reg: ext sync ctrl */
#define MASTERFIP_EXT_SYNC_CTRL_SAFE_WIND WBGEN2_GEN_MASK(24, 1)
/* definitions for register: ext sync pulses cnt */
/* definitions for register: bus speed */
......
......@@ -3169,23 +3169,6 @@ masterfip_led_tx_err_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
masterfip_led_ext_sync_used_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
masterfip_led_ext_sync_act_o
......@@ -3489,6 +3472,40 @@ masterfip_ext_sync_ctrl_p_cnt_rst_o
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
masterfip_ext_sync_ctrl_opt_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
masterfip_ext_sync_ctrl_safe_wind_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
......@@ -12336,6 +12353,9 @@ DBG[7:0]
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
EXT_SYNC_ERR
</td>
......@@ -12343,9 +12363,6 @@ EXT_SYNC_ERR
EXT_SYNC_ACT
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
EXT_SYNC_USED
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TX_ERR
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
......@@ -12373,9 +12390,6 @@ TX_ACT
TX_ERR
</b>[<i>read/write</i>]: tx err red led
<li><b>
EXT_SYNC_USED
</b>[<i>read/write</i>]: write 1 to indicate that the ext sync is used
<li><b>
EXT_SYNC_ACT
</b>[<i>read/write</i>]: ext sync act green led
<li><b>
......@@ -12384,6 +12398,7 @@ EXT_SYNC_ERR
<li><b>
DBG
</b>[<i>read/write</i>]: dbg
<br>bit 8 is connected to TP3; bit 9 is connected to TP4
</ul>
<a name="DS1820_TEMPER"></a>
<h3><a name="sect_3_4">3.4. fmc temperature</a></h3>
......@@ -13250,8 +13265,8 @@ EXT_SYNC_CTRL
<td class="td_unused">
-
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
SAFE_WIND
</td>
</tr>
</table>
......@@ -13304,8 +13319,8 @@ EXT_SYNC_CTRL
<td class="td_unused">
-
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
OPT
</td>
</tr>
</table>
......@@ -13429,11 +13444,19 @@ DIR
<li><b>
OE_N
</b>[<i>read/write</i>]: transceiver output enable negative logic
<br>write 0: normal operation, the external sync pulse arrives to the FPGA<br> write 1: the external sync pulse does not arrive to the FPGA<br> WARNING: this bit is hard-wired in the HDL top to 0
<br>write 0: normal operation, the external sync pulse arrives to the FPGA and controls the macrocycle counter<br> write 1: the external sync pulse is disabled; the macrocycle counting is based on internal counters
<li><b>
P_CNT_RST
</b>[<i>read/write</i>]: pulses counter reset
<br>resets the pulses counter
<li><b>
OPT
</b>[<i>read/write</i>]: counting options
<br>0: external pulse resets the macrocycle counter whenever it arrives<br> 1: external pulse resets the macrocycle counter, only when it arrives in a window as expected by the<br> processor and the macrocycle configuration. In this option for example if a macrocycle is set at 20 ms<br> but a pulse arrives every 10 ms by mistake, then one every 2 pulses will be ignored.<br> Note that the ext_sync_p_cnt will be counting in any case all the incoming pulses, so the error will<br> be reported, but the macrocycle will run smoothly at 20 ms
<li><b>
SAFE_WIND
</b>[<i>read/write</i>]: safe window
<br>0: processor busy with periodic traffic; reception of a new external pulse is NOT safe<br> 1: processor ready for a new external pulse; macrocycle periodic part has been played
</ul>
<a name="EXT_SYNC_P_CNT"></a>
<h3><a name="sect_3_8">3.8. ext sync pulses cnt</a></h3>
......@@ -13691,7 +13714,7 @@ EXT_SYNC_P_CNT[7:0]
<li><b>
EXT_SYNC_P_CNT
</b>[<i>read-only</i>]: ext_sync_p_cnt
<br>number of ext sync pulses since the application startup OR a rst_core OR a ext_sync_p_cnt_rst;<br> for the fastest macrocycle of 20ms, the counter can keep counting for up to >2.5 years.
<br>number of ext sync pulses since the application startup OR a rst_core OR a ext_sync_p_cnt_rst;<br> for the fastest macrocycle of 20ms, the counter can keep counting for up to 2.7 years.
</ul>
<a name="SPEED"></a>
<h3><a name="sect_3_9">3.9. bus speed</a></h3>
......@@ -14727,7 +14750,7 @@ MACROCYC_NUM_CNT[7:0]
<li><b>
MACROCYC_NUM_CNT
</b>[<i>read-only</i>]: number of macrocycles
<br>amount of macrocycles that have been counted since the application startup OR a rst_core;<br> for the fastest macrocycle of 20ms, the counter can keep counting for up to >2.5 years.
<br>amount of macrocycles that have been counted since the application startup OR a rst_core;<br> for the fastest macrocycle of 20ms, the counter can keep counting for up to 2.7 years.
</ul>
<a name="TURNAR"></a>
<h3><a name="sect_3_13">3.13. turnaround lgth</a></h3>
......
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