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MasterFIP - Gateware
Commit 3de128f4 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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updated to latest MT core; changed ip_core branch; code cleanup

parent a6c43633
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.gitmodules
View file @ 3de128f4
[submodule "ip_cores/wr-node-core"]
path = ip_cores/wr-node-core
url = git://ohwr.org/white-rabbit/wr-node-core.git
[submodule "ip_cores/general-cores"]
path = ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
general-cores @ 9a40120b
Subproject commit 8915ade1685e0af62b93ff178ebbc2023c3edd09
Subproject commit 9a40120ba4af4a7551f9fd8cbbe61f1d434f30bf
wr-node-core @ c13bc43e
Subproject commit 57feacea81ddf573180b6694e06c428838142d6e
Subproject commit c13bc43e88febd74b5eaa9c5d85675d6b28671cd
rtl/fmc_masterFIP_core.vhd
View file @ 3de128f4
......@@ -154,7 +154,7 @@ entity fmc_masterFIP_core is
-- External synchronisation pulse transceiver
ext_sync_term_en_o : out std_logic; -- enable 50 Ohms termination of the pulse
ext_sync_dir_o : out std_logic; -- transceiver direction
ext_sync_oe_o : out std_logic; -- transceiver output enable
ext_sync_oe_n_o : out std_logic; -- transceiver output enable negative
ext_sync_tst_n_o : out std_logic; -- emulation of the LEMO input
ext_sync_i : in std_logic; -- sync pulse
......@@ -245,7 +245,8 @@ architecture rtl of fmc_masterFIP_core is
signal sync_led, out_of_sync_led : std_logic;
-- debug
signal mf_dbg : std_logic_vector(31 downto 0);
signal mf_dbg_p, mf_dbg_p_ext : std_logic;
signal mf_dbg_p, mf_dbg_p_ext, macrocyc_cnt_zero, macrocyc_cnt_twentyfive, macrocyc_cnt_twentyfive_p : std_logic;
-- chipscope
-- component chipscope_ila
......@@ -303,14 +304,6 @@ begin
adc_prim_conn_n_o <= '0' when reg_from_mt.adc_prim_conn_n_o = '0' else 'Z';
---------------------------------------------------------------------------------------------------
-- EXT SYNC PULSE --
---------------------------------------------------------------------------------------------------
ext_sync_tst_n_o <= '0' when reg_from_mt.ext_sync_tst_n_o = '0' else 'Z';
ext_sync_dir_o <= reg_from_mt.ext_sync_dir_o;
ext_sync_term_en_o <= reg_from_mt.ext_sync_term_en_o;
---------------------------------------------------------------------------------------------------
-- speed --
---------------------------------------------------------------------------------------------------
......@@ -341,6 +334,12 @@ begin
---------------------------------------------------------------------------------------------------
-- external sync --
---------------------------------------------------------------------------------------------------
ext_sync_tst_n_o <= '0' when reg_from_mt.ext_sync_tst_n_o = '0' else 'Z';
ext_sync_dir_o <= reg_from_mt.ext_sync_dir_o;
ext_sync_term_en_o <= reg_from_mt.ext_sync_term_en_o;
ext_sync_oe_n_o <= reg_from_mt.ext_sync_oe_n_o;
-- input synchronizer of the ext_sync_i signal
cmp_ext_sync_sync: gc_sync_ffs
port map
......@@ -750,7 +749,7 @@ begin
-- drivers. Note that a temperature reading is provided every second, with the first one a couple
-- of sec after the board power-up/ reset.
cmp_onewire: onewire_interf --gc_ds182x_interface
cmp_onewire: gc_ds182x_interface
generic map (freq => 100)
port map
(clk_i => clk_i,
......@@ -808,7 +807,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sync_led: gc_extend_pulse
generic map
(g_width => 1000000)
(g_width => 10000)--1000000
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
......@@ -816,16 +815,25 @@ begin
extended_o => sync_led);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_tmp_ext: gc_extend_pulse
generic map
(g_width => 10000)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => macrocyc_cnt_twentyfive_p,
extended_o => macrocyc_cnt_twentyfive);
macrocyc_cnt_twentyfive_p <= '1' when macrocyc_cnt = "0000000000000000000000000011001" else '0';
aux_o(7) <= out_of_sync_led;
aux_o(6) <= mf_dbg_p_ext;
aux_o(5) <= reg_from_mt.dbg_o(5);
aux_o(4) <= reg_from_mt.dbg_o(4); --rx_byte_ready_p;
aux_o(3) <= rx_fss_received_p;--mf_dbg(3); --macrocyc_cnt_zero_p;
aux_o(2) <= rx_frame_ok_p;--(2); --tx_completed;
aux_o(1) <= tx_completed_p;--mf_dbg(1);
aux_o(0) <= silen_load_p;--mf_dbg(0); --sync_led;
ext_sync_oe_o <= ext_sync_oe;
aux_o(3) <= ext_sync_p_cnt_rst;--mf_dbg(3); --macrocyc_cnt_zero_p;
aux_o(2) <= reg_from_mt.macrocyc_start_o;--(2); --tx_completed;
aux_o(1) <= macrocyc_cnt_twentyfive;--mf_dbg(1);
aux_o(0) <= sync_led;--mf_dbg(0); --sync_led;
---------------------------------------------------------------------------------------------------
......
rtl/fmc_masterfip_csr.vhd
View file @ 3de128f4
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fmc_masterfip_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
-- Created : 10/07/16 17:41:49
-- Created : 10/17/16 12:35:48
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
......@@ -52,7 +52,7 @@ signal mrfip_dac_config_load_dly0 : std_logic ;
signal mrfip_dac_config_load_int : std_logic ;
signal mrfip_ext_sync_term_en_int : std_logic ;
signal mrfip_ext_sync_dir_int : std_logic ;
signal mrfip_ext_sync_oe_int : std_logic ;
signal mrfip_ext_sync_oe_n_int : std_logic ;
signal mrfip_ext_sync_tst_n_int : std_logic ;
signal mrfip_ext_sync_p_cnt_rst_int : std_logic ;
signal mrfip_macrocyc_lgth_int : std_logic_vector(30 downto 0);
......@@ -178,7 +178,7 @@ begin
mrfip_dac_config_load_int <= '0';
mrfip_ext_sync_term_en_int <= '0';
mrfip_ext_sync_dir_int <= '0';
mrfip_ext_sync_oe_int <= '0';
mrfip_ext_sync_oe_n_int <= '0';
mrfip_ext_sync_tst_n_int <= '0';
mrfip_ext_sync_p_cnt_rst_int <= '0';
mrfip_macrocyc_lgth_int <= "0000000000000000000000000000000";
......@@ -438,13 +438,13 @@ begin
if (wb_we_i = '1') then
mrfip_ext_sync_term_en_int <= wrdata_reg(0);
mrfip_ext_sync_dir_int <= wrdata_reg(1);
mrfip_ext_sync_oe_int <= wrdata_reg(2);
mrfip_ext_sync_oe_n_int <= wrdata_reg(2);
mrfip_ext_sync_tst_n_int <= wrdata_reg(3);
mrfip_ext_sync_p_cnt_rst_int <= wrdata_reg(8);
end if;
rddata_reg(0) <= mrfip_ext_sync_term_en_int;
rddata_reg(1) <= mrfip_ext_sync_dir_int;
rddata_reg(2) <= mrfip_ext_sync_oe_int;
rddata_reg(2) <= mrfip_ext_sync_oe_n_int;
rddata_reg(3) <= mrfip_ext_sync_tst_n_int;
rddata_reg(8) <= mrfip_ext_sync_p_cnt_rst_int;
rddata_reg(4) <= 'X';
......@@ -1776,8 +1776,8 @@ begin
regs_o.ext_sync_term_en_o <= mrfip_ext_sync_term_en_int;
-- transceiver direction
regs_o.ext_sync_dir_o <= mrfip_ext_sync_dir_int;
-- transceiver output enable
regs_o.ext_sync_oe_o <= mrfip_ext_sync_oe_int;
-- transceiver output enable negative logic
regs_o.ext_sync_oe_n_o <= mrfip_ext_sync_oe_n_int;
-- test pulse
regs_o.ext_sync_tst_n_o <= mrfip_ext_sync_tst_n_int;
-- pulses counter reset
......
rtl/masterFIP_pkg.vhd
View file @ 3de128f4
......@@ -201,7 +201,7 @@ package masterFIP_pkg is
fd_txena_o : out std_logic;
ext_sync_term_en_o : out std_logic;
ext_sync_dir_o : out std_logic;
ext_sync_oe_o : out std_logic;
ext_sync_oe_n_o : out std_logic;
ext_sync_tst_n_o : out std_logic;
ext_sync_i : in std_logic;
adc_1v8_shdn_n_o : out std_logic;
......
rtl/mf_wbgen2_pkg.vhd
View file @ 3de128f4
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC masterFIP core registers
---------------------------------------------------------------------------------------
-- File : mf_wbgen2_pkg.vhd
-- File : fmc_masterfip_csr_pkg.vhd
-- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
-- Created : 10/07/16 17:41:49
-- Created : 10/17/16 12:35:48
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
......@@ -222,7 +222,7 @@ package mrfip_wbgen2_pkg is
dac_config_load_o : std_logic;
ext_sync_term_en_o : std_logic;
ext_sync_dir_o : std_logic;
ext_sync_oe_o : std_logic;
ext_sync_oe_n_o : std_logic;
ext_sync_tst_n_o : std_logic;
ext_sync_p_cnt_rst_o : std_logic;
macrocyc_lgth_o : std_logic_vector(30 downto 0);
......@@ -318,7 +318,7 @@ package mrfip_wbgen2_pkg is
dac_config_load_o => '0',
ext_sync_term_en_o => '0',
ext_sync_dir_o => '0',
ext_sync_oe_o => '0',
ext_sync_oe_n_o => '0',
ext_sync_tst_n_o => '0',
ext_sync_p_cnt_rst_o => '0',
macrocyc_lgth_o => (others => '0'),
......
rtl/wbgen/fmc_masterfip_csr.h
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rtl/wbgen/fmc_masterfip_csr.htm
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rtl/wbgen/fmc_masterfip_csr.wb
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syn/spec/spec_masterfip.xise
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syn/spec/tb_masterFIP.fdo
View file @ 3de128f4
######################################################################
##
## Filename: tb_masterFIP.fdo
## Created on: Tue Oct 04 14:18:34 W. Europe Daylight Time 2016
## Created on: Thu Oct 20 12:14:30 W. Europe Daylight Time 2016
##
## Auto generated by Project Navigator for Behavioral Simulation
##
......@@ -20,21 +20,19 @@ vlib work
#
# Compile sources
#
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_package.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_sync_register.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_package.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/dualram_512x8.vhd"
vcom -explicit -93 "../../rtl/mf_wbgen2_pkg.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_incr_counter.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_decr_counter.vhd"
vcom -explicit -93 "../../rtl/from_nanofip/wf_crc.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_incr_counter.vhd"
vlib nanoFIP_lib
......@@ -60,7 +58,7 @@ vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
vcom -explicit -93 "../../sim/spec/testbench/tb_package.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_tx_serializer.vhd"
......@@ -102,20 +100,19 @@ vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd"
vcom -explicit -93 "../../top/spec/synthesis_descriptor.vhd"
vcom -explicit -93 "../../top/spec/spec_reset_gen.vhd"
vcom -explicit -93 "../../sim/spec/testbench/wishbone_monitor.vhd"
vcom -explicit -93 "../../sim/spec/testbench/wishbone_interface.vhd"
vcom -explicit -93 "../../sim/spec/testbench/user_sequencer.vhd"
vcom -explicit -93 "../../sim/spec/testbench/user_config.vhd"
vcom -explicit -93 "../../sim/spec/testbench/user_access_monitor.vhd"
vcom -explicit -93 "../../sim/spec/testbench/slone_monitor.vhd"
vcom -explicit -93 "../../sim/spec/testbench/slone_interface.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_wb_controller.vhd"
vlib nanoFIP_lib
......@@ -139,7 +136,7 @@ vcom -explicit -93 "../../sim/spec/testbench/gnum_model/cmd_router1.vhd"
vcom -explicit -93 "../../rtl/fmc_masterFIP_core.vhd"
vcom -explicit -93 "../../rtl/carrier_info.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
vcom -explicit -93 "../../top/spec/spec_masterFIP.vhd"
vcom -explicit -93 "../../sim/spec/testbench/user_interface.vhd"
vlib nanoFIP_lib
......
syn/spec_mt/spec_masterfip_mt.xise
View file @ 3de128f4
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top/spec_mt/spec_masterfip_mt.ucf
View file @ 3de128f4
......@@ -178,9 +178,10 @@ NET "fmc_prsnt_m2c_l_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# FMC slot
#----------------------------------------
# <ucfgen_start>
# This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.
# ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 0
NET "mezz_onewire_b" LOC = "C18";
NET "mezz_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fd_rstn_o" LOC = "Y18";
NET "fd_rstn_o" IOSTANDARD = "LVCMOS25";
......@@ -220,8 +221,8 @@ NET "ext_sync_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_tst_n_o" LOC = U8;
NET "ext_sync_tst_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_oe_o" LOC = W6;
NET "ext_sync_oe_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_oe_n_o" LOC = W6;
NET "ext_sync_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_dir_o" LOC = Y6;
NET "ext_sync_dir_o" IOSTANDARD = "LVCMOS25";
......
top/spec_mt/spec_masterfip_mt.vhd
View file @ 3de128f4
......@@ -48,6 +48,7 @@ use work.spec_node_pkg.all;
use work.wrn_mqueue_pkg.all;
use work.wr_node_pkg.all;
use work.masterFIP_pkg.all;
use work.mrfip_wbgen2_pkg.all;
use work.gencores_pkg.all;
library unisim;
......@@ -104,10 +105,13 @@ entity spec_masterfip_mt is
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
-- Mezzanine 1-wire
mezz_onewire_b : inout std_logic;
-- WorldFIP external synchronisation pulse transceiver
ext_sync_term_en_o : out std_logic; -- enable 50 Ohms termination of the pulse
ext_sync_dir_o : out std_logic; -- transceiver direction
ext_sync_oe_o : out std_logic; -- transceiver output enable
ext_sync_oe_n_o : out std_logic; -- transceiver output enable
ext_sync_tst_n_o : out std_logic; -- emulation of the LEMO input
ext_sync_i : in std_logic; -- sync pulse
......@@ -321,7 +325,7 @@ begin
-- External Synch pulse
ext_sync_term_en_o => ext_sync_term_en_o,
ext_sync_dir_o => ext_sync_dir_o,
ext_sync_oe_o => ext_sync_oe_o,
ext_sync_oe_n_o => ext_sync_oe_n_o,
ext_sync_tst_n_o => ext_sync_tst_n_o,
ext_sync_i => ext_sync_i,
-- ADC relays and supplies
......@@ -334,6 +338,8 @@ begin
dac_cs_n_o => dac_cs_n_o,
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o,
-- Mezzanine one-wire
onewire_b => mezz_onewire_b,
-- WISHBONE interface with
wb_adr_i => fmc_wb_muxed_out.adr,
wb_dat_i => fmc_wb_muxed_out.dat,
......
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