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MasterFIP - Gateware
Commit 462ce06a authored by Evangelia Gousiou's avatar Evangelia Gousiou
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code cleanup; added more comments to .wb

parent 3c5faced
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rtl/fmc_masterFIP_core.vhd
View file @ 462ce06a
...@@ -126,6 +126,7 @@ use work.gencores_pkg.all; ...@@ -126,6 +126,7 @@ use work.gencores_pkg.all;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
use work.wrcore_pkg.all; use work.wrcore_pkg.all;
use work.genram_pkg.all; use work.genram_pkg.all;
use work.wf_package.all;
--================================================================================================= --=================================================================================================
...@@ -197,11 +198,8 @@ entity fmc_masterFIP_core is ...@@ -197,11 +198,8 @@ entity fmc_masterFIP_core is
architecture rtl of fmc_masterFIP_core is architecture rtl of fmc_masterFIP_core is
-- resets -- resets
constant c_RST_UNLOCK_VALUE : std_logic_vector(15 downto 0) := x"cafe"; signal rst_n, core_host_rst_p, core_rst, core_rst_n : std_logic;
signal rst_n, core_rst, core_rst_n : std_logic; signal fd_host_rst_p, fd_host_rst : std_logic;
signal core_rstn_tmp, fd_rstn_tmp, rstn_lock_wr, fd_host_rstn : std_logic;
signal core_host_rst, core_host_rstn : std_logic;
signal rstn_lock : std_logic_vector(15 downto 0);
-- config -- config
signal speed : std_logic_vector(1 downto 0); signal speed : std_logic_vector(1 downto 0);
-- ext pulse -- ext pulse
...@@ -233,8 +231,9 @@ architecture rtl of fmc_masterFIP_core is ...@@ -233,8 +231,9 @@ architecture rtl of fmc_masterFIP_core is
signal rx_ctrl_byte, rx_byte : std_logic_vector(7 downto 0); signal rx_ctrl_byte, rx_byte : std_logic_vector(7 downto 0);
signal rx_byte_index, rx_bytes_num : std_logic_vector(15 downto 0); signal rx_byte_index, rx_bytes_num : std_logic_vector(15 downto 0);
-- fd_wdgn, fd_txer -- fd_wdgn, fd_txer
signal fd_wdgn_tstamp, fd_txer_tstamp : std_logic_vector(30 downto 0); signal fd_wdg_tstamp, fd_txer_tstamp : std_logic_vector(30 downto 0);
signal fd_wdg, fd_wdgn_p,fd_txer,fd_txer_p, fd_txer_cnt_reinit : std_logic; signal fd_wdg_sync, fd_wdg, fd_wdg_act : std_logic;
signal fd_txer, fd_txer_p, fd_txer_cnt_reinit : std_logic;
signal fd_txer_cnt : std_logic_vector(31 downto 0); signal fd_txer_cnt : std_logic_vector(31 downto 0);
-- ADC -- ADC
signal adc_sec_conn_n, adc_prim_conn_n : std_logic; signal adc_sec_conn_n, adc_prim_conn_n : std_logic;
...@@ -295,10 +294,8 @@ begin ...@@ -295,10 +294,8 @@ begin
wb_ack_o => wb_ack_o, wb_ack_o => wb_ack_o,
wb_stall_o => wb_stall_o, wb_stall_o => wb_stall_o,
-- resets -- resets
mf_rstn_core_o => core_rstn_tmp, -- reset has to be confirmed with lock word mf_rstn_lock_o mf_rst_core_o => core_host_rst_p, -- 1-clk-tick-long pulse
mf_rstn_fd_o => fd_rstn_tmp, -- reset has to be confirmed with lock word mf_rstn_lock_o mf_rst_fd_o => fd_host_rst_p, -- 1-clk-tick-long pulse
mf_rstn_lock_o => rstn_lock,
mf_rstn_lock_wr_o => rstn_lock_wr,
--dbg --dbg
mf_dbg_o => mf_dbg, mf_dbg_o => mf_dbg,
-- adc supplies -- adc supplies
...@@ -316,7 +313,7 @@ begin ...@@ -316,7 +313,7 @@ begin
mf_ext_sync_p_cnt_i => ext_sync_p_cnt, mf_ext_sync_p_cnt_i => ext_sync_p_cnt,
-- DAC configuration -- DAC configuration
mf_dac_config_value_o => dac_value, mf_dac_config_value_o => dac_value,
mf_dac_config_load_o => dac_load, mf_dac_config_load_o => dac_load_p, -- 1-clk-tick-long pulse
-- bus speed -- bus speed
mf_speed_i(1) => speed_b1_i, mf_speed_i(1) => speed_b1_i,
mf_speed_i(0) => speed_b0_i, mf_speed_i(0) => speed_b0_i,
...@@ -325,29 +322,29 @@ begin ...@@ -325,29 +322,29 @@ begin
mf_macrocyc_num_cnt_i => num_of_macrocyc_cnt, mf_macrocyc_num_cnt_i => num_of_macrocyc_cnt,
mf_turnar_lgth_o => turnar_lgth, mf_turnar_lgth_o => turnar_lgth,
mf_silen_lgth_o => silen_lgth, mf_silen_lgth_o => silen_lgth,
mf_macrocyc_start_o => macrocyc_host_load, -- optional counters loading through the host mf_macrocyc_start_o => macrocyc_host_load_p, -- 1-clk-tick-long pulse
mf_turnar_start_o => turnar_host_load, mf_turnar_start_o => turnar_host_load_p, -- 1-clk-tick-long pulse
mf_silen_start_o => silen_host_load, mf_silen_start_o => silen_host_load_p, -- 1-clk-tick-long pulse
-- counters inputs -- counters inputs
mf_macrocyc_time_cnt_i => macrocyc_cnt, mf_macrocyc_time_cnt_i => macrocyc_cnt,
mf_turnar_time_cnt_i => turnar_cnt, mf_turnar_time_cnt_i => turnar_cnt,
mf_silen_time_cnt_i => silen_cnt, mf_silen_time_cnt_i => silen_cnt,
-- tx control -- tx control
mf_tx_ctrl_rst_o => tx_host_rst, -- tx rst; then converted to 1-tick-long pulse mf_tx_ctrl_rst_o => tx_host_rst_p, -- 1-clk-tick-long pulse
mf_tx_ctrl_start_o => tx_start, -- tx start serializing a frame; then converted to 1-tick-long pulse mf_tx_ctrl_start_o => tx_start_p, -- 1-clk-tick-long pulse; tx start serializing a frame
mf_tx_ctrl_bytes_num_o => tx_bytes_num, -- number of bytes to serialize; sampled upon tx_start mf_tx_ctrl_bytes_num_o => tx_bytes_num, -- number of bytes to serialize; sampled upon tx_start
-- tx status -- tx status
mf_tx_stat_stop_i => tx_completed, -- 16x10ns long pulse upon the end of delivery of a frame mf_tx_stat_stop_i => tx_completed, -- stays active until a tx_rst or core_rst or tx_start_p
mf_tx_stat_curr_byte_indx_i => tx_byte_index, -- index of current byte being serialized mf_tx_stat_curr_byte_indx_i => tx_byte_index, -- index of current byte being serialized
mf_tx_stat_ena_i => fd_txena, -- FIELDRIVE txena, signal generated by the tx_serializer mf_tx_stat_ena_i => fd_txena, -- FIELDRIVE txena, signal generated by the tx_serializer
-- fd_wdgn -- fd_wdgn
mf_fd_wdgn_tstamp_i => fd_wdgn_tstamp, mf_fd_wdgn_tstamp_i => fd_wdg_tstamp,
mf_fd_wdgn_act_i => fd_wdg, mf_fd_wdgn_act_i => fd_wdg,
-- fd_txer -- fd_txer
mf_fd_txer_cnt_i => fd_txer_cnt, mf_fd_txer_cnt_i => fd_txer_cnt,
mf_fd_txer_tstamp_i => fd_txer_tstamp, mf_fd_txer_tstamp_i => fd_txer_tstamp,
-- rx control -- rx control
mf_rx_ctrl_rst_o => rx_host_rst, -- note: this is not a pulse mf_rx_ctrl_rst_o => rx_host_rst_p, -- 1-clk-tick-long pulse
-- rx status -- rx status
mf_rx_stat_pream_ok_i => rx_fss_received, mf_rx_stat_pream_ok_i => rx_fss_received,
mf_rx_stat_frame_ok_i => rx_frame_ok, mf_rx_stat_frame_ok_i => rx_frame_ok,
...@@ -503,30 +500,23 @@ begin ...@@ -503,30 +500,23 @@ begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- resets -- -- resets --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
rst_n <= not rst_i; rst_n <= not rst_i;
core_rst <= core_host_rst_p or rst_i; -- combination of PoR, PCIe reset, reset from WRNC
core_rst_n <= not core_rst;
speed <= speed_b1_i & speed_b0_i;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- reset generation -- FIELDRIVE reset generation
p_host_reset : process(clk_i) cmp_fd_rst_generate: gc_extend_pulse
begin generic map (g_width => 6400)--c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(speed)))) -- reset duration: 2 WorldFIP-tick-cycles of the lowest speed 31.25Kbps
if rising_edge(clk_i) then port map
if(rst_n = '0') then (clk_i => clk_i,
core_host_rstn <= '0'; rst_n_i => core_rst_n,
fd_host_rstn <= '0'; pulse_i => fd_host_rst_p,
else extended_o => fd_host_rst);
-- protection against accidental write -- -- -- -- -- -- -- -- -- -- --
if(rstn_lock_wr = '1' and rstn_lock = c_RST_UNLOCK_VALUE) then fd_rstn_o <= not fd_host_rst;
core_host_rstn <= core_rstn_tmp;
fd_host_rstn <= fd_rstn_tmp;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- --
core_host_rst <= not core_host_rstn;
fd_rstn_o <= fd_host_rstn;
core_rst <= core_host_rst or rst_i; -- combination of PoR, PCIe reset, reset from WRNC
core_rst_n <= not core_rst;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -596,15 +586,6 @@ begin ...@@ -596,15 +586,6 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
macrocyc_load_p <= macrocyc_cnt_zero_p or macrocyc_host_load_p or ext_sync_p; macrocyc_load_p <= macrocyc_cnt_zero_p or macrocyc_host_load_p or ext_sync_p;
-- edge detection of the macrocyc_host_load signal
cmp_macrocyc_host_load_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => macrocyc_host_load,
ppulse_o => macrocyc_host_load_p);
-- counter counting the number of macrocycles; when it fills up it restarts -- counter counting the number of macrocycles; when it fills up it restarts
cmp_macrocycles_cnt:incr_counter cmp_macrocycles_cnt:incr_counter
generic map(g_counter_lgth => 32) generic map(g_counter_lgth => 32)
...@@ -634,15 +615,6 @@ begin ...@@ -634,15 +615,6 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
turnar_load_p <= tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or turnar_host_load_p; turnar_load_p <= tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or turnar_host_load_p;
-- edge detection of the turnar_host_load signal
cmp_turnar_host_load_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => turnar_host_load,
ppulse_o => turnar_host_load_p);
-------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------
-- silence counter -- -- silence counter --
...@@ -662,42 +634,11 @@ begin ...@@ -662,42 +634,11 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
silen_load_p <= tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or silen_host_load_p; silen_load_p <= tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or silen_host_load_p;
-- edge detection of the silen_host_load signal
cmp_silen_host_load_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => silen_host_load,
ppulse_o => silen_host_load_p);
--------------------------------------------------------------------------------------------------
-- signals for tx --
--------------------------------------------------------------------------------------------------
-- edge detection on the tx_start signal
cmp_tx_start_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => tx_start,
ppulse_o => tx_start_p);
-------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------
-- signals for rx -- -- signals for rx --
-------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------
-- edge detection on the rx_host_rst signal rx_rst <= rx_host_rst_p or fd_txena;
cmp_rx_host_rst_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
rst_n_i => rst_n,
data_i => rx_host_rst,
ppulse_o => rx_host_rst_p);
-- -- -- -- -- -- -- -- -- -- --
rx_rst <= rx_host_rst_p or fd_txena;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- registering the number of received bytes -- registering the number of received bytes
...@@ -768,9 +709,6 @@ begin ...@@ -768,9 +709,6 @@ begin
rx_crc_wrong_p_o => rx_crc_wrong_p); rx_crc_wrong_p_o => rx_crc_wrong_p);
------------------------------------------------------------- -------------------------------------------------------------
speed <= speed_b1_i & speed_b0_i;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- tx -- -- tx --
...@@ -815,16 +753,6 @@ begin ...@@ -815,16 +753,6 @@ begin
-------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------
-- signals for tx -- -- signals for tx --
-------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------
-- edge detection on the tx_host_rst signal
cmp_tx_host_rst_pulse_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map
(clk_i => clk_i,
rst_n_i => rst_n,
data_i => tx_host_rst,
ppulse_o => tx_host_rst_p);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- extending the tx_completed_p until a core_rst or rx_rst is received -- extending the tx_completed_p until a core_rst or rx_rst is received
p_tx_completed_extend : process(clk_i) p_tx_completed_extend : process(clk_i)
begin begin
...@@ -844,26 +772,29 @@ begin ...@@ -844,26 +772,29 @@ begin
-- FielDrive TXERR, WDGN -- -- FielDrive TXERR, WDGN --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- edge detection on the fd_wdgn_i signal -- synchronisation of the fd_wdgn_i signal
cmp_fd_wdgn_i_pulse_detect: gc_sync_ffs cmp_fd_wdgn_i_pulse_detect: gc_sync_ffs
generic map(g_sync_edge => "negative") generic map(g_sync_edge => "positive")
port map port map
(clk_i => clk_i, (clk_i => clk_i,
rst_n_i => rst_n, rst_n_i => rst_n,
data_i => fd_wdgn_i, data_i => fd_wdg,
ppulse_o => fd_wdgn_p); synced_o => fd_wdg_sync);
fd_wdg <= not fd_wdgn_i;
-- process that registers the macrocycle_cnt value upon the last fd_wdgn_p of a macrocycle -- process that registers the activation of fd_wdgn_i and the macrocycle_cnt upon the activation;
-- the signals are reset upon a core_rst_n or a fd_host_rstn
p_fd_wdgn_capture : process(clk_i) p_fd_wdgn_capture : process(clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if(core_rst_n = '0' or macrocyc_load_p = '1' or fd_host_rstn = '0') then if(core_rst = '1' or fd_host_rst = '1') then
fd_wdg <= '0'; fd_wdg_act <= '0';
fd_wdgn_tstamp <= macrocyc_cnt; fd_wdg_tstamp <= macrocyc_cnt;
else else
if fd_wdgn_p = '1' then if fd_wdg_sync = '1' then
fd_wdg <= '1'; fd_wdg_act <= '1';
fd_wdgn_tstamp <= macrocyc_cnt; fd_wdg_tstamp <= macrocyc_cnt;
end if; end if;
end if; end if;
end if; end if;
...@@ -872,7 +803,7 @@ begin ...@@ -872,7 +803,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- edge detection on the fd_txer_i signal -- edge detection on the fd_txer_i signal
cmp_fd_txer_i_pulse_detect: gc_sync_ffs cmp_fd_txer_i_pulse_detect: gc_sync_ffs
generic map(g_sync_edge => "negative") generic map(g_sync_edge => "positive")
port map port map
(clk_i => clk_i, (clk_i => clk_i,
rst_n_i => rst_n, rst_n_i => rst_n,
...@@ -880,7 +811,7 @@ begin ...@@ -880,7 +811,7 @@ begin
ppulse_o => fd_txer_p); ppulse_o => fd_txer_p);
-- counter counting the number of fd_wdgn_p -- counter counting the number of fd_wdgn_p
cmp_fd_wdgn_cnt:incr_counter cmp_fd_txer_cnt:incr_counter
generic map(g_counter_lgth => 32) generic map(g_counter_lgth => 32)
port map port map
(clk_i => clk_i, (clk_i => clk_i,
...@@ -889,14 +820,14 @@ begin ...@@ -889,14 +820,14 @@ begin
counter_is_full_o => open, counter_is_full_o => open,
counter_o => fd_txer_cnt); counter_o => fd_txer_cnt);
fd_txer_cnt_reinit <= '1' when core_rst_n = '0' or macrocyc_load_p = '1' or fd_host_rstn = '0' fd_txer_cnt_reinit <= '1' when core_rst_n = '0' or macrocyc_load_p = '1' or fd_host_rst = '1'
else '0'; else '0';
-- process that registers the macrocycle_cnt value upon the last fd_txer_p of a macrocycle -- process that registers the macrocycle_cnt value upon the last fd_txer_p of a macrocycle
p_fd_txer_capture : process(clk_i) p_fd_txer_capture : process(clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if(core_rst_n = '0' or macrocyc_load_p = '1' or fd_host_rstn = '0') then if(core_rst_n = '0' or macrocyc_load_p = '1' or fd_host_rst = '1') then
fd_txer <= '1'; fd_txer <= '1';
fd_txer_tstamp <= macrocyc_cnt; fd_txer_tstamp <= macrocyc_cnt;
else else
...@@ -929,15 +860,6 @@ begin ...@@ -929,15 +860,6 @@ begin
dac_sclk_o => dac_sclk_o, dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o); dac_din_o => dac_din_o);
-- edge detection on the dac_value signal
cmp_dac_value_pulse_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => dac_load,
ppulse_o => dac_load_p);
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- LEDs -- -- LEDs --
......
rtl/fmc_masterfip_csr.vhd
View file @ 462ce06a
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : fmc_masterfip_csr.vhd -- File : fmc_masterfip_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb -- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
-- Created : 03/14/16 12:32:54 -- Created : 03/17/16 18:51:54
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
...@@ -27,13 +27,10 @@ entity fmc_masterfip_csr is ...@@ -27,13 +27,10 @@ entity fmc_masterfip_csr is
wb_we_i : in std_logic; wb_we_i : in std_logic;
wb_ack_o : out std_logic; wb_ack_o : out std_logic;
wb_stall_o : out std_logic; wb_stall_o : out std_logic;
-- Port for BIT field: 'reset of the masterFIP core' in reg: 'rstn' -- Port for MONOSTABLE field: 'reset of the masterFIP core' in reg: 'rst'
mf_rstn_core_o : out std_logic; mf_rst_core_o : out std_logic;
-- Port for BIT field: 'reset of the fieldrive chip (FD_RSTN)' in reg: 'rstn' -- Port for MONOSTABLE field: 'reset of the fieldrive chip' in reg: 'rst'
mf_rstn_fd_o : out std_logic; mf_rst_fd_o : out std_logic;
-- Ports for PASS_THROUGH field: 'reset magic value' in reg: 'rstn'
mf_rstn_lock_o : out std_logic_vector(15 downto 0);
mf_rstn_lock_wr_o : out std_logic;
-- Port for std_logic_vector field: 'debugging' in reg: 'dbg' -- Port for std_logic_vector field: 'debugging' in reg: 'dbg'
mf_dbg_o : out std_logic_vector(31 downto 0); mf_dbg_o : out std_logic_vector(31 downto 0);
-- Port for BIT field: '1v8_shdn_n' in reg: 'adc' -- Port for BIT field: '1v8_shdn_n' in reg: 'adc'
...@@ -48,7 +45,7 @@ entity fmc_masterfip_csr is ...@@ -48,7 +45,7 @@ entity fmc_masterfip_csr is
mf_adc_sec_conn_n_o : out std_logic; mf_adc_sec_conn_n_o : out std_logic;
-- Port for std_logic_vector field: 'value' in reg: 'dac' -- Port for std_logic_vector field: 'value' in reg: 'dac'
mf_dac_config_value_o : out std_logic_vector(15 downto 0); mf_dac_config_value_o : out std_logic_vector(15 downto 0);
-- Port for BIT field: 'load' in reg: 'dac' -- Port for MONOSTABLE field: 'load' in reg: 'dac'
mf_dac_config_load_o : out std_logic; mf_dac_config_load_o : out std_logic;
-- Port for BIT field: 'termination enable' in reg: 'ext sync' -- Port for BIT field: 'termination enable' in reg: 'ext sync'
mf_ext_sync_term_en_o : out std_logic; mf_ext_sync_term_en_o : out std_logic;
...@@ -66,15 +63,15 @@ entity fmc_masterfip_csr is ...@@ -66,15 +63,15 @@ entity fmc_masterfip_csr is
mf_speed_i : in std_logic_vector(1 downto 0); mf_speed_i : in std_logic_vector(1 downto 0);
-- Port for std_logic_vector field: 'macrocycle lgth' in reg: 'macrocycle lgth' -- Port for std_logic_vector field: 'macrocycle lgth' in reg: 'macrocycle lgth'
mf_macrocyc_lgth_o : out std_logic_vector(30 downto 0); mf_macrocyc_lgth_o : out std_logic_vector(30 downto 0);
-- Port for BIT field: 'macrocycle cnt start' in reg: 'macrocycle lgth' -- Port for MONOSTABLE field: 'macrocycle cnt start' in reg: 'macrocycle lgth'
mf_macrocyc_start_o : out std_logic; mf_macrocyc_start_o : out std_logic;
-- Port for std_logic_vector field: 'turnaround time' in reg: 'turnaround lgth' -- Port for std_logic_vector field: 'turnaround time' in reg: 'turnaround lgth'
mf_turnar_lgth_o : out std_logic_vector(30 downto 0); mf_turnar_lgth_o : out std_logic_vector(30 downto 0);
-- Port for BIT field: 'turnaround cnt start' in reg: 'turnaround lgth' -- Port for MONOSTABLE field: 'turnaround cnt start' in reg: 'turnaround lgth'
mf_turnar_start_o : out std_logic; mf_turnar_start_o : out std_logic;
-- Port for std_logic_vector field: 'silence time' in reg: 'silence lgth' -- Port for std_logic_vector field: 'silence time' in reg: 'silence lgth'
mf_silen_lgth_o : out std_logic_vector(30 downto 0); mf_silen_lgth_o : out std_logic_vector(30 downto 0);
-- Port for BIT field: 'silence cnt start' in reg: 'silence lgth' -- Port for MONOSTABLE field: 'silence cnt start' in reg: 'silence lgth'
mf_silen_start_o : out std_logic; mf_silen_start_o : out std_logic;
-- Port for std_logic_vector field: 'macrocycle time counter' in reg: 'macrocycle time cnt' -- Port for std_logic_vector field: 'macrocycle time counter' in reg: 'macrocycle time cnt'
mf_macrocyc_time_cnt_i : in std_logic_vector(30 downto 0); mf_macrocyc_time_cnt_i : in std_logic_vector(30 downto 0);
...@@ -84,9 +81,9 @@ entity fmc_masterfip_csr is ...@@ -84,9 +81,9 @@ entity fmc_masterfip_csr is
mf_turnar_time_cnt_i : in std_logic_vector(30 downto 0); mf_turnar_time_cnt_i : in std_logic_vector(30 downto 0);
-- Port for std_logic_vector field: 'silence time counter' in reg: 'silence time cnt' -- Port for std_logic_vector field: 'silence time counter' in reg: 'silence time cnt'
mf_silen_time_cnt_i : in std_logic_vector(30 downto 0); mf_silen_time_cnt_i : in std_logic_vector(30 downto 0);
-- Port for BIT field: 'tx rst' in reg: 'tx ctrl' -- Port for MONOSTABLE field: 'tx rst' in reg: 'tx ctrl'
mf_tx_ctrl_rst_o : out std_logic; mf_tx_ctrl_rst_o : out std_logic;
-- Port for BIT field: 'tx strt' in reg: 'tx ctrl' -- Port for MONOSTABLE field: 'tx strt' in reg: 'tx ctrl'
mf_tx_ctrl_start_o : out std_logic; mf_tx_ctrl_start_o : out std_logic;
-- Port for std_logic_vector field: 'tx number of bytes' in reg: 'tx ctrl' -- Port for std_logic_vector field: 'tx number of bytes' in reg: 'tx ctrl'
mf_tx_ctrl_bytes_num_o : out std_logic_vector(15 downto 0); mf_tx_ctrl_bytes_num_o : out std_logic_vector(15 downto 0);
...@@ -104,7 +101,7 @@ entity fmc_masterfip_csr is ...@@ -104,7 +101,7 @@ entity fmc_masterfip_csr is
mf_fd_txer_cnt_i : in std_logic_vector(31 downto 0); mf_fd_txer_cnt_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'fd_txer_tstamp' in reg: 'fieldrive txer tstamp' -- Port for std_logic_vector field: 'fd_txer_tstamp' in reg: 'fieldrive txer tstamp'
mf_fd_txer_tstamp_i : in std_logic_vector(30 downto 0); mf_fd_txer_tstamp_i : in std_logic_vector(30 downto 0);
-- Port for BIT field: 'rx rst' in reg: 'rx ctrl' -- Port for MONOSTABLE field: 'rx rst' in reg: 'rx ctrl'
mf_rx_ctrl_rst_o : out std_logic; mf_rx_ctrl_rst_o : out std_logic;
-- Port for BIT field: 'rx preamble detected' in reg: 'rx status' -- Port for BIT field: 'rx preamble detected' in reg: 'rx status'
mf_rx_stat_pream_ok_i : in std_logic; mf_rx_stat_pream_ok_i : in std_logic;
...@@ -393,8 +390,10 @@ end fmc_masterfip_csr; ...@@ -393,8 +390,10 @@ end fmc_masterfip_csr;
architecture syn of fmc_masterfip_csr is architecture syn of fmc_masterfip_csr is
signal mf_rstn_core_int : std_logic ; signal mf_rst_core_dly0 : std_logic ;
signal mf_rstn_fd_int : std_logic ; signal mf_rst_core_int : std_logic ;
signal mf_rst_fd_dly0 : std_logic ;
signal mf_rst_fd_int : std_logic ;
signal mf_dbg_int : std_logic_vector(31 downto 0); signal mf_dbg_int : std_logic_vector(31 downto 0);
signal mf_adc_1v8_shdn_n_int : std_logic ; signal mf_adc_1v8_shdn_n_int : std_logic ;
signal mf_adc_m5v_shdn_n_int : std_logic ; signal mf_adc_m5v_shdn_n_int : std_logic ;
...@@ -402,6 +401,7 @@ signal mf_adc_5v_en_n_int : std_logic ; ...@@ -402,6 +401,7 @@ signal mf_adc_5v_en_n_int : std_logic ;
signal mf_adc_prim_conn_n_int : std_logic ; signal mf_adc_prim_conn_n_int : std_logic ;
signal mf_adc_sec_conn_n_int : std_logic ; signal mf_adc_sec_conn_n_int : std_logic ;
signal mf_dac_config_value_int : std_logic_vector(15 downto 0); signal mf_dac_config_value_int : std_logic_vector(15 downto 0);
signal mf_dac_config_load_dly0 : std_logic ;
signal mf_dac_config_load_int : std_logic ; signal mf_dac_config_load_int : std_logic ;
signal mf_ext_sync_term_en_int : std_logic ; signal mf_ext_sync_term_en_int : std_logic ;
signal mf_ext_sync_dir_int : std_logic ; signal mf_ext_sync_dir_int : std_logic ;
...@@ -409,14 +409,20 @@ signal mf_ext_sync_oe_int : std_logic ; ...@@ -409,14 +409,20 @@ signal mf_ext_sync_oe_int : std_logic ;
signal mf_ext_sync_tst_n_int : std_logic ; signal mf_ext_sync_tst_n_int : std_logic ;
signal mf_ext_sync_p_cnt_rst_int : std_logic ; signal mf_ext_sync_p_cnt_rst_int : std_logic ;
signal mf_macrocyc_lgth_int : std_logic_vector(30 downto 0); signal mf_macrocyc_lgth_int : std_logic_vector(30 downto 0);
signal mf_macrocyc_start_dly0 : std_logic ;
signal mf_macrocyc_start_int : std_logic ; signal mf_macrocyc_start_int : std_logic ;
signal mf_turnar_lgth_int : std_logic_vector(30 downto 0); signal mf_turnar_lgth_int : std_logic_vector(30 downto 0);
signal mf_turnar_start_dly0 : std_logic ;
signal mf_turnar_start_int : std_logic ; signal mf_turnar_start_int : std_logic ;
signal mf_silen_lgth_int : std_logic_vector(30 downto 0); signal mf_silen_lgth_int : std_logic_vector(30 downto 0);
signal mf_silen_start_dly0 : std_logic ;
signal mf_silen_start_int : std_logic ; signal mf_silen_start_int : std_logic ;
signal mf_tx_ctrl_rst_dly0 : std_logic ;
signal mf_tx_ctrl_rst_int : std_logic ; signal mf_tx_ctrl_rst_int : std_logic ;
signal mf_tx_ctrl_start_dly0 : std_logic ;
signal mf_tx_ctrl_start_int : std_logic ; signal mf_tx_ctrl_start_int : std_logic ;
signal mf_tx_ctrl_bytes_num_int : std_logic_vector(15 downto 0); signal mf_tx_ctrl_bytes_num_int : std_logic_vector(15 downto 0);
signal mf_rx_ctrl_rst_dly0 : std_logic ;
signal mf_rx_ctrl_rst_int : std_logic ; signal mf_rx_ctrl_rst_int : std_logic ;
signal mf_tx_data_ctrl_int : std_logic_vector(7 downto 0); signal mf_tx_data_ctrl_int : std_logic_vector(7 downto 0);
signal mf_tx_data_reg1_int : std_logic_vector(31 downto 0); signal mf_tx_data_reg1_int : std_logic_vector(31 downto 0);
...@@ -513,9 +519,8 @@ begin ...@@ -513,9 +519,8 @@ begin
ack_sreg <= "0000000000"; ack_sreg <= "0000000000";
ack_in_progress <= '0'; ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000"; rddata_reg <= "00000000000000000000000000000000";
mf_rstn_core_int <= '0'; mf_rst_core_int <= '0';
mf_rstn_fd_int <= '0'; mf_rst_fd_int <= '0';
mf_rstn_lock_wr_o <= '0';
mf_dbg_int <= "00000000000000000000000000000000"; mf_dbg_int <= "00000000000000000000000000000000";
mf_adc_1v8_shdn_n_int <= '0'; mf_adc_1v8_shdn_n_int <= '0';
mf_adc_m5v_shdn_n_int <= '0'; mf_adc_m5v_shdn_n_int <= '0';
...@@ -613,22 +618,30 @@ begin ...@@ -613,22 +618,30 @@ begin
ack_sreg(9) <= '0'; ack_sreg(9) <= '0';
if (ack_in_progress = '1') then if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then if (ack_sreg(0) = '1') then
mf_rstn_lock_wr_o <= '0'; mf_rst_core_int <= '0';
mf_rst_fd_int <= '0';
mf_dac_config_load_int <= '0';
mf_macrocyc_start_int <= '0';
mf_turnar_start_int <= '0';
mf_silen_start_int <= '0';
mf_tx_ctrl_rst_int <= '0';
mf_tx_ctrl_start_int <= '0';
mf_rx_ctrl_rst_int <= '0';
ack_in_progress <= '0'; ack_in_progress <= '0';
else else
mf_rstn_lock_wr_o <= '0';
end if; end if;
else else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(7 downto 0) is case rwaddr_reg(7 downto 0) is
when "00000000" => when "00000000" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
mf_rstn_core_int <= wrdata_reg(0); mf_rst_core_int <= wrdata_reg(0);
mf_rstn_fd_int <= wrdata_reg(1); mf_rst_fd_int <= wrdata_reg(1);
mf_rstn_lock_wr_o <= '1';
end if; end if;
rddata_reg(0) <= mf_rstn_core_int; rddata_reg(0) <= '0';
rddata_reg(1) <= mf_rstn_fd_int; rddata_reg(1) <= '0';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X'; rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X'; rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X'; rddata_reg(4) <= 'X';
...@@ -659,7 +672,7 @@ begin ...@@ -659,7 +672,7 @@ begin
rddata_reg(29) <= 'X'; rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X'; rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(2) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00000001" => when "00000001" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
...@@ -722,7 +735,7 @@ begin ...@@ -722,7 +735,7 @@ begin
mf_dac_config_load_int <= wrdata_reg(16); mf_dac_config_load_int <= wrdata_reg(16);
end if; end if;
rddata_reg(15 downto 0) <= mf_dac_config_value_int; rddata_reg(15 downto 0) <= mf_dac_config_value_int;
rddata_reg(16) <= mf_dac_config_load_int; rddata_reg(16) <= '0';
rddata_reg(17) <= 'X'; rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X'; rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X'; rddata_reg(19) <= 'X';
...@@ -738,7 +751,7 @@ begin ...@@ -738,7 +751,7 @@ begin
rddata_reg(29) <= 'X'; rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X'; rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(2) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00000101" => when "00000101" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
...@@ -830,8 +843,8 @@ begin ...@@ -830,8 +843,8 @@ begin
mf_macrocyc_start_int <= wrdata_reg(31); mf_macrocyc_start_int <= wrdata_reg(31);
end if; end if;
rddata_reg(30 downto 0) <= mf_macrocyc_lgth_int; rddata_reg(30 downto 0) <= mf_macrocyc_lgth_int;
rddata_reg(31) <= mf_macrocyc_start_int; rddata_reg(31) <= '0';
ack_sreg(0) <= '1'; ack_sreg(2) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00001001" => when "00001001" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
...@@ -839,8 +852,8 @@ begin ...@@ -839,8 +852,8 @@ begin
mf_turnar_start_int <= wrdata_reg(31); mf_turnar_start_int <= wrdata_reg(31);
end if; end if;
rddata_reg(30 downto 0) <= mf_turnar_lgth_int; rddata_reg(30 downto 0) <= mf_turnar_lgth_int;
rddata_reg(31) <= mf_turnar_start_int; rddata_reg(31) <= '0';
ack_sreg(0) <= '1'; ack_sreg(2) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00001010" => when "00001010" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
...@@ -848,8 +861,8 @@ begin ...@@ -848,8 +861,8 @@ begin
mf_silen_start_int <= wrdata_reg(31); mf_silen_start_int <= wrdata_reg(31);
end if; end if;
rddata_reg(30 downto 0) <= mf_silen_lgth_int; rddata_reg(30 downto 0) <= mf_silen_lgth_int;
rddata_reg(31) <= mf_silen_start_int; rddata_reg(31) <= '0';
ack_sreg(0) <= '1'; ack_sreg(2) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00001011" => when "00001011" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
...@@ -884,8 +897,8 @@ begin ...@@ -884,8 +897,8 @@ begin
mf_tx_ctrl_start_int <= wrdata_reg(1); mf_tx_ctrl_start_int <= wrdata_reg(1);
mf_tx_ctrl_bytes_num_int <= wrdata_reg(23 downto 8); mf_tx_ctrl_bytes_num_int <= wrdata_reg(23 downto 8);
end if; end if;
rddata_reg(0) <= mf_tx_ctrl_rst_int; rddata_reg(0) <= '0';
rddata_reg(1) <= mf_tx_ctrl_start_int; rddata_reg(1) <= '0';
rddata_reg(23 downto 8) <= mf_tx_ctrl_bytes_num_int; rddata_reg(23 downto 8) <= mf_tx_ctrl_bytes_num_int;
rddata_reg(2) <= 'X'; rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X'; rddata_reg(3) <= 'X';
...@@ -901,7 +914,7 @@ begin ...@@ -901,7 +914,7 @@ begin
rddata_reg(29) <= 'X'; rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X'; rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(2) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00010000" => when "00010000" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
...@@ -949,7 +962,7 @@ begin ...@@ -949,7 +962,7 @@ begin
if (wb_we_i = '1') then if (wb_we_i = '1') then
mf_rx_ctrl_rst_int <= wrdata_reg(0); mf_rx_ctrl_rst_int <= wrdata_reg(0);
end if; end if;
rddata_reg(0) <= mf_rx_ctrl_rst_int; rddata_reg(0) <= '0';
rddata_reg(1) <= 'X'; rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X'; rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X'; rddata_reg(3) <= 'X';
...@@ -981,7 +994,7 @@ begin ...@@ -981,7 +994,7 @@ begin
rddata_reg(29) <= 'X'; rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X'; rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(2) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00010101" => when "00010101" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
...@@ -1973,12 +1986,31 @@ begin ...@@ -1973,12 +1986,31 @@ begin
-- Drive the data output bus -- Drive the data output bus
wb_dat_o <= rddata_reg; wb_dat_o <= rddata_reg;
-- reset of the masterFIP core -- reset of the masterFIP core
mf_rstn_core_o <= mf_rstn_core_int; process (clk_sys_i, rst_n_i)
-- reset of the fieldrive chip (FD_RSTN) begin
mf_rstn_fd_o <= mf_rstn_fd_int; if (rst_n_i = '0') then
-- reset magic value mf_rst_core_dly0 <= '0';
-- pass-through field: reset magic value in register: rstn mf_rst_core_o <= '0';
mf_rstn_lock_o <= wrdata_reg(31 downto 16); elsif rising_edge(clk_sys_i) then
mf_rst_core_dly0 <= mf_rst_core_int;
mf_rst_core_o <= mf_rst_core_int and (not mf_rst_core_dly0);
end if;
end process;
-- reset of the fieldrive chip
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
mf_rst_fd_dly0 <= '0';
mf_rst_fd_o <= '0';
elsif rising_edge(clk_sys_i) then
mf_rst_fd_dly0 <= mf_rst_fd_int;
mf_rst_fd_o <= mf_rst_fd_int and (not mf_rst_fd_dly0);
end if;
end process;
-- debugging -- debugging
mf_dbg_o <= mf_dbg_int; mf_dbg_o <= mf_dbg_int;
-- 1v8_shdn_n -- 1v8_shdn_n
...@@ -1994,7 +2026,18 @@ begin ...@@ -1994,7 +2026,18 @@ begin
-- value -- value
mf_dac_config_value_o <= mf_dac_config_value_int; mf_dac_config_value_o <= mf_dac_config_value_int;
-- load -- load
mf_dac_config_load_o <= mf_dac_config_load_int; process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
mf_dac_config_load_dly0 <= '0';
mf_dac_config_load_o <= '0';
elsif rising_edge(clk_sys_i) then
mf_dac_config_load_dly0 <= mf_dac_config_load_int;
mf_dac_config_load_o <= mf_dac_config_load_int and (not mf_dac_config_load_dly0);
end if;
end process;
-- termination enable -- termination enable
mf_ext_sync_term_en_o <= mf_ext_sync_term_en_int; mf_ext_sync_term_en_o <= mf_ext_sync_term_en_int;
-- transceiver direction -- transceiver direction
...@@ -2010,23 +2053,78 @@ begin ...@@ -2010,23 +2053,78 @@ begin
-- macrocycle lgth -- macrocycle lgth
mf_macrocyc_lgth_o <= mf_macrocyc_lgth_int; mf_macrocyc_lgth_o <= mf_macrocyc_lgth_int;
-- macrocycle cnt start -- macrocycle cnt start
mf_macrocyc_start_o <= mf_macrocyc_start_int; process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
mf_macrocyc_start_dly0 <= '0';
mf_macrocyc_start_o <= '0';
elsif rising_edge(clk_sys_i) then
mf_macrocyc_start_dly0 <= mf_macrocyc_start_int;
mf_macrocyc_start_o <= mf_macrocyc_start_int and (not mf_macrocyc_start_dly0);
end if;
end process;
-- turnaround time -- turnaround time
mf_turnar_lgth_o <= mf_turnar_lgth_int; mf_turnar_lgth_o <= mf_turnar_lgth_int;
-- turnaround cnt start -- turnaround cnt start
mf_turnar_start_o <= mf_turnar_start_int; process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
mf_turnar_start_dly0 <= '0';
mf_turnar_start_o <= '0';
elsif rising_edge(clk_sys_i) then
mf_turnar_start_dly0 <= mf_turnar_start_int;
mf_turnar_start_o <= mf_turnar_start_int and (not mf_turnar_start_dly0);
end if;
end process;
-- silence time -- silence time
mf_silen_lgth_o <= mf_silen_lgth_int; mf_silen_lgth_o <= mf_silen_lgth_int;
-- silence cnt start -- silence cnt start
mf_silen_start_o <= mf_silen_start_int; process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
mf_silen_start_dly0 <= '0';
mf_silen_start_o <= '0';
elsif rising_edge(clk_sys_i) then
mf_silen_start_dly0 <= mf_silen_start_int;
mf_silen_start_o <= mf_silen_start_int and (not mf_silen_start_dly0);
end if;
end process;
-- macrocycle time counter -- macrocycle time counter
-- number of macrocycles -- number of macrocycles
-- turnaround time counter -- turnaround time counter
-- silence time counter -- silence time counter
-- tx rst -- tx rst
mf_tx_ctrl_rst_o <= mf_tx_ctrl_rst_int; process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
mf_tx_ctrl_rst_dly0 <= '0';
mf_tx_ctrl_rst_o <= '0';
elsif rising_edge(clk_sys_i) then
mf_tx_ctrl_rst_dly0 <= mf_tx_ctrl_rst_int;
mf_tx_ctrl_rst_o <= mf_tx_ctrl_rst_int and (not mf_tx_ctrl_rst_dly0);
end if;
end process;
-- tx strt -- tx strt
mf_tx_ctrl_start_o <= mf_tx_ctrl_start_int; process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
mf_tx_ctrl_start_dly0 <= '0';
mf_tx_ctrl_start_o <= '0';
elsif rising_edge(clk_sys_i) then
mf_tx_ctrl_start_dly0 <= mf_tx_ctrl_start_int;
mf_tx_ctrl_start_o <= mf_tx_ctrl_start_int and (not mf_tx_ctrl_start_dly0);
end if;
end process;
-- tx number of bytes -- tx number of bytes
mf_tx_ctrl_bytes_num_o <= mf_tx_ctrl_bytes_num_int; mf_tx_ctrl_bytes_num_o <= mf_tx_ctrl_bytes_num_int;
-- tx ended -- tx ended
...@@ -2037,7 +2135,18 @@ begin ...@@ -2037,7 +2135,18 @@ begin
-- fd_txer_cnt -- fd_txer_cnt
-- fd_txer_tstamp -- fd_txer_tstamp
-- rx rst -- rx rst
mf_rx_ctrl_rst_o <= mf_rx_ctrl_rst_int; process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
mf_rx_ctrl_rst_dly0 <= '0';
mf_rx_ctrl_rst_o <= '0';
elsif rising_edge(clk_sys_i) then
mf_rx_ctrl_rst_dly0 <= mf_rx_ctrl_rst_int;
mf_rx_ctrl_rst_o <= mf_rx_ctrl_rst_int and (not mf_rx_ctrl_rst_dly0);
end if;
end process;
-- rx preamble detected -- rx preamble detected
-- rx frame ok -- rx frame ok
-- rx frame crc error -- rx frame crc error
......
rtl/masterFIP_pkg.vhd
View file @ 462ce06a
...@@ -191,10 +191,8 @@ package masterFIP_pkg is ...@@ -191,10 +191,8 @@ package masterFIP_pkg is
wb_ack_o : out std_logic; wb_ack_o : out std_logic;
wb_stall_o : out std_logic; wb_stall_o : out std_logic;
mf_rstn_core_o : out std_logic; mf_rst_core_o : out std_logic;
mf_rstn_fd_o : out std_logic; mf_rst_fd_o : out std_logic;
mf_rstn_lock_o : out std_logic_vector(15 downto 0);
mf_rstn_lock_wr_o : out std_logic;
mf_dbg_o : out std_logic_vector(31 downto 0); mf_dbg_o : out std_logic_vector(31 downto 0);
......
rtl/wbgen/fmc_masterfip_csr.h
View file @ 462ce06a
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* File : fmc_masterfip_csr.h * File : fmc_masterfip_csr.h
* Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb * Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
* Created : 03/14/16 12:32:55 * Created : 03/17/16 18:51:55
* Standard : ANSI C * Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
...@@ -31,19 +31,13 @@ ...@@ -31,19 +31,13 @@
#endif #endif
/* definitions for register: rstn */ /* definitions for register: rst */
/* definitions for field: reset of the masterFIP core in reg: rstn */ /* definitions for field: reset of the masterFIP core in reg: rst */
#define MF_RSTN_CORE WBGEN2_GEN_MASK(0, 1) #define MF_RST_CORE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: reset of the fieldrive chip (FD_RSTN) in reg: rstn */ /* definitions for field: reset of the fieldrive chip in reg: rst */
#define MF_RSTN_FD WBGEN2_GEN_MASK(1, 1) #define MF_RST_FD WBGEN2_GEN_MASK(1, 1)
/* definitions for field: reset magic value in reg: rstn */
#define MF_RSTN_LOCK_MASK WBGEN2_GEN_MASK(16, 16)
#define MF_RSTN_LOCK_SHIFT 16
#define MF_RSTN_LOCK_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define MF_RSTN_LOCK_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: id */ /* definitions for register: id */
...@@ -477,8 +471,8 @@ ...@@ -477,8 +471,8 @@
/* definitions for register: tx data reg66 */ /* definitions for register: tx data reg66 */
/* definitions for register: tx data reg67 */ /* definitions for register: tx data reg67 */
/* [0x0]: REG rstn */ /* [0x0]: REG rst */
#define MF_REG_RSTN 0x00000000 #define MF_REG_RST 0x00000000
/* [0x4]: REG id */ /* [0x4]: REG id */
#define MF_REG_ID 0x00000004 #define MF_REG_ID 0x00000004
/* [0x8]: REG dbg */ /* [0x8]: REG dbg */
......
rtl/wbgen/fmc_masterfip_csr.htm
View file @ 462ce06a
...@@ -34,7 +34,7 @@ ...@@ -34,7 +34,7 @@
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/> <span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/> <span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/> <span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">rstn</a></span><br/> <span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">rst</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">id</a></span><br/> <span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">id</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">dbg</a></span><br/> <span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">dbg</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">adc</a></span><br/> <span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">adc</a></span><br/>
...@@ -220,13 +220,13 @@ C prefix ...@@ -220,13 +220,13 @@ C prefix
REG REG
</td> </td>
<td > <td >
<A href="#RSTN">rstn</a> <A href="#RST">rst</a>
</td> </td>
<td class="td_code"> <td class="td_code">
mf_rstn mf_rst
</td> </td>
<td class="td_code"> <td class="td_code">
RSTN RST
</td> </td>
</tr> </tr>
<tr class="tr_even"> <tr class="tr_even">
...@@ -2930,7 +2930,7 @@ rst_n_i ...@@ -2930,7 +2930,7 @@ rst_n_i
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
<b>rstn:</b> <b>rst:</b>
</td> </td>
<td class="td_arrow_right"> <td class="td_arrow_right">
...@@ -2947,7 +2947,7 @@ clk_sys_i ...@@ -2947,7 +2947,7 @@ clk_sys_i
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
mf_rstn_core_o mf_rst_core_o
</td> </td>
<td class="td_arrow_right"> <td class="td_arrow_right">
&rarr; &rarr;
...@@ -2964,7 +2964,7 @@ wb_adr_i[7:0] ...@@ -2964,7 +2964,7 @@ wb_adr_i[7:0]
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
mf_rstn_fd_o mf_rst_fd_o
</td> </td>
<td class="td_arrow_right"> <td class="td_arrow_right">
&rarr; &rarr;
...@@ -2978,13 +2978,13 @@ mf_rstn_fd_o ...@@ -2978,13 +2978,13 @@ mf_rstn_fd_o
wb_dat_i[31:0] wb_dat_i[31:0]
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
&nbsp;
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
mf_rstn_lock_o[15:0]
</td> </td>
<td class="td_arrow_right"> <td class="td_arrow_right">
&rArr;
</td> </td>
</tr> </tr>
<tr> <tr>
...@@ -2998,10 +2998,10 @@ wb_dat_o[31:0] ...@@ -2998,10 +2998,10 @@ wb_dat_o[31:0]
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
mf_rstn_lock_wr_o <b>id:</b>
</td> </td>
<td class="td_arrow_right"> <td class="td_arrow_right">
&rarr;
</td> </td>
</tr> </tr>
<tr> <tr>
...@@ -3032,7 +3032,7 @@ wb_sel_i[3:0] ...@@ -3032,7 +3032,7 @@ wb_sel_i[3:0]
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
<b>id:</b> <b>dbg:</b>
</td> </td>
<td class="td_arrow_right"> <td class="td_arrow_right">
...@@ -3046,40 +3046,6 @@ wb_sel_i[3:0] ...@@ -3046,40 +3046,6 @@ wb_sel_i[3:0]
wb_stb_i wb_stb_i
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_we_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>dbg:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_ack_o
</td>
<td class="td_sym_center">
</td> </td>
<td class="td_pblock_right"> <td class="td_pblock_right">
...@@ -3091,10 +3057,10 @@ mf_dbg_o[31:0] ...@@ -3091,10 +3057,10 @@ mf_dbg_o[31:0]
</tr> </tr>
<tr> <tr>
<td class="td_arrow_left"> <td class="td_arrow_left">
&larr; &rarr;
</td> </td>
<td class="td_pblock_left"> <td class="td_pblock_left">
wb_stall_o wb_we_i
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
&nbsp; &nbsp;
...@@ -3108,10 +3074,10 @@ wb_stall_o ...@@ -3108,10 +3074,10 @@ wb_stall_o
</tr> </tr>
<tr> <tr>
<td class="td_arrow_left"> <td class="td_arrow_left">
&larr;
</td> </td>
<td class="td_pblock_left"> <td class="td_pblock_left">
wb_ack_o
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
...@@ -3125,10 +3091,10 @@ wb_stall_o ...@@ -3125,10 +3091,10 @@ wb_stall_o
</tr> </tr>
<tr> <tr>
<td class="td_arrow_left"> <td class="td_arrow_left">
&larr;
</td> </td>
<td class="td_pblock_left"> <td class="td_pblock_left">
wb_stall_o
</td> </td>
<td class="td_sym_center"> <td class="td_sym_center">
...@@ -11388,15 +11354,15 @@ mf_tx_data_reg67_o[31:0] ...@@ -11388,15 +11354,15 @@ mf_tx_data_reg67_o[31:0]
</table> </table>
<h3><a name="sect_3_0">3. Register description</a></h3> <h3><a name="sect_3_0">3. Register description</a></h3>
<a name="RSTN"></a> <a name="RST"></a>
<h3><a name="sect_3_1">3.1. rstn</a></h3> <h3><a name="sect_3_1">3.1. rst</a></h3>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
<td > <td >
<b>HW prefix: </b> <b>HW prefix: </b>
</td> </td>
<td class="td_code"> <td class="td_code">
mf_rstn mf_rst
</td> </td>
</tr> </tr>
<tr> <tr>
...@@ -11412,7 +11378,7 @@ mf_rstn ...@@ -11412,7 +11378,7 @@ mf_rstn
<b>C prefix: </b> <b>C prefix: </b>
</td> </td>
<td class="td_code"> <td class="td_code">
RSTN RST
</td> </td>
</tr> </tr>
<tr> <tr>
...@@ -11425,7 +11391,7 @@ RSTN ...@@ -11425,7 +11391,7 @@ RSTN
</tr> </tr>
</table> </table>
<p> <p>
software reset of the masterFIP core; active low; there is also an unlock word provided to prevent resetting the core by accidentally accessing this register. software reset of the masterFIP core
</p> </p>
<table cellpadding=0 cellspacing=0 border=0> <table cellpadding=0 cellspacing=0 border=0>
<tr> <tr>
...@@ -11455,29 +11421,29 @@ software reset of the masterFIP core; active low; there is also an unlock word p ...@@ -11455,29 +11421,29 @@ software reset of the masterFIP core; active low; there is also an unlock word p
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td class="td_unused">
LOCK[15:8] -
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
</tr> </tr>
</table> </table>
...@@ -11509,29 +11475,29 @@ LOCK[15:8] ...@@ -11509,29 +11475,29 @@ LOCK[15:8]
</td> </td>
</tr> </tr>
<tr> <tr>
<td style="border: solid 1px black;" colspan=8 class="td_field"> <td class="td_unused">
LOCK[7:0] -
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
<td > <td class="td_unused">
-
</td> </td>
</tr> </tr>
</table> </table>
...@@ -11646,16 +11612,12 @@ CORE ...@@ -11646,16 +11612,12 @@ CORE
<ul> <ul>
<li><b> <li><b>
CORE CORE
</b>[<i>read/write</i>]: reset of the masterFIP core </b>[<i>write-only</i>]: reset of the masterFIP core
<br>write 0: masterFIP core is held in reset<br> write 1: normal core operation <br>write 1: generates a 1-tick-long (10ns) masterFIP core reset;<br> note: there is no need to clear the field before writing another '1'
<li><b> <li><b>
FD FD
</b>[<i>read/write</i>]: reset of the fieldrive chip (FD_RSTN) </b>[<i>write-only</i>]: reset of the fieldrive chip
<br>write 0: fieldrive is held in reset<br> write 1: normal fieldrive operation <br>write 1: to generate a fieldrive reset;<br> upon writing, the masterFIP_core generates a 1-WorldFIP-tick-long FD RSTN;<br> note: there is no need to clear the field before writing another '1'
<li><b>
LOCK
</b>[<i>write-only</i>]: reset magic value
<br>Protection field - the state of the rst line will<br> only be updated if lock is written with 0xcafe together with the new state of the reset line.
</ul> </ul>
<a name="ID"></a> <a name="ID"></a>
<h3><a name="sect_3_2">3.2. id</a></h3> <h3><a name="sect_3_2">3.2. id</a></h3>
...@@ -12712,7 +12674,7 @@ VALUE ...@@ -12712,7 +12674,7 @@ VALUE
<li><b> <li><b>
LOAD LOAD
</b>[<i>read/write</i>]: load </b>[<i>read/write</i>]: load
<br>upon rising edge, the value is transferred to the dac <br>write 1: loads the dac with the dac_value;<br> note: there is no need to clear the field before writing another '1'
</ul> </ul>
<a name="EXT_SYNC"></a> <a name="EXT_SYNC"></a>
<h3><a name="sect_3_6">3.6. ext sync</a></h3> <h3><a name="sect_3_6">3.6. ext sync</a></h3>
...@@ -13764,7 +13726,7 @@ LGTH ...@@ -13764,7 +13726,7 @@ LGTH
<li><b> <li><b>
START START
</b>[<i>read/write</i>]: macrocycle cnt start </b>[<i>read/write</i>]: macrocycle cnt start
<br>initiates the counting of the macrocycle counter <br>write 1: initiates the counting of the macrocycle counter<br> note: there is no need to clear the field before writing another '1'
</ul> </ul>
<a name="TURNAR"></a> <a name="TURNAR"></a>
<h3><a name="sect_3_10">3.10. turnaround lgth</a></h3> <h3><a name="sect_3_10">3.10. turnaround lgth</a></h3>
...@@ -14026,7 +13988,7 @@ LGTH ...@@ -14026,7 +13988,7 @@ LGTH
<li><b> <li><b>
START START
</b>[<i>read/write</i>]: turnaround cnt start </b>[<i>read/write</i>]: turnaround cnt start
<br>initiates the counting of the turnaround counter <br>write 1: initiates the counting of the turnaround counter<br> note: there is no need to clear the field before writing another '1'
</ul> </ul>
<a name="SILEN"></a> <a name="SILEN"></a>
<h3><a name="sect_3_11">3.11. silence lgth</a></h3> <h3><a name="sect_3_11">3.11. silence lgth</a></h3>
...@@ -14288,7 +14250,7 @@ LGTH ...@@ -14288,7 +14250,7 @@ LGTH
<li><b> <li><b>
START START
</b>[<i>read/write</i>]: silence cnt start </b>[<i>read/write</i>]: silence cnt start
<br>initiates the counting of the silence counter <br>initiates the counting of the silence counter<br> note: there is no need to clear the field before writing another '1'
</ul> </ul>
<a name="MACROCYC_TIME_CNT"></a> <a name="MACROCYC_TIME_CNT"></a>
<h3><a name="sect_3_12">3.12. macrocycle time cnt</a></h3> <h3><a name="sect_3_12">3.12. macrocycle time cnt</a></h3>
...@@ -15578,11 +15540,11 @@ RST ...@@ -15578,11 +15540,11 @@ RST
<li><b> <li><b>
RST RST
</b>[<i>read/write</i>]: tx rst </b>[<i>read/write</i>]: tx rst
<br>write 0: normal serializer operation<br> write 1: serializer is held in reset <br>write 1: generates a 1-tick-long reset to the serializer<br> note: there is no need to clear the field before writing another '1'
<li><b> <li><b>
START START
</b>[<i>read/write</i>]: tx strt </b>[<i>read/write</i>]: tx strt
<br>initiates the serializer to send a frame <br>write 1: initiates the serializer to send a frame of tx_ctrl_bytes_num data bytes;<br> the bytes are retrieved one-by-one by the registers: tx_data_ctrl, tx_data_reg1..tx_data_reg67;<br> the bytes: FSS, CRC and FES are generated automatically by the serializer.<br> note: there is no need to clear the field before writing another '1'
<li><b> <li><b>
BYTES_NUM BYTES_NUM
</b>[<i>read/write</i>]: tx number of bytes </b>[<i>read/write</i>]: tx number of bytes
...@@ -16891,7 +16853,7 @@ RST ...@@ -16891,7 +16853,7 @@ RST
<li><b> <li><b>
RST RST
</b>[<i>read/write</i>]: rx rst </b>[<i>read/write</i>]: rx rst
<br>write 0: normal deserializer operation<br> write 1: deserializer is held in reset<br> note that the deserialiser is automatically hw reset when the serializer is active <br>write 1: generates a 1-tick-long reset to the deserializer<br> note: there is no need to clear the field before writing another '1'<br> note: the deserializer is automatically hw-reset when the serializer is active
</ul> </ul>
<a name="RX_STAT"></a> <a name="RX_STAT"></a>
<h3><a name="sect_3_22">3.22. rx status</a></h3> <h3><a name="sect_3_22">3.22. rx status</a></h3>
......
rtl/wbgen/fmc_masterfip_csr.wb
View file @ 462ce06a
...@@ -9,39 +9,26 @@ peripheral { ...@@ -9,39 +9,26 @@ peripheral {
-- reset -- -- reset --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
reg { reg {
name = "rstn"; name = "rst";
prefix = "rstn"; prefix = "rst";
description = "software reset of the masterFIP core; active low; there is also an unlock word provided to prevent resetting the core by accidentally accessing this register."; description = "software reset of the masterFIP core";
field { field {
name = "reset of the masterFIP core"; name = "reset of the masterFIP core";
description = "write 0: masterFIP core is held in reset\ description = "write 1: generates a 1-tick-long (10ns) masterFIP core reset;\
write 1: normal core operation"; note: there is no need to clear the field before writing another '1'";
type=BIT; type = MONOSTABLE;
--type = PASS_THROUGH;
--size = 1;
prefix = "core"; prefix = "core";
}; };
field { field {
name = "reset of the fieldrive chip (FD_RSTN)"; name = "reset of the fieldrive chip";
description = "write 0: fieldrive is held in reset\ description = "write 1: to generate a fieldrive reset;\
write 1: normal fieldrive operation"; upon writing, the masterFIP_core generates a 1-WorldFIP-tick-long FD RSTN;\
type=BIT; note: there is no need to clear the field before writing another '1'";
--type = PASS_THROUGH; type = MONOSTABLE;
--size = 1; prefix = "fd";
prefix = "fd";
}; };
field {
name = "reset magic value";
description = "Protection field - the state of the rst line will\
only be updated if lock is written with 0xcafe together with the new state of the reset line.";
type = PASS_THROUGH;
prefix = "lock";
align = 16;
size = 16;
};
}; };
...@@ -155,7 +142,7 @@ peripheral { ...@@ -155,7 +142,7 @@ peripheral {
For the DAC middle range: value = 32768 = 0x8000"; For the DAC middle range: value = 32768 = 0x8000";
type = SLV; type = SLV;
size = 16; size = 16;
-- add reset value = "0x8000"; -- add reset_value = "0x8000";
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
...@@ -163,8 +150,9 @@ peripheral { ...@@ -163,8 +150,9 @@ peripheral {
field { field {
name = "load"; name = "load";
prefix = "load"; prefix = "load";
description = "upon rising edge, the value is transferred to the dac"; description = "write 1: loads the dac with the dac_value;\
type = BIT; note: there is no need to clear the field before writing another '1'";
type = MONOSTABLE;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
...@@ -281,9 +269,10 @@ peripheral { ...@@ -281,9 +269,10 @@ peripheral {
}; };
field { field {
name = "macrocycle cnt start"; name = "macrocycle cnt start";
description = "initiates the counting of the macrocycle counter"; description = "write 1: initiates the counting of the macrocycle counter\
note: there is no need to clear the field before writing another '1'";
prefix = "start"; prefix = "start";
type = BIT; type = MONOSTABLE;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
...@@ -304,9 +293,10 @@ peripheral { ...@@ -304,9 +293,10 @@ peripheral {
}; };
field { field {
name = "turnaround cnt start"; name = "turnaround cnt start";
description = "initiates the counting of the turnaround counter"; description = "write 1: initiates the counting of the turnaround counter\
note: there is no need to clear the field before writing another '1'";
prefix = "start"; prefix = "start";
type = BIT; type = MONOSTABLE;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
...@@ -327,9 +317,10 @@ peripheral { ...@@ -327,9 +317,10 @@ peripheral {
}; };
field { field {
name = "silence cnt start"; name = "silence cnt start";
description = "initiates the counting of the silence counter"; description = "initiates the counting of the silence counter\
note: there is no need to clear the field before writing another '1'";
prefix = "start"; prefix = "start";
type = BIT; type = MONOSTABLE;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
...@@ -403,19 +394,22 @@ peripheral { ...@@ -403,19 +394,22 @@ peripheral {
field { field {
name = "tx rst"; name = "tx rst";
description = "write 0: normal serializer operation\ description = "write 1: generates a 1-tick-long reset to the serializer\
write 1: serializer is held in reset"; note: there is no need to clear the field before writing another '1'";
prefix = "rst"; prefix = "rst";
type = BIT; type = MONOSTABLE;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
field { field {
name = "tx strt"; name = "tx strt";
description = "initiates the serializer to send a frame"; description = "write 1: initiates the serializer to send a frame of tx_ctrl_bytes_num data bytes;\
the bytes are retrieved one-by-one by the registers: tx_data_ctrl, tx_data_reg1..tx_data_reg67;\
the bytes: FSS, CRC and FES are generated automatically by the serializer.\
note: there is no need to clear the field before writing another '1'";
prefix = "start"; prefix = "start";
type = BIT; type = MONOSTABLE;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
...@@ -552,12 +546,12 @@ peripheral { ...@@ -552,12 +546,12 @@ peripheral {
field { field {
name = "rx rst"; name = "rx rst";
description = "write 0: normal deserializer operation\ description = "write 1: generates a 1-tick-long reset to the deserializer\
write 1: deserializer is held in reset\ note: there is no need to clear the field before writing another '1'\
note that the deserialiser is automatically hw reset when the serializer is active"; note: the deserializer is automatically hw-reset when the serializer is active";
prefix = "rst"; prefix = "rst";
type = BIT; type = MONOSTABLE;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
......
sim/spec/data_vectors/masterFIP_test.vec
View file @ 462ce06a
...@@ -96,7 +96,9 @@ wr 0000000000030174 F EEDDCC05 -- for 2 data bytes: EEDDCC05 | for 8 data bytes ...@@ -96,7 +96,9 @@ wr 0000000000030174 F EEDDCC05 -- for 2 data bytes: EEDDCC05 | for 8 data bytes
-- tx_start -- tx_start
wr 000000000003003C F 00000502 -- for 2 data bytes: 00000502 | for 8 data bytes: 00000B02 wr 000000000003003C F 00000502 -- for 2 data bytes: 00000502 | for 8 data bytes: 00000B02
wait %d40000 wait %d20000
wr 000000000003003C F 00000000
wait %d20000
--------------- ID_DAT --------------- --------------- ID_DAT ---------------
...@@ -116,7 +118,7 @@ wait %d20 ...@@ -116,7 +118,7 @@ wait %d20
-- tx_start -- tx_start
wr 000000000003003C F 00000202 wr 000000000003003C F 00000202
wait %d20 wait %d200
-- deactivate tx_start -- deactivate tx_start
wr 000000000003003C F 00000000 wr 000000000003003C F 00000000
......
sim/spec/testbench/tb_masterFIP.vhd
View file @ 462ce06a
...@@ -524,7 +524,7 @@ begin ...@@ -524,7 +524,7 @@ begin
nostat_i => nostat, nostat_i => nostat,
rstin_i => (rst_n),--was not rstin_i => (rst_n),--was not
rstpon_i => '1', rstpon_i => '1',
slone_i => '0', --slone, slone_i => slone,
rston_o => urst_from_nf, rston_o => urst_from_nf,
var1_acc_i => var1_acc, var1_acc_i => var1_acc,
...@@ -536,7 +536,7 @@ begin ...@@ -536,7 +536,7 @@ begin
ack_o => ack, ack_o => ack,
adr_i => adr, adr_i => adr,
cyc_i => cyc, cyc_i => cyc,
dat_i => dat_to_fip, dat_i => "0101010101010111",--dat_to_fip,
dat_o => dat_from_fip, dat_o => dat_from_fip,
stb_i => stb, stb_i => stb,
we_i => we, we_i => we,
...@@ -739,6 +739,10 @@ begin ...@@ -739,6 +739,10 @@ begin
'1' after 194000 ns, '0' after 194080 ns, '1' after 194000 ns, '0' after 194080 ns,
'1' after 565151 ns, '0' after 565231 ns; '1' after 565151 ns, '0' after 565231 ns;
fd_wdgn <= '0' after 8500 ns, '1' after 8580 ns,
'0' after 194000 ns, '1' after 194080 ns,
'0' after 565151 ns, '1' after 565231 ns;
rst_n <= RSTOUT18n; rst_n <= RSTOUT18n;
GPIO(0) <= irq_p; GPIO(0) <= irq_p;
GPIO(1) <= spare; GPIO(1) <= spare;
......
syn/spec/spec_masterfip.xise
View file @ 462ce06a
...@@ -17,11 +17,11 @@ ...@@ -17,11 +17,11 @@
<files> <files>
<file xil_pn:name="../../rtl/carrier_info.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../rtl/carrier_info.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="95"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="95"/>
<association xil_pn:name="Implementation" xil_pn:seqID="53"/> <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file> </file>
<file xil_pn:name="../../rtl/decr_counter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../rtl/decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
<association xil_pn:name="Implementation" xil_pn:seqID="34"/> <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file> </file>
<file xil_pn:name="../../rtl/free_counter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../rtl/free_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
...@@ -29,7 +29,7 @@ ...@@ -29,7 +29,7 @@
</file> </file>
<file xil_pn:name="../../rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="54"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="54"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/> <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file> </file>
<file xil_pn:name="../../rtl/irq_generator.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../rtl/irq_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
...@@ -61,7 +61,7 @@ ...@@ -61,7 +61,7 @@
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
<association xil_pn:name="Implementation" xil_pn:seqID="49"/> <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
...@@ -77,7 +77,7 @@ ...@@ -77,7 +77,7 @@
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="71"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="71"/>
<association xil_pn:name="Implementation" xil_pn:seqID="48"/> <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
...@@ -121,43 +121,43 @@ ...@@ -121,43 +121,43 @@
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/>
<association xil_pn:name="Implementation" xil_pn:seqID="36"/> <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="67"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="67"/>
<association xil_pn:name="Implementation" xil_pn:seqID="44"/> <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/> <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/>
<association xil_pn:name="Implementation" xil_pn:seqID="43"/> <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="Implementation" xil_pn:seqID="42"/> <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
<association xil_pn:name="Implementation" xil_pn:seqID="41"/> <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
<association xil_pn:name="Implementation" xil_pn:seqID="40"/> <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/>
<association xil_pn:name="Implementation" xil_pn:seqID="56"/> <association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
<association xil_pn:name="Implementation" xil_pn:seqID="47"/> <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/>
<association xil_pn:name="Implementation" xil_pn:seqID="46"/> <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
...@@ -181,19 +181,19 @@ ...@@ -181,19 +181,19 @@
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/>
<association xil_pn:name="Implementation" xil_pn:seqID="55"/> <association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/> <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
<association xil_pn:name="Implementation" xil_pn:seqID="45"/> <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/> <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
...@@ -301,7 +301,7 @@ ...@@ -301,7 +301,7 @@
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/> <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrc_syscon_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
...@@ -309,7 +309,7 @@ ...@@ -309,7 +309,7 @@
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/wrcore_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/> <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wrc_core/xwr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
...@@ -317,11 +317,11 @@ ...@@ -317,11 +317,11 @@
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="57"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="57"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
...@@ -629,23 +629,23 @@ ...@@ -629,23 +629,23 @@
</file> </file>
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...@@ -653,15 +653,15 @@ ...@@ -653,15 +653,15 @@
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...@@ -671,11 +671,11 @@ ...@@ -671,11 +671,11 @@
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...@@ -683,7 +683,7 @@ ...@@ -683,7 +683,7 @@
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...@@ -695,7 +695,7 @@ ...@@ -695,7 +695,7 @@
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...@@ -723,7 +723,7 @@ ...@@ -723,7 +723,7 @@
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...@@ -755,7 +755,7 @@ ...@@ -755,7 +755,7 @@
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...@@ -767,7 +767,7 @@ ...@@ -767,7 +767,7 @@
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...@@ -794,7 +794,7 @@ ...@@ -794,7 +794,7 @@
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...@@ -903,7 +903,7 @@ ...@@ -903,7 +903,7 @@
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...@@ -911,141 +911,141 @@ ...@@ -911,141 +911,141 @@
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<library xil_pn:name="nanoFIP_lib"/> <library xil_pn:name="nanoFIP_lib"/>
</file> </file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_fd_transmitter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_fd_transmitter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="88"/>
<association xil_pn:name="Implementation" xil_pn:seqID="334"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/> <library xil_pn:name="nanoFIP_lib"/>
</file> </file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_incr_counter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_incr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="335"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/> <library xil_pn:name="nanoFIP_lib"/>
</file> </file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_jtag_controller.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_jtag_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="87"/>
<association xil_pn:name="Implementation" xil_pn:seqID="336"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/> <library xil_pn:name="nanoFIP_lib"/>
</file> </file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_model_constr_decoder.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_model_constr_decoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
<association xil_pn:name="Implementation" xil_pn:seqID="337"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/> <library xil_pn:name="nanoFIP_lib"/>
</file> </file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_production.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_production.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
<association xil_pn:name="Implementation" xil_pn:seqID="339"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/> <library xil_pn:name="nanoFIP_lib"/>
</file> </file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_prod_bytes_retriever.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_prod_bytes_retriever.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
<association xil_pn:name="Implementation" xil_pn:seqID="340"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/> <library xil_pn:name="nanoFIP_lib"/>
</file> </file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_prod_data_lgth_calc.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_prod_data_lgth_calc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
<association xil_pn:name="Implementation" xil_pn:seqID="341"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/> <library xil_pn:name="nanoFIP_lib"/>
</file> </file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_prod_permit.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_prod_permit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="342"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/> <library xil_pn:name="nanoFIP_lib"/>
</file> </file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_reset_unit.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_reset_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
<association xil_pn:name="Implementation" xil_pn:seqID="343"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/> <library xil_pn:name="nanoFIP_lib"/>
</file> </file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_rx_deglitcher.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_rx_deglitcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
<association xil_pn:name="Implementation" xil_pn:seqID="344"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/> <library xil_pn:name="nanoFIP_lib"/>
</file> </file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_rx_deserializer.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_rx_deserializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
<association xil_pn:name="Implementation" xil_pn:seqID="345"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/> <library xil_pn:name="nanoFIP_lib"/>
</file> </file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_rx_osc.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_rx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
<association xil_pn:name="Implementation" xil_pn:seqID="346"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/> <library xil_pn:name="nanoFIP_lib"/>
</file> </file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_status_bytes_gen.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_status_bytes_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
<association xil_pn:name="Implementation" xil_pn:seqID="347"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/> <library xil_pn:name="nanoFIP_lib"/>
</file> </file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_tx_osc.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_tx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
<association xil_pn:name="Implementation" xil_pn:seqID="348"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/> <library xil_pn:name="nanoFIP_lib"/>
</file> </file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_tx_serializer.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_tx_serializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
<association xil_pn:name="Implementation" xil_pn:seqID="349"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/> <library xil_pn:name="nanoFIP_lib"/>
</file> </file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_wb_controller.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_wb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
<association xil_pn:name="Implementation" xil_pn:seqID="350"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/> <library xil_pn:name="nanoFIP_lib"/>
</file> </file>
<file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_package.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../sim/spec/testbench/nanoFIP_lib/wf_package.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="325"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP_lib"/> <library xil_pn:name="nanoFIP_lib"/>
</file> </file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.xise" xil_pn:type="FILE_COREGENISE"> <file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.xise" xil_pn:type="FILE_COREGENISE">
......
syn/spec/tb_masterFIP.fdo
View file @ 462ce06a
###################################################################### ######################################################################
## ##
## Filename: tb_masterFIP.fdo ## Filename: tb_masterFIP.fdo
## Created on: Tue Mar 15 09:49:08 W. Europe Standard Time 2016 ## Created on: Thu Apr 21 18:04:40 W. Europe Daylight Time 2016
## ##
## Auto generated by Project Navigator for Behavioral Simulation ## Auto generated by Project Navigator for Behavioral Simulation
## ##
......
top/spec/spec_masterfip.ucf
View file @ 462ce06a
...@@ -62,9 +62,6 @@ NET "led_rx_err_n_o" IOSTANDARD = "LVCMOS25"; ...@@ -62,9 +62,6 @@ NET "led_rx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_act_n_o" LOC = A20; NET "led_rx_act_n_o" LOC = A20;
NET "led_rx_act_n_o" IOSTANDARD = "LVCMOS25"; NET "led_rx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "bus_term_en_n_o" LOC = Y13;
NET "bus_term_en_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_term_en_o" LOC = AB13; NET "ext_sync_term_en_o" LOC = AB13;
NET "ext_sync_term_en_o" IOSTANDARD = "LVCMOS25"; NET "ext_sync_term_en_o" IOSTANDARD = "LVCMOS25";
......
top/spec_mt/spec_masterfip_mt.vhd
View file @ 462ce06a
...@@ -157,14 +157,14 @@ architecture rtl of spec_masterfip_mt is ...@@ -157,14 +157,14 @@ architecture rtl of spec_masterfip_mt is
3 => (width => 128, entries => 4), -- output of the MT CPU1 with WorldFIP SMMPS periodic variables 3 => (width => 128, entries => 4), -- output of the MT CPU1 with WorldFIP SMMPS periodic variables
4 => (width => 128, entries => 4), -- output of the MT CPU0 with WorldFIP SMMPS aperiodic variables 4 => (width => 128, entries => 4), -- output of the MT CPU0 with WorldFIP SMMPS aperiodic variables
5 => (width => 128, entries => 4), -- output of the MT CPU0 with IRQs to the application (variable/messages programmed with an irq flag) 5 => (width => 128, entries => 4), -- output of the MT CPU0 with IRQs to the application (variable/messages programmed with an irq flag)
6 => (width => 128, entries => 4), -- output of the MT CPU0 command response 6 => (width => 128, entries => 4), -- output of the MT CPU0 command response
7 => (width => 128, entries => 4), -- output of the MT CPU1 command response 7 => (width => 128, entries => 4), -- output of the MT CPU1 command response
others => (0, 0)), others => (0, 0)),
in_slot_count => 2, in_slot_count => 2,
in_slot_config => in_slot_config =>
(0 => (width => 128, entries => 4), -- input to MT CPU0 with commands from the host for the bus configuration (commands like: PROGRAM_BA,HW_RESET, BA_START, BA_RUNNING) (0 => (width => 128, entries => 4), -- input to MT CPU0 with commands from the host for the bus configuration (commands like: PROGRAM_BA,HW_RESET, BA_START, BA_RUNNING)
1 => (width => 128, entries => 4), -- input to MT CPU1 with commands from the host for the control of CPU0 (handles commands like: BA_STOP,SET_VAR_PAYLOAD, SET_MSG_PAYLOAD, GET_REPORT, GET_PRESENT_LIST, GET_IDENT_VAR) 1 => (width => 128, entries => 4), -- input to MT CPU1 with commands from the host for the control of CPU0 (handles commands like: BA_STOP,SET_VAR_PAYLOAD, SET_MSG_PAYLOAD, GET_REPORT, GET_PRESENT_LIST, GET_IDENT_VAR)
-- (change of payload, stop BA, reset CPU0 etc through shared mem, host asking for report) -- (change of payload, stop BA, reset CPU0 etc through shared mem, host asking for report)
others => (0, 0))); others => (0, 0)));
-- RMQs not used -- RMQs not used
...@@ -177,10 +177,10 @@ architecture rtl of spec_masterfip_mt is ...@@ -177,10 +177,10 @@ architecture rtl of spec_masterfip_mt is
constant c_node_config : t_wr_node_config := constant c_node_config : t_wr_node_config :=
(app_id => x"0f1dc03e", (app_id => x"0f1dc03e",
cpu_count => 2, cpu_count => 2,
cpu_memsizes => (65536+32768, 8192, 0, 0, 0, 0, 0, 0), cpu_memsizes => (65536+32768, 8192, 0, 0, 0, 0, 0, 0), -- bytes
hmq_config => c_hmq_config, hmq_config => c_hmq_config,
rmq_config => c_rmq_config, rmq_config => c_rmq_config,
shared_mem_size => 65536); shared_mem_size => 65536); -- bytes
-- crossbar constants -- crossbar constants
constant c_slave_addr : t_wishbone_address_array(0 downto 0):= ( 0 => x"00000000" ); constant c_slave_addr : t_wishbone_address_array(0 downto 0):= ( 0 => x"00000000" );
......
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