software reset of the masterFIP core; active low; there is also an unlock word provided to prevent resetting the core by accidentally accessing this register.
software reset of the masterFIP core
</p>
<tablecellpadding=0cellspacing=0border=0>
<tr>
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@@ -11455,29 +11421,29 @@ software reset of the masterFIP core; active low; there is also an unlock word p
</b>[<i>read/write</i>]: reset of the masterFIP core
<br>write 0: masterFIP core is held in reset<br> write 1: normal core operation
</b>[<i>write-only</i>]: reset of the masterFIP core
<br>write 1: generates a 1-tick-long (10ns) masterFIP core reset;<br> note: there is no need to clear the field before writing another '1'
<li><b>
FD
</b>[<i>read/write</i>]: reset of the fieldrive chip (FD_RSTN)
<br>write 0: fieldrive is held in reset<br> write 1: normal fieldrive operation
<li><b>
LOCK
</b>[<i>write-only</i>]: reset magic value
<br>Protection field - the state of the rst line will<br> only be updated if lock is written with 0xcafe together with the new state of the reset line.
</b>[<i>write-only</i>]: reset of the fieldrive chip
<br>write 1: to generate a fieldrive reset;<br> upon writing, the masterFIP_core generates a 1-WorldFIP-tick-long FD RSTN;<br> note: there is no need to clear the field before writing another '1'
</ul>
<aname="ID"></a>
<h3><aname="sect_3_2">3.2. id</a></h3>
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@@ -12712,7 +12674,7 @@ VALUE
<li><b>
LOAD
</b>[<i>read/write</i>]: load
<br>upon rising edge, the value is transferred to the dac
<br>write 1: loads the dac with the dac_value;<br> note: there is no need to clear the field before writing another '1'
</ul>
<aname="EXT_SYNC"></a>
<h3><aname="sect_3_6">3.6. ext sync</a></h3>
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@@ -13764,7 +13726,7 @@ LGTH
<li><b>
START
</b>[<i>read/write</i>]: macrocycle cnt start
<br>initiates the counting of the macrocycle counter
<br>write 1: initiates the counting of the macrocycle counter<br> note: there is no need to clear the field before writing another '1'
<br>initiates the counting of the silence counter<br> note: there is no need to clear the field before writing another '1'
</ul>
<aname="MACROCYC_TIME_CNT"></a>
<h3><aname="sect_3_12">3.12. macrocycle time cnt</a></h3>
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@@ -15578,11 +15540,11 @@ RST
<li><b>
RST
</b>[<i>read/write</i>]: tx rst
<br>write 0: normal serializer operation<br> write 1: serializer is held in reset
<br>write 1: generates a 1-tick-long reset to the serializer<br> note: there is no need to clear the field before writing another '1'
<li><b>
START
</b>[<i>read/write</i>]: tx strt
<br>initiates the serializer to send a frame
<br>write 1: initiates the serializer to send a frame of tx_ctrl_bytes_num data bytes;<br> the bytes are retrieved one-by-one by the registers: tx_data_ctrl, tx_data_reg1..tx_data_reg67;<br> the bytes: FSS, CRC and FES are generated automatically by the serializer.<br> note: there is no need to clear the field before writing another '1'
<li><b>
BYTES_NUM
</b>[<i>read/write</i>]: tx number of bytes
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@@ -16891,7 +16853,7 @@ RST
<li><b>
RST
</b>[<i>read/write</i>]: rx rst
<br>write 0: normal deserializer operation<br> write 1: deserializer is held in reset<br> note that the deserialiser is automatically hw reset when the serializer is active
<br>write 1: generates a 1-tick-long reset to the deserializer<br> note: there is no need to clear the field before writing another '1'<br> note: the deserializer is automatically hw-reset when the serializer is active
description = "software reset of the masterFIP core; active low; there is also an unlock word provided to prevent resetting the core by accidentally accessing this register.";
name = "rst";
prefix = "rst";
description = "software reset of the masterFIP core";
field {
name = "reset of the masterFIP core";
description = "write 0: masterFIP core is held in reset\
@@ -157,14 +157,14 @@ architecture rtl of spec_masterfip_mt is
3=>(width=>128,entries=>4),-- output of the MT CPU1 with WorldFIP SMMPS periodic variables
4=>(width=>128,entries=>4),-- output of the MT CPU0 with WorldFIP SMMPS aperiodic variables
5=>(width=>128,entries=>4),-- output of the MT CPU0 with IRQs to the application (variable/messages programmed with an irq flag)
6=>(width=>128,entries=>4),-- output of the MT CPU0 command response
6=>(width=>128,entries=>4),-- output of the MT CPU0 command response
7=>(width=>128,entries=>4),-- output of the MT CPU1 command response
others=>(0,0)),
in_slot_count=>2,
in_slot_config=>
(0=>(width=>128,entries=>4),-- input to MT CPU0 with commands from the host for the bus configuration (commands like: PROGRAM_BA,HW_RESET, BA_START, BA_RUNNING)
1=>(width=>128,entries=>4),-- input to MT CPU1 with commands from the host for the control of CPU0 (handles commands like: BA_STOP,SET_VAR_PAYLOAD, SET_MSG_PAYLOAD, GET_REPORT, GET_PRESENT_LIST, GET_IDENT_VAR)
-- (change of payload, stop BA, reset CPU0 etc through shared mem, host asking for report)
-- (change of payload, stop BA, reset CPU0 etc through shared mem, host asking for report)
others=>(0,0)));
-- RMQs not used
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@@ -177,10 +177,10 @@ architecture rtl of spec_masterfip_mt is
