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MasterFIP - Gateware
Commits
5ea0f26e
Commit
5ea0f26e
authored
Jul 29, 2016
by
Evangelia Gousiou
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onewire code cleanup; onewire at 100MHz
parent
89953bc8
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7 changed files
with
895 additions
and
971 deletions
+895
-971
fmc_masterFIP_core.vhd
rtl/fmc_masterFIP_core.vhd
+142
-192
masterFIP_pkg.vhd
rtl/masterFIP_pkg.vhd
+12
-14
onewire_interf.vhd
rtl/onewire_interf.vhd
+566
-0
serialIdTempInt.vhd
rtl/serialIdTempInt.vhd
+0
-590
spec_masterfip.xise
syn/spec/spec_masterfip.xise
+149
-145
tb_masterFIP.fdo
syn/spec/tb_masterFIP.fdo
+1
-1
spec_masterfip.vhd
top/spec/spec_masterfip.vhd
+25
-29
No files found.
rtl/fmc_masterFIP_core.vhd
View file @
5ea0f26e
...
...
@@ -137,20 +137,19 @@ entity fmc_masterFIP_core is
generic
(
g_span
:
integer
:
=
32
;
-- address span in bus interfaces
g_width
:
integer
:
=
32
;
-- data width in bus interfaces
values_for_simul
:
boolean
:
=
FALSE
);
--
this generic is
set to TRUE when instantiated in a test-bench
values_for_simul
:
boolean
:
=
FALSE
);
-- set to TRUE when instantiated in a test-bench
port
(
-- Clock and reset
clk_i
:
in
std_logic
;
-- 100 MHz clock
clk_40m_i
:
in
std_logic
;
-- 40 MHz clock
clk_i
:
in
std_logic
;
-- only one clk domain
rst_i
:
in
std_logic
;
-- PoR or PCIe reset, synched with the clk_i
-- Bus Speed -- 31.25 Kbps: speed_b1 = 0, speed_b0 = 0
speed_b0_i
:
in
std_logic
;
-- 1 Mbps : speed_b1 = 0, speed_b0 = 1
speed_b1_i
:
in
std_logic
;
-- 2.5 Mbps : speed_b1 = 1, speed_b0 = 0
-- 5 Mbps : speed_b1 = 1, speed_b0 = 1
-- One wire DS18B20U+
carrier_onewire_b
:
inout
std_logic
;
--
1-wire
-- One wire DS18B20U+
on the mezzanine
onewire_b
:
inout
std_logic
;
-- mezzanine
1-wire
-- External synchronisation pulse transceiver
ext_sync_term_en_o
:
out
std_logic
;
-- enable 50 Ohms termination of the pulse
ext_sync_dir_o
:
out
std_logic
;
-- transceiver direction
...
...
@@ -164,7 +163,7 @@ entity fmc_masterFIP_core is
adc_5v_en_n_o
:
out
std_logic
;
adc_prim_conn_n_o
:
out
std_logic
;
adc_sec_conn_n_o
:
out
std_logic
;
-- DAC configuration (to set OSC1 to its middle range where the stability is max)
dac_cs_n_o
:
out
std_logic_vector
(
1
downto
0
);
dac_sclk_o
:
out
std_logic
;
...
...
@@ -191,8 +190,8 @@ entity fmc_masterFIP_core is
wb_ack_o
:
out
std_logic
;
wb_dat_o
:
out
std_logic_vector
(
g_width
-1
downto
0
);
-- Aux
aux_o
:
out
std_logic_vector
(
7
downto
0
));
-- group of 8 aux signals to pass to the higher levels
-- Aux
, 8 debugging signals to pass to the higher levels
aux_o
:
out
std_logic_vector
(
7
downto
0
));
end
fmc_masterFIP_core
;
...
...
@@ -244,24 +243,19 @@ architecture rtl of fmc_masterFIP_core is
-- DAC
signal
dac_value
:
std_logic_vector
(
15
downto
0
);
signal
dac_load
,
dac_load_p
:
std_logic
;
-- one wire
signal
temper
,
tmp_temper
:
std_logic_vector
(
15
downto
0
);
signal
id
,
tmp_id
:
std_logic_vector
(
63
downto
0
);
signal
onewire_read_p
,
pps_is_zero
,
pps_load_p
:
std_logic
;
-- ext_sync
signal
ext_sync
,
ext_sync_filt
:
std_logic
;
signal
ext_sync_tst_n
:
std_logic
;
signal
ext_sync_di
:
std_logic_vector
(
0
downto
0
);
-- LEDs
signal
sync_led
,
out_of_sync_led
:
std_logic
;
-- debug
signal
mf_dbg
:
std_logic_vector
(
31
downto
0
);
signal
mf_dbg_p
,
mf_dbg_p_ext
:
std_logic
;
-- prescaler should be (clock_speed/desired_clock_speed)/2 because you want a rising edge every period
signal
prescaler
:
STD_LOGIC_VECTOR
(
25
downto
0
)
:
=
"10111110101111000010000000"
;
-- 12,500,000 in binary
signal
prescaler_counter
:
STD_LOGIC_VECTOR
(
25
downto
0
)
:
=
(
others
=>
'0'
);
signal
clk_1m
:
std_logic
;
signal
temper
,
temp_temper
:
std_logic_vector
(
15
downto
0
);
signal
id
,
temp_id
:
std_logic_vector
(
63
downto
0
);
signal
onewire_read_p
,
pps_is_zero
,
pps_load_p
:
std_logic
;
-- chipscope
-- component chipscope_ila
-- port (
...
...
@@ -506,12 +500,13 @@ begin
mf_onewire_temper_i
=>
temper
,
mf_onewire_id_lsb_i
=>
id
(
31
downto
0
),
mf_onewire_id_msb_i
=>
id
(
63
downto
32
));
-- -- -- -- -- -- -- -- -- -- --
adc_sec_conn_n_o
<=
'0'
when
adc_sec_conn_n
=
'0'
else
'Z'
;
adc_prim_conn_n_o
<=
'0'
when
adc_prim_conn_n
=
'0'
else
'Z'
;
ext_sync_tst_n_o
<=
'0'
when
ext_sync_tst_n
=
'0'
else
'Z'
;
---------------------------------------------------------------------------------------------------
-- resets --
---------------------------------------------------------------------------------------------------
...
...
@@ -521,35 +516,31 @@ begin
speed
<=
speed_b1_i
&
speed_b0_i
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FIELDRIVE reset generation
-- FIELDRIVE reset generation
of length: 2 WorldFIP-clk-cycles of the lowest speed 31.25Kbps
cmp_fd_rst_generate
:
gc_extend_pulse
generic
map
(
g_width
=>
6400
)
--c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(speed)))) -- reset duration: 2 WorldFIP-tick-cycles of the lowest speed 31.25Kbps
generic
map
(
g_width
=>
6400
)
port
map
(
clk_i
=>
clk_i
,
rst_n_i
=>
core_rst_n
,
pulse_i
=>
fd_host_rst_p
,
extended_o
=>
fd_host_rst
);
-- -- -- -- -- -- -- -- -- -- --
fd_rstn_o
<=
not
fd_host_rst
;
-- -- -- -- -- -- -- -- -- -- --
fd_rstn_o
<=
not
fd_host_rst
;
---------------------------------------------------------------------------------------------------
-- external sync --
---------------------------------------------------------------------------------------------------
-- TODO: maybe also disable the reception of a new pulse for some time after the previous pulse
-- input synchronizer
cmp_ext_sync_sync
:
gc_sync_register
generic
map
(
g_width
=>
1
)
-- input synchronizer of the ext_sync_i signal
cmp_ext_sync_sync
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_i
,
rst_n_a_i
=>
core_rst_n
,
d_i
=>
ext_sync_di
,
q_o
(
0
)
=>
ext_sync
);
ext_sync_di
(
0
)
<=
ext_sync_i
;
-- d_i is std_logic_vector; in our case there is only 1 bit
rst_n_i
=>
core_rst_n
,
data_i
=>
ext_sync_i
,
synced_o
=>
ext_sync
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- deglitch filter
cmp_ext_sync_glitch_filt
:
gc_glitch_filt
generic
map
(
g_len
=>
10
)
-- glitches up to 100ns are ignored;
...
...
@@ -559,7 +550,8 @@ begin
dat_i
=>
ext_sync
,
dat_o
=>
ext_sync_filt
);
-- edge detection
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- rising edge detection on the deglitched signal
cmp_ext_sync_p_detect
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_i
,
...
...
@@ -567,7 +559,8 @@ begin
data_i
=>
ext_sync_filt
,
ppulse_o
=>
ext_sync_p
);
-- pulses counter
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- counter of the number of rising edges
cmp_ext_sync_p_cnt
:
incr_counter
generic
map
(
g_counter_lgth
=>
32
)
port
map
...
...
@@ -576,17 +569,20 @@ begin
counter_reinit_i
=>
ext_sync_p_cnt_rst
,
counter_o
=>
ext_sync_p_cnt
);
-- -- -- -- -- -- -- -- -- -- --
ext_sync_p_cnt_rst
<=
ext_sync_p_cnt_host_rst
or
core_rst
;
ext_sync_p_cnt_rst
<=
ext_sync_p_cnt_host_rst
or
core_rst
;
--
---------------------------------------------------------------------------------------------------
-- macrocycle counter --
---------------------------------------------------------------------------------------------------
-- in an application where an external synchronization pulse is expected for every macrocyle,
-- the macrocyc_lgth is set slightly larger than the external synchronization period; therefore
-- th macrocycle counter should not be reaching zero; if it reaches zero, it means that the
-- external synchronization pulse did not arrive in time
-- Regarding synchronisation, the masterFIP application can work in two modes:
-- using an internal counter that counts each macrocycle based on the local oscillator, or
-- using the ext_sync_i pulse to signal the beginning of each macrocycle.
-- In an application where the external synchronization pulse is expected for every macrocycle,
-- the macrocyc_lgth is set slightly larger than the external synchronization period; therefore
-- the macrocycle counter should not be reaching zero; if it reaches zero, it means that the
-- external synchronization pulse did not arrive in time.
-- counter counting the macrocycle time
cmp_macrocycle_time_cnt
:
decr_counter
...
...
@@ -599,8 +595,9 @@ begin
counter_o
=>
macrocyc_cnt
,
counter_is_zero_o
=>
macrocyc_cnt_zero_p
);
-- -- -- -- -- -- -- -- -- -- --
macrocyc_load_p
<=
macrocyc_cnt_zero_p
or
macrocyc_host_load_p
or
ext_sync_p
;
macrocyc_load_p
<=
macrocyc_cnt_zero_p
or
macrocyc_host_load_p
or
ext_sync_p
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- counter counting the number of macrocycles; when it fills up it restarts
cmp_macrocycles_cnt
:
incr_counter
generic
map
(
g_counter_lgth
=>
32
)
...
...
@@ -610,13 +607,19 @@ begin
counter_reinit_i
=>
num_of_macrocyc_cnt_reinit
,
counter_is_full_o
=>
num_of_macrocyc_cnt_full
,
counter_o
=>
num_of_macrocyc_cnt
);
-- -- -- -- -- -- -- -- -- -- --
num_of_macrocyc_cnt_reinit
<=
core_rst_n
or
num_of_macrocyc_cnt_full
;
num_of_macrocyc_cnt_reinit
<=
core_rst_n
or
num_of_macrocyc_cnt_full
;
---------------------------------------------------------------------------------------------------
-- turnaround counter --
---------------------------------------------------------------------------------------------------
-- counter counting the turnaround time i.e. the time after the end of transmission of a frame
-- (tx_completed_p), or after the end of reception of a frame (rx_frame_ok_p/ rx_crc_wrong_p)
-- and before the transmission of a new frame.
-- Note that the MT core is using the turnar_cnt rather than the 1-clk-tick long counter_is_zero_o.
-- turnaround counter
cmp_turnaround_cnt
:
decr_counter
generic
map
(
width
=>
31
)
...
...
@@ -628,15 +631,18 @@ begin
counter_o
=>
turnar_cnt
,
counter_is_zero_o
=>
open
);
-- -- -- -- -- -- -- -- -- -- --
turnar_load_p
<=
tx_completed_p
or
rx_frame_ok_p
or
rx_crc_wrong_p
or
turnar_host_load_p
;
turnar_load_p
<=
tx_completed_p
or
rx_frame_ok_p
or
rx_crc_wrong_p
or
turnar_host_load_p
;
--------------------------------------------------------------------------------------------------
-- silence counter --
--------------------------------------------------------------------------------------------------
-- silence time: maximum amount of time that the masterFIP waits for a response frame.
-- the counting starts after an ID_DAT sent by the master (therefore loaded upon tx_completed_p)
-- or by the FES of an RP_DAT_MSG as a RP_FIN is expected afterwards
-- counter counting the silence time i.e. the maximum amount of time that the masterFIP waits for
-- a response frame; the counting starts after the transmission of a frame sent by the master
-- (tx_completed_p) or after the reception of a frame (rx_frame_ok_p/ rx_crc_wrong_p) for the
-- case of a RP_DAT_MSG that would be followed by P_FIN.
cmp_silence_cnt
:
decr_counter
generic
map
(
width
=>
31
)
port
map
...
...
@@ -647,7 +653,7 @@ begin
counter_o
=>
silen_cnt
,
counter_is_zero_o
=>
open
);
-- -- -- -- -- -- -- -- -- -- --
silen_load_p
<=
tx_completed_p
or
rx_frame_ok_p
or
rx_crc_wrong_p
or
silen_host_load_p
;
silen_load_p
<=
tx_completed_p
or
rx_frame_ok_p
or
rx_crc_wrong_p
or
silen_host_load_p
;
--------------------------------------------------------------------------------------------------
...
...
@@ -786,8 +792,13 @@ begin
---------------------------------------------------------------------------------------------------
-- FielDrive TXERR, WDGN --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- synchronisation of the fd_wdgn_i signal
-- The fd_wdgn_i is activated when the FielDrive detects TXD activity > 1024 bytes long;
-- it is deactivated with a FielDrive reset.
-- The following processes provide to the MT the macrocycle number when the fd_wdgn_i was activated.
-- Note that it is the logic running on the MT that is responsible for activating a fd_rst_o upon
-- the detection of a fd_wdg_act.
-- synch of the incoming fd_wdgn_i signal
cmp_fd_wdgn_i_pulse_detect
:
gc_sync_ffs
generic
map
(
g_sync_edge
=>
"positive"
)
port
map
...
...
@@ -798,7 +809,8 @@ begin
fd_wdg
<=
not
fd_wdgn_i
;
-- process that registers the activation of fd_wdgn_i and the macrocycle_cnt upon the activation;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- process that registers the activation of fd_wdgn_i and the macrocycle_cnt upon its activation;
-- the signals are reset upon a core_rst_n or a fd_host_rstn
p_fd_wdgn_capture
:
process
(
clk_i
)
begin
...
...
@@ -815,7 +827,9 @@ begin
end
if
;
end
process
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The fd_txerr_i is activated when the FielDrive detects an overload/underload; for example if
-- edge detection on the fd_txer_i signal
cmp_fd_txer_i_pulse_detect
:
gc_sync_ffs
generic
map
(
g_sync_edge
=>
"positive"
)
...
...
@@ -825,7 +839,8 @@ begin
data_i
=>
fd_txer_i
,
ppulse_o
=>
fd_txer_p
);
-- counter counting the number of fd_wdgn_p
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- counter counting the number of fd_txerr_p
cmp_fd_txer_cnt
:
incr_counter
generic
map
(
g_counter_lgth
=>
32
)
port
map
...
...
@@ -834,10 +849,11 @@ begin
counter_reinit_i
=>
fd_txer_cnt_reinit
,
counter_is_full_o
=>
open
,
counter_o
=>
fd_txer_cnt
);
-- -- -- -- -- -- -- -- -- -- --
fd_txer_cnt_reinit
<=
'1'
when
core_rst_n
=
'0'
or
macrocyc_load_p
=
'1'
or
fd_host_rst
=
'1'
else
'0'
;
fd_txer_cnt_reinit
<=
'1'
when
core_rst_n
=
'0'
or
macrocyc_load_p
=
'1'
or
fd_host_rst
=
'1'
else
'0'
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- process that registers the macrocycle_cnt value upon the last fd_txer_p of a macrocycle
p_fd_txer_capture
:
process
(
clk_i
)
begin
...
...
@@ -854,15 +870,19 @@ begin
end
if
;
end
process
;
---------------------------------------------------------------------------------------------------
-- DAC --
---------------------------------------------------------------------------------------------------
-- DAC --
---------------------------------------------------------------------------------------------------
-- Communication with the SPEC DAC AD5662BRM2 that controls the 20 MHz OSC2 which is the source of
-- the design's timing. Setting the DAC at its middle range maximized the oscillator's stability;
-- this is important for free-running applications that are not using the ext_sync_i
cmp_dac_config
:
spec_serial_dac_arb
generic
map
generic
map
(
g_invert_sclk
=>
false
,
g_num_extra_bits
=>
8
)
port
map
port
map
(
clk_i
=>
clk_i
,
rst_n_i
=>
core_rst_n
,
val1_i
=>
dac_value
,
...
...
@@ -871,92 +891,62 @@ begin
load2_i
=>
'0'
,
dac_cs_n_o
(
0
)
=>
dac_cs_n_o
(
0
),
dac_cs_n_o
(
1
)
=>
dac_cs_n_o
(
1
),
-- dac_clr_n_o => open,
dac_sclk_o
=>
dac_sclk_o
,
dac_din_o
=>
dac_din_o
);
---------------------------------------------------------------------------------------------------
-- DS18B20U one wire --
---------------------------------------------------------------------------------------------------
-- one wire --
---------------------------------------------------------------------------------------------------
cmp_temper_onewire
:
serialIdTempInt
generic
map
(
FREQ
=>
40
)
port
map
(
Clk
=>
clk_40m_i
,
RstN
=>
core_rst_n
,
SerialId
=>
carrier_onewire_b
,
Id
=>
temp_id
,
Temp
=>
temp_temper
,
IdRead
=>
onewire_read_p
,
Pps
=>
pps_is_zero
);
-- generate_1m_clk: process(clk_i, clk_1m)
-- begin
-- if rising_edge(clk_i) then
-- prescaler_counter <= prescaler_counter + 1;
-- if(prescaler_counter > prescaler) then
-- -- -- Iterate
-- clk_1m <= not clk_1m;
-- prescaler_counter <= (others => '0');
-- end if;
-- end if;
-- end process;
-- Communication with the 1-wire DS18B20U+ for the unique ID and temperature reading;
-- rather than sw bit-banging the whole 1-wire communication is implemented in vhdl, to simplify
-- drivers. Note that a temperature reading is provided every second, with the first one a couple
-- of sec after the board power-up/ reset.
cmp_onewire
:
onewire_interf
generic
map
(
freq
=>
100
)
port
map
(
clk_i
=>
clk_i
,
rst_n_i
=>
core_rst_n
,
onewire_b
=>
onewire_b
,
id_o
=>
tmp_id
,
temper_o
=>
tmp_temper
,
id_read_o
=>
onewire_read_p
,
pps_p_i
=>
pps_is_zero
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- pps generator based on the 100 MHz clk
cmp_pps_gen
:
wf_decr_counter
generic
map
(
g_counter_lgth
=>
2
6
)
generic
map
(
g_counter_lgth
=>
2
7
)
port
map
(
uclk_i
=>
clk_40m
_i
,
(
uclk_i
=>
clk
_i
,
counter_rst_i
=>
core_rst
,
counter_decr_i
=>
'1'
,
counter_load_i
=>
pps_load_p
,
counter_top_i
=>
"10011000100101101000000000"
,
-- 40000000 * 25 ns = 1s
counter_o
=>
open
,
counter_load_i
=>
pps_load_p
,
counter_top_i
=>
"101111101011110000100000000"
,
-- 100'000'000
counter_is_zero_o
=>
pps_is_zero
);
-- -- -- -- -- -- -- -- -- -- --
pps_load_p
<=
pps_is_zero
or
core_rst
;
latch
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
temper
<=
(
others
=>
'0'
);
id
<=
(
others
=>
'0'
);
if
(
onewire_read_p
=
'1'
)
then
temper
<=
temp_temper
;
id
<=
temp_id
;
end
if
;
end
if
;
end
process
;
cmp_ow_read_p
:
gc_extend_pulse
generic
map
(
g_width
=>
1000000
)
-- ns -> ms
port
map
(
clk_i
=>
clk_40m_i
,
rst_n_i
=>
core_rst_n
,
pulse_i
=>
onewire_read_p
,
extended_o
=>
aux_o
(
2
));
pps_load_p
<=
pps_is_zero
;
-- looping
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- registering of the read values
reg_reading
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
temper
<=
(
others
=>
'0'
);
id
<=
(
others
=>
'0'
);
if
(
onewire_read_p
=
'1'
)
then
temper
<=
tmp_temper
;
id
<=
tmp_id
;
end
if
;
end
if
;
end
process
;
cmp_ow_pps_p
:
gc_extend_pulse
generic
map
(
g_width
=>
1000000
)
-- ns -> ms
port
map
(
clk_i
=>
clk_40m_i
,
rst_n_i
=>
core_rst_n
,
pulse_i
=>
pps_is_zero
,
extended_o
=>
aux_o
(
3
));
-- cmp_temper_onewire: temperature
-- port map
-- (clk1m => clk_1m,
-- temper => temp_temper,
-- wireout=> carrier_onewire_b);
---------------------------------------------------------------------------------------------------
--
LEDs
--
--
LEDs & aux
--
---------------------------------------------------------------------------------------------------
cmp_out_of_sync_led
:
gc_extend_pulse
generic
map
...
...
@@ -967,7 +957,7 @@ begin
pulse_i
=>
macrocyc_cnt_zero_p
,
extended_o
=>
out_of_sync_led
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sync_led
:
gc_extend_pulse
generic
map
(
g_width
=>
1000000
)
...
...
@@ -977,55 +967,34 @@ begin
pulse_i
=>
ext_sync_p
,
extended_o
=>
sync_led
);
---------------------------------------------------------------------------------------------------
-- aux --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
aux_o
(
7
)
<=
out_of_sync_led
;
aux_o
(
6
)
<=
mf_dbg_p_ext
;
--macrocyc_host_load_p;
aux_o
(
5
)
<=
mf_dbg
(
5
);
--macrocyc_load_p;
aux_o
(
4
)
<=
mf_dbg
(
4
);
--rx_byte_ready_p;
--aux_o(3) <= mf_dbg(3);
--macrocyc_cnt_zero_p;
--aux_o(2) <= mf_dbg(2);--core_rst;--ext_sync_p;
--tx_completed;
aux_o
(
1
)
<=
onewire_read_p
;
--mf_dbg(1);
--tx_start;
aux_o
(
0
)
<=
pps_is_zero
;
--mf_dbg(0);
--sync_led;
aux_o
(
6
)
<=
mf_dbg_p_ext
;
aux_o
(
5
)
<=
mf_dbg
(
5
);
aux_o
(
4
)
<=
mf_dbg
(
4
);
--rx_byte_ready_p;
aux_o
(
3
)
<=
mf_dbg
(
3
);
--macrocyc_cnt_zero_p;
aux_o
(
2
)
<=
mf_dbg
(
2
);
--tx_completed;
aux_o
(
1
)
<=
mf_dbg
(
1
);
--tx_start;
aux_o
(
0
)
<=
mf_dbg
(
0
);
--sync_led;
ext_sync_oe_o
<=
ext_sync_oe
;
-- edge detection on the mf_dbg signal
-- cmp_mf_dbg_pulse_detect: gc_sync_ffs
-- generic map(g_sync_edge => "positive")
-- port map
-- (clk_i => clk_i,
-- rst_n_i => rst_n,
-- data_i => mf_dbg,
-- ppulse_o => mf_dbg_p);
-- extension of the mf_dbg_p to capture it easier on the scope
-- cmp_mf_dbg_p_extend : gc_extend_pulse
-- generic map (g_width => 32) -- 32 ticks long
-- port map
-- (clk_i => clk_i,
-- rst_n_i => core_rst_n,
-- pulse_i => mf_dbg_p,
-- extended_o => mf_dbg_p_ext);
---------------------------------------------------------------------------------------------------
-- CHIPSCOPE --
---------------------------------------------------------------------------------------------------
-- chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_i,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
-- chipscope_ila_1 : chipscope_ila
-- port map (
-- CONTROL => CONTROL,
-- CLK => clk_i,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
-- chipscope_icon_1 : chipscope_icon
-- port map ( CONTROL0 => CONTROL);
-- port map ( CONTROL0 => CONTROL);
-- TRIG0(8 downto 0) <= tx_bytes_num;
-- TRIG0(9) <= tx_start;
...
...
@@ -1036,9 +1005,8 @@ begin
-- TRIG0(29) <= fd_txena;
-- TRIG0(30) <= fd_txd;
-- TRIG0(31) <= fd_txck;
-- TRIG1 <= tx_frame(0);
-- TRIG1(15 downto 8) <= rx_byte_index;
-- TRIG2(8 downto 0) <= rx_byte_index;
-- TRIG2(9) <= rx_fss_received_p;
-- TRIG2(10) <= rx_byte_ready_p;
...
...
@@ -1046,27 +1014,9 @@ begin
-- TRIG2(26 downto 19) <= rx_ctrl_byte;
-- TRIG2(27) <= rx_frame_ok_p;
-- TRIG2(28) <= rx_crc_wrong_p;
-- TRIG2(29) <= core_rst;
-- TRIG2(31 downto 30) <= speed_b1_i & speed_b0_i;
-- TRIG3 <= rx_frame(0);
--TRIG0(17) <= tx_start_p;
--TRIG0(18) <= rx_fss_crc_fes_ok_p;
--TRIG0(19) <= start_tx_p;
--TRIG0(21) <= rx_fss_crc_fes_ok_p;
--TRIG0(22) <= rx_fss_received_p;
--TRIG0(23) <= rx_crc_wrong_p;
--TRIG1(15 downto 8) <= rx_byte_index;
--TRIG0(16) <= start_from_fpga;
--TRIG0(24 downto 17) <= retrig_nb_offset(7 downto 0);
--TRIG0(31 downto 25) <= clk_i_cycles_offset(6 downto 0);
end
rtl
;
----------------------------------------------------------------------------------------------------
-- architecture ends
...
...
rtl/masterFIP_pkg.vhd
View file @
5ea0f26e
...
...
@@ -395,11 +395,10 @@ package masterFIP_pkg is
values_for_simul
:
boolean
:
=
FALSE
);
port
(
clk_i
:
in
std_logic
;
clk_40m_i
:
in
std_logic
;
-- 40 MHz clock
rst_i
:
in
std_logic
;
speed_b0_i
:
in
std_logic
;
speed_b1_i
:
in
std_logic
;
carrier_onewire_b
:
inout
std_logic
;
onewire_b
:
inout
std_logic
;
fd_rxcdn_i
:
in
std_logic
;
fd_rxd_i
:
in
std_logic
;
fd_txer_i
:
in
std_logic
;
...
...
@@ -454,25 +453,24 @@ port
end
component
;
component
serialIdTempInt
is
component
onewire_interf
is
generic
(
FREQ
:
integer
:
=
40
--Frequency in MHz
freq
:
integer
:
=
40
--Frequency in MHz
);
port
(
Clk
:
in
std_logic
;
RstN
:
in
std_logic
;
SerialId
:
inout
std_logic
;
-- IO to be connected to the chip (DS1822)
Id
:
out
std_logic_vector
(
63
downto
0
);
-- ID value
Temp
:
out
std_logic_vector
(
15
downto
0
);
-- Temperature value (refreshed every second)
IdRead
:
out
std_logic
;
-- ID value is valid
Pps
:
in
std_logic
;
-- Pulse per second (for temperature read)
IdOk
:
out
std_logic
-- Same as IdRead, but not reset with RstN !!
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
onewire_b
:
inout
std_logic
;
-- IO to be connected to the chip (DS1822)
id_o
:
out
std_logic_vector
(
63
downto
0
);
-- ID value
temper_o
:
out
std_logic_vector
(
15
downto
0
);
-- Temperature value (refreshed every second)
id_read_o
:
out
std_logic
;
-- ID value is valid
pps_p_i
:
in
std_logic
;
-- Pulse per second (for temperature read)
id_ok_o
:
out
std_logic
-- Same as IdRead, but not reset with RstN !!
);
end
component
;
---------------------------------------------------------------------------------------------------
component
carrier_info
port
...
...
rtl/onewire_interf.vhd
0 → 100644
View file @
5ea0f26e
---------------------------------------------------------------------------------------------------
-- |
-- one wire temperature unique id interface |
-- |
---------------------------------------------------------------------------------------------------
-- File onewire_interf.vhd |
-- |
-- Description Interface with the serial ID+Thermometer DS1822, DS1820 |
-- Notes: Started from the DS2401 interface. |
-- |
-- Authors Pablo Antonio Alvarez Sanchez |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
library
IEEE
;
use
IEEE
.
std_logic_1164
.
all
;
use
IEEE
.
NUMERIC_STD
.
all
;
--=================================================================================================
-- Entity declaration for fmc_masterFIP_core
--=================================================================================================
entity
onewire_interf
is
generic
(
freq
:
integer
:
=
40
);
-- clk frequency in MHz
port
(
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
onewire_b
:
inout
std_logic
;
-- IO to be connected to the chip(DS1820/DS1822)
id_o
:
out
std_logic_vector
(
63
downto
0
);
-- id_o value
temper_o
:
out
std_logic_vector
(
15
downto
0
);
-- temperature value (refreshed every second)
id_read_o
:
out
std_logic
;
-- id_o value is valid_o
pps_p_i
:
in
std_logic
;
-- Pulse per second (for temp_oerature read)
id_ok_o
:
out
std_logic
);
-- Same as id_read_o, but not reset with rst_n_i
end
onewire_interf
;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture
rtl
of
onewire_interf
is
-- time slot constants according to specs https://www.maximintegrated.com/en/app-notes/index.mvp/id/162
constant
SLOT_CNT_START
:
unsigned
(
15
downto
0
)
:
=
to_unsigned
(
0
*
freq
/
40
,
16
);
constant
SLOT_CNT_START_PLUSONE
:
unsigned
(
15
downto
0
)
:
=
SLOT_CNT_START
+
1
;
constant
SLOT_CNT_SET
:
unsigned
(
15
downto
0
)
:
=
to_unsigned
(
60
*
freq
/
40
,
16
);
constant
SLOT_CNT_RD
:
unsigned
(
15
downto
0
)
:
=
to_unsigned
(
600
*
freq
/
40
,
16
);
constant
SLOT_CNT_STOP
:
unsigned
(
15
downto
0
)
:
=
to_unsigned
(
3600
*
freq
/
40
,
16
);
constant
SLOT_CNT_PRESTOP
:
unsigned
(
15
downto
0
)
:
=
to_unsigned
((
3600-60
)
*
freq
/
40
,
16
);
constant
READ_ID_HEADER
:
std_logic_vector
(
7
downto
0
)
:
=
X"33"
;
constant
CONVERT_HEADER
:
std_logic_vector
(
7
downto
0
)
:
=
X"44"
;
constant
READ_TEMPER_HEADER
:
std_logic_vector
(
7
downto
0
)
:
=
X"BE"
;
constant
SKIPHEADER
:
std_logic_vector
(
7
downto
0
)
:
=
X"CC"
;
constant
ID_LEFT
:
integer
:
=
71
;
constant
ID_RIGHT
:
integer
:
=
8
;
constant
TEMPER_LEFT
:
integer
:
=
15
;
constant
TEMPER_RIGHT
:
integer
:
=
0
;
constant
TEMPER_DONE_BIT
:
std_logic
:
=
'0'
;
-- The serial line is asserted to this value by the
-- DS1820/DS1822 when the temperature conversion is ready
constant
TEMPER_LGTH
:
unsigned
(
7
downto
0
)
:
=
to_unsigned
(
72
,
8
);
constant
ID_LGTH
:
unsigned
(
7
downto
0
)
:
=
to_unsigned
(
64
,
8
);
type
op_fsm_t
is
(
READ_ID_OP
,
SKIP_ROM_OP1
,
CONV_OP1
,
CONV_OP2
,
SKIP_ROM_OP2
,
READ_TEMP_OP
);
type
cm_fsm_t
is
(
RST_CM
,
PREP_WR_CM
,
WR_CM
,
PREP_RD_CM
,
RD_CM
,
IDLE_CM
);
signal
bit_top
,
bit_cnt
:
unsigned
(
7
downto
0
);
signal
do_read_bit
,
do_write_bit
,
do_rst
:
std_logic
;
signal
slot_cnt
:
unsigned
(
15
downto
0
);
signal
start_p
,
end_p
,
set_value
,
read_value
,
init_pulse
:
std_logic
;
signal
state_op
,
nxt_state_op
:
op_fsm_t
;
signal
state_cm
,
nxt_state_cm
:
cm_fsm_t
;
signal
crc_vec
,
header
:
std_logic_vector
(
7
downto
0
);
signal
crc_ok
,
init
,
pre_read_p
,
i_id_read
:
std_logic
;
signal
load_temper
,
load_id
,
cm_only
,
pps_p_d
:
std_logic
;
signal
serial_id_out
,
nx_serial_id_out
,
nx_serial_id_oe
:
std_logic
;
signal
i_serial_id_oe
,
serial_idr
:
std_logic
;
signal
end_wr_cm
,
end_rd_cm
,
inc_bit_cnt
,
rst_bit_cnt
:
std_logic
;
signal
shift_header
,
id_cm_reg
:
std_logic
;
signal
cm_reg
:
std_logic_vector
(
71
downto
0
);
signal
shifted_header
:
std_logic_vector
(
7
downto
0
);
signal
pre_init_p
:
std_logic
;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Serial data line in tri-state, when not writing data out
onewire_b
<=
serial_id_out
when
i_serial_id_oe
=
'1'
else
'Z'
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- pps_p_i 1 clock tick delay
pps_p_iDelay
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
pps_p_d
<=
pps_p_i
;
end
if
;
end
process
;
---------------------------------------------------------------------------------------------------
-- operations FSM --
---------------------------------------------------------------------------------------------------
op_fsm_transitions
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
state_op
<=
READ_ID_OP
;
else
state_op
<=
nxt_state_op
;
end
if
;
end
if
;
end
process
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
op_fsm_states
:
process
(
state_op
,
pps_p_i
,
crc_ok
)
begin
nxt_state_op
<=
READ_ID_OP
;
case
state_op
is
when
READ_ID_OP
=>
if
pps_p_i
=
'1'
and
crc_ok
=
'1'
then
nxt_state_op
<=
CONV_OP1
;
else
nxt_state_op
<=
state_op
;
end
if
;
when
CONV_OP1
=>
if
pps_p_i
=
'1'
then
nxt_state_op
<=
SKIP_ROM_OP1
;
else
nxt_state_op
<=
state_op
;
end
if
;
when
SKIP_ROM_OP1
=>
if
pps_p_i
=
'1'
then
nxt_state_op
<=
READ_TEMP_OP
;
else
nxt_state_op
<=
state_op
;
end
if
;
when
READ_TEMP_OP
=>
if
pps_p_i
=
'1'
then
nxt_state_op
<=
SKIP_ROM_OP2
;
else
nxt_state_op
<=
state_op
;
end
if
;
when
SKIP_ROM_OP2
=>
if
pps_p_i
=
'1'
then
nxt_state_op
<=
CONV_OP2
;
else
nxt_state_op
<=
state_op
;
end
if
;
when
CONV_OP2
=>
if
pps_p_i
=
'1'
then
nxt_state_op
<=
SKIP_ROM_OP1
;
else
nxt_state_op
<=
state_op
;
end
if
;
end
case
;
end
process
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
op_fsm_outputs
:
process
(
state_op
,
state_cm
,
crc_ok
,
pps_p_i
,
cm_only
)
begin
header
<=
READ_ID_HEADER
;
bit_top
<=
ID_LGTH
;
load_temper
<=
'0'
;
load_id
<=
'0'
;
cm_only
<=
'0'
;
case
state_op
is
when
READ_ID_OP
=>
header
<=
READ_ID_HEADER
;
bit_top
<=
ID_LGTH
;
if
state_cm
=
IDLE_CM
then
load_id
<=
crc_ok
;
end
if
;
when
CONV_OP1
=>
header
<=
CONVERT_HEADER
;
cm_only
<=
'1'
;
when
SKIP_ROM_OP1
=>
header
<=
SKIPHEADER
;
cm_only
<=
'1'
;
when
READ_TEMP_OP
=>
header
<=
READ_TEMPER_HEADER
;
bit_top
<=
TEMPER_LGTH
;
if
state_cm
=
IDLE_CM
then
load_temper
<=
crc_ok
and
pps_p_i
;
end
if
;
when
SKIP_ROM_OP2
=>
header
<=
SKIPHEADER
;
cm_only
<=
'1'
;
when
CONV_OP2
=>
header
<=
CONVERT_HEADER
;
cm_only
<=
'1'
;
when
others
=>
null
;
end
case
;
end
process
;
---------------------------------------------------------------------------------------------------
-- commands FSM --
---------------------------------------------------------------------------------------------------
cm_fsm_transitions
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
state_cm
<=
RST_CM
;
else
state_cm
<=
nxt_state_cm
;
end
if
;
end
if
;
end
process
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cm_fsm_states
:
process
(
state_cm
,
start_p
,
end_wr_cm
,
end_rd_cm
,
crc_ok
,
state_op
,
cm_only
,
pps_p_d
)
begin
nxt_state_cm
<=
RST_CM
;
case
state_cm
is
when
RST_CM
=>
if
start_p
=
'1'
then
nxt_state_cm
<=
PREP_WR_CM
;
else
nxt_state_cm
<=
state_cm
;
end
if
;
when
PREP_WR_CM
=>
if
start_p
=
'1'
then
nxt_state_cm
<=
WR_CM
;
else
nxt_state_cm
<=
state_cm
;
end
if
;
when
WR_CM
=>
if
end_wr_cm
=
'1'
then
if
cm_only
=
'0'
then
nxt_state_cm
<=
PREP_RD_CM
;
else
nxt_state_cm
<=
IDLE_CM
;
end
if
;
else
nxt_state_cm
<=
state_cm
;
end
if
;
when
PREP_RD_CM
=>
if
start_p
=
'1'
then
nxt_state_cm
<=
RD_CM
;
else
nxt_state_cm
<=
state_cm
;
end
if
;
when
RD_CM
=>
if
end_rd_cm
=
'1'
then
nxt_state_cm
<=
IDLE_CM
;
else
nxt_state_cm
<=
state_cm
;
end
if
;
when
IDLE_CM
=>
if
state_op
=
READ_ID_OP
then
if
crc_ok
=
'0'
then
nxt_state_cm
<=
RST_CM
;
else
nxt_state_cm
<=
state_cm
;
end
if
;
elsif
state_op
=
READ_TEMP_OP
then
-- At this moment I will send a Conv temper_o command
if
pps_p_d
=
'1'
then
nxt_state_cm
<=
PREP_WR_CM
;
else
nxt_state_cm
<=
state_cm
;
end
if
;
elsif
(
state_op
=
CONV_OP1
)
or
(
state_op
=
CONV_OP2
)
then
-- At this moment I will restart a temper_o read
if
pps_p_d
=
'1'
then
nxt_state_cm
<=
PREP_WR_CM
;
else
nxt_state_cm
<=
state_cm
;
end
if
;
elsif
(
state_op
=
SKIP_ROM_OP1
)
or
(
state_op
=
SKIP_ROM_OP2
)
then
-- At this moment I will restart
if
pps_p_d
=
'1'
then
nxt_state_cm
<=
RST_CM
;
else
nxt_state_cm
<=
state_cm
;
end
if
;
else
nxt_state_cm
<=
state_cm
;
end
if
;
end
case
;
end
process
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cm_fsm_outputs
:
process
(
state_cm
,
bit_cnt
,
pre_read_p
,
crc_vec
,
start_p
,
shifted_header
,
init_pulse
,
read_value
,
pre_init_p
)
begin
inc_bit_cnt
<=
'0'
;
nx_serial_id_out
<=
'0'
;
shift_header
<=
'0'
;
id_cm_reg
<=
'0'
;
nx_serial_id_oe
<=
'0'
;
rst_bit_cnt
<=
'0'
;
init
<=
'0'
;
crc_ok
<=
'0'
;
case
state_cm
is
when
RST_CM
=>
rst_bit_cnt
<=
'1'
;
nx_serial_id_out
<=
'0'
;
nx_serial_id_oe
<=
'1'
;
init
<=
start_p
;
when
PREP_WR_CM
=>
rst_bit_cnt
<=
start_p
;
nx_serial_id_oe
<=
'0'
;
nx_serial_id_out
<=
'0'
;
when
WR_CM
=>
shift_header
<=
start_p
;
inc_bit_cnt
<=
start_p
;
rst_bit_cnt
<=
'0'
;
nx_serial_id_out
<=
shifted_header
(
0
)
and
(
not
init_pulse
);
if
bit_cnt
<
to_unsigned
(
7
,
bit_cnt
'length
)
then
nx_serial_id_oe
<=
not
pre_init_p
;
else
nx_serial_id_oe
<=
not
pre_read_p
;
end
if
;
when
PREP_RD_CM
=>
rst_bit_cnt
<=
start_p
;
nx_serial_id_oe
<=
'0'
;
nx_serial_id_out
<=
'0'
;
when
RD_CM
=>
inc_bit_cnt
<=
start_p
;
rst_bit_cnt
<=
'0'
;
nx_serial_id_out
<=
not
init_pulse
;
id_cm_reg
<=
read_value
;
nx_serial_id_oe
<=
init_pulse
;
when
IDLE_CM
=>
if
crc_vec
=
x"00"
then
crc_ok
<=
'1'
;
else
crc_ok
<=
'0'
;
end
if
;
init
<=
'1'
;
end
case
;
end
process
;
---------------------------------------------------------------------------------------------------
-- time slots --
---------------------------------------------------------------------------------------------------
-- Generates time slots
-- Reset pulse
-- Read time slot
-- Write time slots
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
slot_cnt
(
slot_cnt
'left
)
<=
'1'
;
slot_cnt
(
slot_cnt
'left
-1
downto
0
)
<=
(
others
=>
'0'
);
start_p
<=
'0'
;
end_p
<=
'0'
;
set_value
<=
'0'
;
read_value
<=
'0'
;
init_pulse
<=
'0'
;
pre_init_p
<=
'0'
;
pre_read_p
<=
'0'
;
else
-- Slot counter
if
init
=
'1'
then
slot_cnt
(
slot_cnt
'left
)
<=
'1'
;
slot_cnt
(
slot_cnt
'left
-
1
downto
0
)
<=
(
others
=>
'0'
);
elsif
slot_cnt
=
SLOT_CNT_STOP
then
slot_cnt
<=
(
others
=>
'0'
);
else
slot_cnt
<=
slot_cnt
+
1
;
end
if
;
-- Time slot start pulse
if
slot_cnt
=
SLOT_CNT_START
then
start_p
<=
'1'
;
else
start_p
<=
'0'
;
end
if
;
if
((
slot_cnt
>
SLOT_CNT_START
)
and
(
slot_cnt
<
SLOT_CNT_SET
))
then
init_pulse
<=
'1'
;
else
init_pulse
<=
'0'
;
end
if
;
if
((
slot_cnt
>
SLOT_CNT_PRESTOP
)
and
(
slot_cnt
<
SLOT_CNT_STOP
))
then
pre_init_p
<=
'1'
;
else
pre_init_p
<=
'0'
;
end
if
;
if
(((
slot_cnt
>
SLOT_CNT_PRESTOP
)
and
(
slot_cnt
<=
SLOT_CNT_STOP
))
or
(
slot_cnt
<=
SLOT_CNT_START_PLUSONE
))
then
pre_read_p
<=
'1'
;
else
pre_read_p
<=
'0'
;
end
if
;
-- End of time slot pulse
if
slot_cnt
=
SLOT_CNT_START
then
end_p
<=
'1'
;
else
end_p
<=
'0'
;
end
if
;
-- Pulse to write value on serial link
if
slot_cnt
=
SLOT_CNT_SET
then
set_value
<=
'1'
;
else
set_value
<=
'0'
;
end
if
;
-- Pulse to read value on serial link
if
slot_cnt
=
SLOT_CNT_RD
then
read_value
<=
'1'
;
else
read_value
<=
'0'
;
end
if
;
end
if
;
end
if
;
end
process
;
---------------------------------------------------------------------------------------------------
-- serdes --
---------------------------------------------------------------------------------------------------
-- Data serializer bit counter
BitCnt_p
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
bit_cnt
<=
(
others
=>
'0'
);
else
if
rst_bit_cnt
=
'1'
then
bit_cnt
<=
(
others
=>
'0'
);
elsif
inc_bit_cnt
=
'1'
then
bit_cnt
<=
bit_cnt
+
1
;
end
if
;
end
if
;
end
if
;
end
process
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Data serializer shift register
ShiftReg_p
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
shifted_header
<=
READ_ID_HEADER
;
cm_reg
<=
(
others
=>
'0'
);
serial_idr
<=
'0'
;
serial_id_out
<=
'0'
;
i_serial_id_oe
<=
'0'
;
id_o
<=
(
others
=>
'0'
);
i_id_read
<=
'0'
;
id_read_o
<=
'0'
;
crc_vec
<=
(
others
=>
'0'
);
temper_o
<=
(
others
=>
'0'
);
else
-- Samples serial input
serial_idr
<=
onewire_b
;
-- Shifts command out
if
init
=
'1'
then
shifted_header
<=
header
;
elsif
shift_header
=
'1'
then
shifted_header
(
shifted_header
'left
-1
downto
0
)
<=
shifted_header
(
shifted_header
'left
downto
1
);
shifted_header
(
shifted_header
'left
)
<=
'0'
;
end
if
;
-- Computes CRC on read data (include the received CRC itself, if no errror crc_vec = X"00")
if
init
=
'1'
then
crc_vec
<=
(
others
=>
'0'
);
elsif
id_cm_reg
=
'1'
then
crc_vec
(
0
)
<=
serial_idr
xor
crc_vec
(
7
);
crc_vec
(
3
downto
1
)
<=
crc_vec
(
2
downto
0
);
crc_vec
(
4
)
<=
(
serial_idr
xor
crc_vec
(
7
))
xor
crc_vec
(
3
);
crc_vec
(
5
)
<=
(
serial_idr
xor
crc_vec
(
7
))
xor
crc_vec
(
4
);
crc_vec
(
7
downto
6
)
<=
crc_vec
(
6
downto
5
);
end
if
;
-- Stores incoming data
if
(
id_cm_reg
=
'1'
)
then
cm_reg
(
cm_reg
'left
-
1
downto
0
)
<=
cm_reg
(
cm_reg
'left
downto
1
);
cm_reg
(
cm_reg
'left
)
<=
serial_idr
;
end
if
;
-- Updates serial output data
serial_id_out
<=
nx_serial_id_out
;
-- Updates serial output enable
i_serial_id_oe
<=
nx_serial_id_oe
;
-- Stores id_o in register
if
(
load_id
=
'1'
)
then
i_id_read
<=
'1'
;
id_o
<=
cm_reg
(
ID_LEFT
downto
ID_RIGHT
);
end
if
;
-- Stores temp_oerature in register
if
(
load_temper
=
'1'
)
then
temper_o
<=
cm_reg
(
TEMPER_LEFT
downto
TEMPER_RIGHT
);
end
if
;
-- Delays id_o read
id_read_o
<=
i_id_read
;
end
if
;
end
if
;
end
process
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Value on id_o port is valid_o
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
state_cm
=
IDLE_CM
then
id_ok_o
<=
crc_ok
;
end
if
;
end
if
;
end
process
;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Detects end of read or end of write command
end_wr_cm
<=
'1'
when
(
bit_cnt
=
to_unsigned
(
7
,
bit_cnt
'length
))
and
(
inc_bit_cnt
=
'1'
)
else
'0'
;
end_rd_cm
<=
'1'
when
(
bit_cnt
=
bit_top
)
else
'0'
;
end
rtl
;
rtl/serialIdTempInt.vhd
deleted
100644 → 0
View file @
89953bc8
--==============================================================--
--Design Units : Ctr
--Size:
--Speed:
--File Name: CtrOutRem.vhd
--
--Purpose: Interface with the serial ID+Termometre DS1822
--
--Limitations:
--
--Errors:
--
--Libraries:
--
--Dependancies:
--
--Author: Pablo Antonio Alvarez Sanchez
-- European Organisation for Nuclear Research
-- AB -- Control -- Timing Division
-- CERN, Geneva, Switzerland, CH-1211
-- Building 864 Room 1 - A11
--
--Simulator:
--==============================================================--
--Revision List
--Version Author Date Changes
--
--1.0 palvarez Start from the interface for the DS2401.
-- Change Id Header to 0x"33" and add temperature request.
--1.1 palvarez Fixed bug on the state machine. It was sending a constant header
-- waitConvOp state removed
--1.2 palvarez Fixed bug on reset pulse
--1.3 palvarez Fixed bug skip command.
--1.4 palvarez Removed reset from conv and read temp commands. Added frequency generic
--1.5 mcattin 20.10.2009 Add comments, change to NUMERIC_STD library, delay pps 1 tick for the command FSM transitions
--1.6 mcattin 21.10.2009 Temp port size 16 bits (instead of 32), shift register was to small (64 bits)
-- to hold all data when reading temperature (increased to 72 bits)
--
--==============================================================--
library
IEEE
;
use
IEEE
.
STD_LOGIC_1164
.
all
;
use
IEEE
.
NUMERIC_STD
.
all
;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity
serialIdTempInt
is
generic
(
FREQ
:
integer
:
=
40
--Frequency in MHz
);
port
(
Clk
:
in
std_logic
;
RstN
:
in
std_logic
;
SerialId
:
inout
std_logic
;
-- IO to be connected to the chip (DS1822)
Id
:
out
std_logic_vector
(
63
downto
0
);
-- ID value
Temp
:
out
std_logic_vector
(
15
downto
0
);
-- Temperature value (refreshed every second)
IdRead
:
out
std_logic
;
-- ID value is valid
Pps
:
in
std_logic
;
-- Pulse per second (for temperature read)
IdOk
:
out
std_logic
-- Same as IdRead, but not reset with RstN !!
);
end
serialIdTempInt
;
architecture
rtl
of
serialIdTempInt
is
type
stateOperationsType
is
(
readIdOp
,
skipRomOp1
,
convertOp1
,
convertOp2
,
skipRomOp2
,
readTempOp
);
type
stateCommandType
is
(
resetCm
,
prepWriteCm
,
writeCm
,
prepReadCm
,
readCm
,
idleCm
);
-- resetConv, prepWriteConv, writeConv, readConv,
-- resetTemp prepWriteTemp,writeTemp,prepReadTemp,ReadTemp,idleTemp);
type
stateBitType
is
(
synPulseBit
,
holdBit
,
idleBit
);
constant
slotCounterSTART
:
unsigned
(
15
downto
0
)
:
=
to_unsigned
(
0
*
FREQ
/
40
,
16
);
constant
slotCounterSTARTPLUSONE
:
unsigned
(
15
downto
0
)
:
=
slotCounterSTART
+
1
;
constant
slotCounterSET
:
unsigned
(
15
downto
0
)
:
=
to_unsigned
(
60
*
FREQ
/
40
,
16
);
constant
slotCounterREAD
:
unsigned
(
15
downto
0
)
:
=
to_unsigned
(
600
*
FREQ
/
40
,
16
);
constant
slotCounterSTOP
:
unsigned
(
15
downto
0
)
:
=
to_unsigned
(
3600
*
FREQ
/
40
,
16
);
constant
slotCounterPRESTOP
:
unsigned
(
15
downto
0
)
:
=
to_unsigned
((
3600-60
)
*
FREQ
/
40
,
16
);
constant
READIDHEADER
:
std_logic_vector
(
7
downto
0
)
:
=
X"33"
;
constant
CONVERTHEADER
:
std_logic_vector
(
7
downto
0
)
:
=
X"44"
;
constant
READTEMPHEADER
:
std_logic_vector
(
7
downto
0
)
:
=
X"BE"
;
constant
SKIPHEADER
:
std_logic_vector
(
7
downto
0
)
:
=
X"CC"
;
constant
IDLEFT
:
integer
:
=
71
;
constant
IDRIGHT
:
integer
:
=
8
;
constant
TEMPLEFT
:
integer
:
=
15
;
constant
TEMPRIGHT
:
integer
:
=
0
;
constant
TEMPDONEBIT
:
std_logic
:
=
'0'
;
-- The serial line is asserted to this value
-- by the ds1822 when the temperature conversion is ready
constant
TEMPLENGTH
:
unsigned
(
7
downto
0
)
:
=
to_unsigned
(
72
,
8
);
constant
IDLENGTH
:
unsigned
(
7
downto
0
)
:
=
to_unsigned
(
64
,
8
);
signal
bitTop
:
unsigned
(
7
downto
0
);
signal
doReadBit
,
doWriteBit
,
doReset
:
std_logic
;
signal
slotCounter
:
unsigned
(
15
downto
0
);
signal
startPulse
,
endPulse
,
setValue
,
readValue
,
initPulse
:
std_logic
;
signal
stateOp
,
nxStateOp
:
stateOperationsType
;
signal
stateCm
,
nxStateCm
:
stateCommandType
;
signal
stateBit
,
nxStateBit
:
stateBitType
;
signal
bitCounter
:
unsigned
(
7
downto
0
);
signal
serialIdOut
,
iserialIdOe
,
nxSerialIdOut
,
nxSerialIdOe
:
std_logic
;
signal
serialIdr
:
std_logic
;
signal
endWriteCm
,
endReadCm
:
std_logic
;
signal
incBitCnt
,
resetBitCnt
:
std_logic
;
signal
shiftHeader
,
ldCmRg
:
std_logic
;
signal
cmRg
:
std_logic_vector
(
71
downto
0
);
signal
shiftedHeader
:
std_logic_vector
(
7
downto
0
);
signal
preInitPulse
:
std_logic
;
signal
CrcVec
,
C
:
std_logic_vector
(
7
downto
0
);
signal
crcOk
,
init
,
preReadPulse
:
std_logic
;
signal
D
:
std_logic_vector
(
55
downto
0
);
signal
iIdRead
:
std_logic
;
signal
header
:
std_logic_vector
(
7
downto
0
);
signal
loadTemp
,
loadId
:
std_logic
;
signal
commandOnly
:
std_logic
;
signal
pps_d
:
std_logic
;
begin
------------------------------------------------------------------------------
-- Serial data line
-- In tri-state, when not writing data out
SerialId
<=
serialIdOut
when
iserialIdOe
=
'1'
else
'Z'
;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- PPS 1 clock tick delay
PpsDelay_p
:
process
(
Clk
)
begin
if
rising_edge
(
Clk
)
then
pps_d
<=
Pps
;
end
if
;
end
process
PpsDelay_p
;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Operations state machine
OpFsmTransition_p
:
process
(
Clk
)
begin
if
rising_edge
(
Clk
)
then
if
RstN
=
'0'
then
stateOp
<=
readIdOp
;
else
stateOp
<=
nxStateOp
;
end
if
;
end
if
;
end
process
OpFsmTransition_p
;
OpFsmStates_p
:
process
(
stateOp
,
Pps
,
crcOk
)
begin
nxStateOp
<=
readIdOp
;
case
stateOp
is
when
readIdOp
=>
if
Pps
=
'1'
and
crcOk
=
'1'
then
nxStateOp
<=
convertOp1
;
else
nxStateOp
<=
stateOp
;
end
if
;
when
convertOp1
=>
if
Pps
=
'1'
then
nxStateOp
<=
skipRomOp1
;
else
nxStateOp
<=
stateOp
;
end
if
;
when
skipRomOp1
=>
if
Pps
=
'1'
then
nxStateOp
<=
readTempOp
;
else
nxStateOp
<=
stateOp
;
end
if
;
when
readTempOp
=>
if
Pps
=
'1'
then
nxStateOp
<=
skipRomOp2
;
else
nxStateOp
<=
stateOp
;
end
if
;
when
skipRomOp2
=>
if
Pps
=
'1'
then
nxStateOp
<=
convertOp2
;
else
nxStateOp
<=
stateOp
;
end
if
;
when
convertOp2
=>
if
Pps
=
'1'
then
nxStateOp
<=
skipRomOp1
;
else
nxStateOp
<=
stateOp
;
end
if
;
end
case
;
end
process
OpFsmStates_p
;
OpFsmOutputs_p
:
process
(
stateOp
,
stateCm
,
crcOk
,
pps
,
commandOnly
)
begin
header
<=
READIDHEADER
;
bitTop
<=
IDLENGTH
;
loadTemp
<=
'0'
;
loadId
<=
'0'
;
commandOnly
<=
'0'
;
case
stateOp
is
when
readIdOp
=>
header
<=
READIDHEADER
;
bitTop
<=
IDLENGTH
;
if
stateCm
=
idleCm
then
loadId
<=
crcOk
;
end
if
;
when
convertOp1
=>
header
<=
CONVERTHEADER
;
commandOnly
<=
'1'
;
when
skipRomOp1
=>
header
<=
SKIPHEADER
;
commandOnly
<=
'1'
;
when
readTempOp
=>
header
<=
READTEMPHEADER
;
bitTop
<=
TEMPLENGTH
;
if
stateCm
=
idleCm
then
loadTemp
<=
crcOk
and
pps
;
end
if
;
when
skipRomOp2
=>
header
<=
SKIPHEADER
;
commandOnly
<=
'1'
;
when
convertOp2
=>
header
<=
CONVERTHEADER
;
commandOnly
<=
'1'
;
when
others
=>
null
;
end
case
;
end
process
OpFsmOutputs_p
;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Commands state machine
CmFsmTransitions_p
:
process
(
Clk
)
begin
if
rising_edge
(
Clk
)
then
if
RstN
=
'0'
then
stateCm
<=
resetCm
;
else
stateCm
<=
nxStateCm
;
end
if
;
end
if
;
end
process
CmFsmTransitions_p
;
CmFsmStates_p
:
process
(
stateCm
,
startPulse
,
endWriteCm
,
endReadCm
,
crcOk
,
stateOp
,
commandOnly
,
pps_d
)
begin
nxStateCm
<=
resetCm
;
case
stateCm
is
when
resetCm
=>
if
startPulse
=
'1'
then
nxStateCm
<=
prepWriteCm
;
else
nxStateCm
<=
stateCm
;
end
if
;
when
prepWriteCm
=>
if
startPulse
=
'1'
then
nxStateCm
<=
writeCm
;
else
nxStateCm
<=
stateCm
;
end
if
;
when
writeCm
=>
if
endWriteCm
=
'1'
then
if
commandOnly
=
'0'
then
nxStateCm
<=
prepReadCm
;
else
nxStateCm
<=
idleCm
;
end
if
;
else
nxStateCm
<=
stateCm
;
end
if
;
when
prepReadCm
=>
if
startPulse
=
'1'
then
nxStateCm
<=
readCm
;
else
nxStateCm
<=
stateCm
;
end
if
;
when
readCm
=>
if
endReadCm
=
'1'
then
nxStateCm
<=
idleCm
;
else
nxStateCm
<=
stateCm
;
end
if
;
when
idleCm
=>
if
stateOp
=
readIdOp
then
if
crcOk
=
'0'
then
nxStateCm
<=
resetCm
;
else
nxStateCm
<=
stateCm
;
end
if
;
elsif
stateOp
=
readTempOp
then
-- At this moment I will send a Conv Temp command
if
pps_d
=
'1'
then
nxStateCm
<=
prepWriteCm
;
else
nxStateCm
<=
stateCm
;
end
if
;
elsif
(
stateOp
=
convertOp1
)
or
(
stateOp
=
convertOp2
)
then
-- At this moment I will restart a Temp read
if
pps_d
=
'1'
then
nxStateCm
<=
prepWriteCm
;
else
nxStateCm
<=
stateCm
;
end
if
;
elsif
(
stateOp
=
skipRomOp1
)
or
(
stateOp
=
skipRomOp2
)
then
-- At this moment I will restart
if
pps_d
=
'1'
then
nxStateCm
<=
resetCm
;
else
nxStateCm
<=
stateCm
;
end
if
;
else
nxStateCm
<=
stateCm
;
end
if
;
end
case
;
end
process
CmFsmStates_p
;
CmFsmOutputs_p
:
process
(
stateCm
,
bitCounter
,
preReadPulse
,
crcVec
,
startPulse
,
shiftedHeader
,
initPulse
,
readValue
,
preInitPulse
)
begin
incBitCnt
<=
'0'
;
nxSerialIdOut
<=
'0'
;
shiftHeader
<=
'0'
;
ldCmRg
<=
'0'
;
nxserialIdOe
<=
'0'
;
resetBitCnt
<=
'0'
;
init
<=
'0'
;
crcOk
<=
'0'
;
case
stateCm
is
when
resetCm
=>
resetBitCnt
<=
'1'
;
nxSerialIdOut
<=
'0'
;
nxserialIdOe
<=
'1'
;
init
<=
startPulse
;
when
prepWriteCm
=>
resetBitCnt
<=
startPulse
;
nxserialIdOe
<=
'0'
;
nxSerialIdOut
<=
'0'
;
when
writeCm
=>
shiftHeader
<=
startPulse
;
incBitCnt
<=
startPulse
;
resetBitCnt
<=
'0'
;
nxSerialIdOut
<=
shiftedHeader
(
0
)
and
(
not
initPulse
);
if
bitCounter
<
to_unsigned
(
7
,
bitCounter
'length
)
then
nxserialIdOe
<=
not
preInitPulse
;
else
nxserialIdOe
<=
not
preReadPulse
;
end
if
;
when
prepReadCm
=>
resetBitCnt
<=
startPulse
;
nxserialIdOe
<=
'0'
;
nxSerialIdOut
<=
'0'
;
when
readCm
=>
incBitCnt
<=
startPulse
;
resetBitCnt
<=
'0'
;
nxSerialIdOut
<=
not
initPulse
;
ldCmRg
<=
readValue
;
nxserialIdOe
<=
initPulse
;
when
idleCm
=>
if
crcVec
=
x"00"
then
crcOk
<=
'1'
;
else
crcOk
<=
'0'
;
end
if
;
init
<=
'1'
;
end
case
;
end
process
CmFsmOutputs_p
;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Generates time slots
-- Reset pulse
-- Read time slot
-- Write time slots
process
(
Clk
)
begin
if
rising_edge
(
Clk
)
then
if
RstN
=
'0'
then
slotCounter
(
slotCounter
'left
)
<=
'1'
;
slotCounter
(
slotCounter
'left
-1
downto
0
)
<=
(
others
=>
'0'
);
startPulse
<=
'0'
;
endPulse
<=
'0'
;
setValue
<=
'0'
;
readValue
<=
'0'
;
initPulse
<=
'0'
;
preInitPulse
<=
'0'
;
preReadPulse
<=
'0'
;
else
-- Slot counter
if
init
=
'1'
then
slotCounter
(
slotCounter
'left
)
<=
'1'
;
slotCounter
(
slotCounter
'left
-
1
downto
0
)
<=
(
others
=>
'0'
);
elsif
slotCounter
=
slotCounterSTOP
then
slotCounter
<=
(
others
=>
'0'
);
else
slotCounter
<=
slotCounter
+
1
;
end
if
;
-- Time slot start pulse
if
slotCounter
=
slotCounterSTART
then
startPulse
<=
'1'
;
else
startPulse
<=
'0'
;
end
if
;
if
((
slotCounter
>
slotCounterSTART
)
and
(
slotCounter
<
slotCounterSET
))
then
initPulse
<=
'1'
;
else
initPulse
<=
'0'
;
end
if
;
if
((
slotCounter
>
slotCounterPRESTOP
)
and
(
slotCounter
<
slotCounterSTOP
))
then
preInitPulse
<=
'1'
;
else
preInitPulse
<=
'0'
;
end
if
;
if
(((
slotCounter
>
slotCounterPRESTOP
)
and
(
slotCounter
<=
slotCounterSTOP
))
or
(
slotCounter
<=
slotCounterSTARTPLUSONE
))
then
preReadPulse
<=
'1'
;
else
preReadPulse
<=
'0'
;
end
if
;
-- End of time slot pulse
if
slotCounter
=
slotCounterSTART
then
endPulse
<=
'1'
;
else
endPulse
<=
'0'
;
end
if
;
-- Pulse to write value on serial link
if
slotCounter
=
slotCounterSET
then
setValue
<=
'1'
;
else
setValue
<=
'0'
;
end
if
;
-- Pulse to read value on serial link
if
slotCounter
=
slotCounterREAD
then
readValue
<=
'1'
;
else
readValue
<=
'0'
;
end
if
;
end
if
;
end
if
;
end
process
;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Data serializer bit counter
BitCnt_p
:
process
(
Clk
)
begin
if
rising_edge
(
Clk
)
then
if
RstN
=
'0'
then
bitCounter
<=
(
others
=>
'0'
);
else
if
resetBitCnt
=
'1'
then
bitCounter
<=
(
others
=>
'0'
);
elsif
incBitCnt
=
'1'
then
bitCounter
<=
bitCounter
+
1
;
end
if
;
end
if
;
end
if
;
end
process
BitCnt_p
;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Data serializer shift register
ShiftReg_p
:
process
(
Clk
)
begin
if
rising_edge
(
Clk
)
then
if
RstN
=
'0'
then
shiftedHeader
<=
READIDHEADER
;
cmRg
<=
(
others
=>
'0'
);
SerialIdr
<=
'0'
;
serialIdOut
<=
'0'
;
iserialIdOe
<=
'0'
;
Id
<=
(
others
=>
'0'
);
iIdRead
<=
'0'
;
IdRead
<=
'0'
;
crcVec
<=
(
others
=>
'0'
);
Temp
<=
(
others
=>
'0'
);
else
-- Samples serial input
SerialIdr
<=
SerialId
;
-- Shifts command out
if
init
=
'1'
then
shiftedHeader
<=
header
;
elsif
shiftHeader
=
'1'
then
shiftedHeader
(
shiftedHeader
'left
-1
downto
0
)
<=
shiftedHeader
(
shiftedHeader
'left
downto
1
);
shiftedHeader
(
shiftedHeader
'left
)
<=
'0'
;
end
if
;
-- Computes CRC on read data (include the received CRC itself, if no errror crcVec = X"00")
if
init
=
'1'
then
crcVec
<=
(
others
=>
'0'
);
elsif
ldCmRg
=
'1'
then
crcVec
(
0
)
<=
serialIdr
xor
crcVec
(
7
);
crcVec
(
3
downto
1
)
<=
crcVec
(
2
downto
0
);
crcVec
(
4
)
<=
(
serialIdr
xor
crcVec
(
7
))
xor
crcVec
(
3
);
crcVec
(
5
)
<=
(
serialIdr
xor
crcVec
(
7
))
xor
crcVec
(
4
);
crcVec
(
7
downto
6
)
<=
crcVec
(
6
downto
5
);
end
if
;
-- Stores incomming data
if
(
ldCmRg
=
'1'
)
then
cmRg
(
cmRg
'left
-
1
downto
0
)
<=
cmRg
(
cmRg
'left
downto
1
);
cmRg
(
cmRg
'left
)
<=
serialIdr
;
end
if
;
-- Updates serial ouptut data
serialIdOut
<=
nxSerialIdOut
;
-- Updates serial output enable
iserialIdOe
<=
nxSerialIdOe
;
-- Stores ID in register
if
(
loadId
=
'1'
)
then
iIdRead
<=
'1'
;
Id
<=
cmRg
(
IDLEFT
downto
IDRIGHT
);
end
if
;
-- Stores Temperature in register
if
(
loadTemp
=
'1'
)
then
Temp
<=
cmRg
(
TEMPLEFT
downto
TEMPRIGHT
);
end
if
;
-- Delays ID read
IdRead
<=
iIdRead
;
end
if
;
end
if
;
end
process
ShiftReg_p
;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Value on Id port is valid
process
(
Clk
)
begin
if
rising_edge
(
Clk
)
then
if
stateCm
=
idleCm
then
IdOk
<=
crcOk
;
end
if
;
end
if
;
end
process
;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Detects end of read or end of write command
endWriteCm
<=
'1'
when
(
bitCounter
=
to_unsigned
(
7
,
bitCounter
'length
))
and
(
incBitCnt
=
'1'
)
else
'0'
;
endReadCm
<=
'1'
when
(
bitCounter
=
bitTop
)
else
'0'
;
------------------------------------------------------------------------------
end
rtl
;
syn/spec/spec_masterfip.xise
View file @
5ea0f26e
...
...
@@ -16,20 +16,20 @@
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...
...
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...
...
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<property
xil_pn:name=
"Specify 'define Macro Name and Value"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Behavioral"
xil_pn:value=
"work.tb_
masterFIP
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Behavioral"
xil_pn:value=
"work.tb_
onewire_interf
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Post-Map"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Post-Route"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Post-Translate"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
...
...
@@ -1405,7 +1409,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property
xil_pn:name=
"PROP_BehavioralSimTop"
xil_pn:value=
"Architecture|tb_
masterFIP|behavioral
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"PROP_BehavioralSimTop"
xil_pn:value=
"Architecture|tb_
onewire_interf|behavior
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"PROP_DesignName"
xil_pn:value=
"spec_top_fmc_tdc"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"PROP_DevFamilyPMName"
xil_pn:value=
"spartan6"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"PROP_FPGAConfiguration"
xil_pn:value=
"FPGAConfiguration"
xil_pn:valueState=
"default"
/>
...
...
syn/spec/tb_masterFIP.fdo
View file @
5ea0f26e
######################################################################
##
## Filename: tb_masterFIP.fdo
## Created on: Fri Jul 22 18:
19
:57 W. Europe Daylight Time 2016
## Created on: Fri Jul 22 18:
44
:57 W. Europe Daylight Time 2016
##
## Auto generated by Project Navigator for Behavioral Simulation
##
...
...
top/spec/spec_masterfip.vhd
View file @
5ea0f26e
...
...
@@ -241,7 +241,7 @@ architecture rtl of spec_masterfip is
signal
led_clk_100m_aux
:
std_logic_vector
(
7
downto
0
);
signal
rx_err
,
rx_act
,
fd_txena
:
std_logic
;
signal
pllout_clk_40m
,
clk_40m
:
std_logic
;
--=================================================================================================
-- architecture begin
--=================================================================================================
...
...
@@ -279,7 +279,7 @@ begin
port
map
(
CLKFBOUT
=>
pllout_clk_sys_fb
,
CLKOUT0
=>
pllout_clk_sys
,
CLKOUT1
=>
pllout_clk_40m
,
CLKOUT1
=>
open
,
CLKOUT2
=>
open
,
CLKOUT3
=>
open
,
CLKOUT4
=>
open
,
...
...
@@ -294,11 +294,8 @@ begin
port
map
(
O
=>
clk_100m_sys
,
I
=>
pllout_clk_sys
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_clk_40m_buf
:
BUFG
port
map
(
O
=>
clk_40m
,
I
=>
pllout_clk_40m
);
---------------------------------------------------------------------------------------------------
-- RESET --
...
...
@@ -432,13 +429,12 @@ begin
values_for_simul
=>
FALSE
)
port
map
(
clk_i
=>
clk_100m_sys
,
clk_40m_i
=>
clk_40m
,
rst_i
=>
rst_sys
,
-- Bus speed
speed_b0_i
=>
speed_b0_i
,
speed_b1_i
=>
speed_b1_i
,
-- One Wire
carrier_onewire_b
=>
carrier_onewire_b
,
onewire_b
=>
carrier_onewire_b
,
-- FielDrive
fd_rxcdn_i
=>
fd_rxcdn_i
,
fd_rxd_i
=>
fd_rxd_i
,
...
...
@@ -510,26 +506,26 @@ begin
-- SPEC 1-wire --
---------------------------------------------------------------------------------------------------
cmp_carrier_onewire
:
xwb_onewire_master
generic
map
(
g_interface_mode
=>
CLASSIC
,
g_address_granularity
=>
BYTE
,
g_num_ports
=>
1
,
g_ow_btp_normal
=>
"5.0"
,
g_ow_btp_overdrive
=>
"1.0"
)
port
map
(
clk_sys_i
=>
clk_100m_sys
,
rst_n_i
=>
rst_sys_n
,
slave_i
=>
cnx_master_out
(
c_WB_SLAVE_SPEC_ONEWIRE
),
slave_o
=>
cnx_master_in
(
c_WB_SLAVE_SPEC_ONEWIRE
),
desc_o
=>
open
,
owr_pwren_o
=>
open
,
owr_en_o
=>
carrier_owr_en
,
owr_i
=>
carrier_owr_i
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
carrier_onewire_b
<=
'0'
when
carrier_owr_en
(
0
)
=
'1'
else
'Z'
;
carrier_owr_i
(
0
)
<=
carrier_onewire_b
;
--
cmp_carrier_onewire : xwb_onewire_master
--
generic map
--
(g_interface_mode => CLASSIC,
--
g_address_granularity => BYTE,
--
g_num_ports => 1,
--
g_ow_btp_normal => "5.0",
--
g_ow_btp_overdrive => "1.0")
--
port map
--
(clk_sys_i => clk_100m_sys,
--
rst_n_i => rst_sys_n,
--
slave_i => cnx_master_out(c_WB_SLAVE_SPEC_ONEWIRE),
--
slave_o => cnx_master_in(c_WB_SLAVE_SPEC_ONEWIRE),
--
desc_o => open,
--
owr_pwren_o => open,
--
owr_en_o => carrier_owr_en,
--
owr_i => carrier_owr_i);
--
--
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
--
carrier_onewire_b <= '0' when carrier_owr_en(0) = '1' else 'Z';
--
carrier_owr_i(0) <= carrier_onewire_b;
---------------------------------------------------------------------------------------------------
...
...
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