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MasterFIP - Gateware
Commit 6173ce17 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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- added TP to the top level 

- cleaned up simulation
parent 86ec47a0
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Showing with 387 additions and 359 deletions
rtl/fmc_masterFIP_core.vhd
View file @ 6173ce17
......@@ -315,7 +315,8 @@ begin
len_i => extend,
extended_o => fd_host_rst);
extend <= std_logic_vector(c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(speed))));
extend <= std_logic_vector(c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(speed))));
fd_rstn_o <= fd_host_rst;
---------------------------------------------------------------------------------------------------
......
sim/spec/testbench/tb_masterFIP.vhd
View file @ 6173ce17
......@@ -300,7 +300,7 @@ constant pll_clk_period : time:= 8 ns;
constant g_width : integer:= 32;
constant g_span : integer:= 32;
constant spec_clk_period : time:= 50 ns;
--signal nanoFIP_clk_period : time:= 25 ns;
constant nanoFIP_clk_period : time:= 25 ns;
-- Number of Models receiving commands
constant N_BFM : integer := 1; -- 0 : GN412X_BFM in Model Mode
......@@ -440,7 +440,7 @@ signal spare : std_logic;
signal cyc : std_logic;
signal dat_to_fip, dat_to_fip_tmp : std_logic_vector(15 downto 0);
signal rst : std_logic := '0';
signal rst : std_logic;
signal stb : std_logic;
signal wclk : std_logic;
signal we : std_logic;
......@@ -537,7 +537,7 @@ begin
fd_txena_o => nanoFIP_txena,
nostat_i => nostat,
rstin_i => (rst_n),--was not
rstin_i => rst,
rstpon_i => '1',
slone_i => slone,
rston_o => urst_from_nf,
......@@ -595,7 +595,7 @@ begin
adr_o => adr,
cyc_o => cyc,
dat_o => dat_to_fip_tmp,
rst_o => rst,
rst_o => open,
stb_o => stb,
wclk_o => wclk,
we_o => we
......@@ -748,11 +748,11 @@ begin
wait for pll_clk_period/2;
end process;
-- nanoFIP_clock: process
-- begin
-- nanoFIP_clk <= not (nanoFIP_clk) after 1 ns;
-- wait for nanoFIP_clk_period/2;
-- end process;
-- nanoFIP_clock: process
-- begin
-- nanoFIP_clk <= not (nanoFIP_clk) after 10 ns;
-- wait for nanoFIP_clk_period/2;
-- end process;
ext_sync <= '1' after 8500 ns, '0' after 8580 ns,
'1' after 194000 ns, '0' after 194080 ns,
......@@ -763,6 +763,7 @@ begin
'0' after 565151 ns, '1' after 565231 ns;
rst_n <= RSTOUT18n;
rst <= not rst_n;
GPIO(0) <= irq_p;
GPIO(1) <= spare;
......
sim/spec/testbench_masterfip.do 0 → 100644
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syn/spec/spec_masterfip.xise
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syn/spec/tb_masterFIP.fdo
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top/spec_mt/spec_masterfip_mt.ucf
View file @ 6173ce17
#bank 0
#----------------------------------------
# BANK 0 P2V5: Clock
#----------------------------------------
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# BANK 1 P1V8: PCIe interface
#----------------------------------------
NET "l_rst_n_i" LOC = N20;
NET "l_rst_n_i" IOSTANDARD = "LVCMOS18";
NET "GPIO_b[1]" LOC = U16;
NET "GPIO_b[1]" IOSTANDARD = "LVCMOS25";
NET "GPIO_b[0]" LOC = AB19;
NET "GPIO_b[0]" IOSTANDARD = "LVCMOS25";
NET "L2P_CLKN_o" LOC = K22;
NET "L2P_CLKN_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP_o" LOC = K21;
......@@ -138,11 +139,25 @@ NET "P2L_DATA_i[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[15]" LOC = H19;
NET "P2L_DATA_i[15]" IOSTANDARD = "SSTL18_I";
#----------------------------------------
# BANK 0 P2V5: SPEC LEDs
#----------------------------------------
NET "GPIO_b[1]" LOC = U16;
NET "GPIO_b[1]" IOSTANDARD = "LVCMOS25";
NET "GPIO_b[0]" LOC = AB19;
NET "GPIO_b[0]" IOSTANDARD = "LVCMOS25";
NET "LED_RED_O" LOC = D5;
NET "LED_RED_O" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN_O" LOC = E5;
NET "LED_GREEN_O" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# BANK 0 P2V5: SPEC DAC
#----------------------------------------
NET "dac_cs_n_o[0]" LOC = A3;
NET "dac_cs_n_o[0]" IOSTANDARD = "LVCMOS25";
NET "dac_cs_n_o[1]" LOC = B3;
......@@ -152,13 +167,12 @@ NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
NET "fmc_prsnt_m2c_n_i" LOC = AB14;
NET "fmc_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# FMC slot
# Bank 2 P2V5: FMC
#----------------------------------------
NET "fmc_prsnt_m2c_n_i" LOC = AB14;
NET "fmc_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "fmc_onewire_b" LOC = "C18";
NET "fmc_onewire_b" IOSTANDARD = "LVCMOS25";
......@@ -241,6 +255,19 @@ NET "led_sync_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_sync_err_n_o" LOC = Y10;
NET "led_sync_err_n_o" IOSTANDARD = "LVCMOS25";
NET "tp1_o" LOC = AA16;
NET "tp1_o" IOSTANDARD = "LVCMOS25";
NET "tp2_o" LOC = AB16;
NET "tp2_o" IOSTANDARD = "LVCMOS25";
NET "tp3_o" LOC = Y17;
NET "tp3_o" IOSTANDARD = "LVCMOS25";
NET "tp4_o" LOC = AB17;
NET "tp4_o" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2015/07/27
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
......
top/spec_mt/spec_masterfip_mt.vhd
View file @ 6173ce17
......@@ -50,7 +50,7 @@ use unisim.vcomponents.all;
entity spec_masterfip_mt is
generic (g_simulation : boolean := false);
port
(-- Carrier signals
(-- Carrier signals
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Clock
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference,
......@@ -90,9 +90,8 @@ entity spec_masterfip_mt is
dac_din_o : out std_logic;
-- SPEC LEDs
led_red_o : out std_logic;
led_green_o : out std_logic;
led_green_o : out std_logic; -- blinking with clk_100m_sys
led_red_o : out std_logic; -- active during a PCIe rst, l_rst_n_i
-- FMC signals
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- FMC presence
......@@ -121,13 +120,19 @@ entity spec_masterfip_mt is
ext_sync_oe_n_o : out std_logic := '0'; -- output fixed to enabled
ext_sync_i : in std_logic; -- sync pulse
-- FMC Front panel LEDs
-- FMC Front panel LEDs: controlled by the MT firmware, updated every macrocycle
led_rx_act_n_o : out std_logic;
led_rx_err_n_o : out std_logic;
led_tx_act_n_o : out std_logic;
led_tx_err_n_o : out std_logic;
led_sync_act_n_o : out std_logic;
led_sync_err_n_o : out std_logic;
led_sync_act_n_o : out std_logic; -- stays OFF when ext_sync is not used
led_sync_err_n_o : out std_logic; -- stays OFF when ext_sync is not used
-- Test points
tp1_o : out std_logic; -- connected to fd_rxd
tp2_o : out std_logic; -- connected to fd_txd
tp3_o : out std_logic; -- connected to MT led&dbg reg bit 8
tp4_o : out std_logic; -- connected to MT led&dbg reg bit 9
-- To be removed on hw V3
ext_sync_tst_n_o : out std_logic;
......@@ -194,18 +199,18 @@ architecture rtl of spec_masterfip_mt is
-- Signals --
---------------------------------------------------------------------------------------------------
-- clk, reset
signal clk_100m_sys : std_logic;
signal rst_n_sys, rst_sys : std_logic;
signal clk_100m_sys : std_logic;
signal rst_n_sys, rst_sys : std_logic;
-- Mock Turtle
signal fmc_core_wb_out : t_wishbone_master_out_array(0 to 2);
signal fmc_core_wb_in : t_wishbone_master_in_array(0 to 2);
signal fmc_wb_muxed_out : t_wishbone_master_out;
signal fmc_wb_muxed_in : t_wishbone_master_in;
signal fmc_core_wb_out : t_wishbone_master_out_array(0 to 2);
signal fmc_core_wb_in : t_wishbone_master_in_array(0 to 2);
signal fmc_wb_muxed_out : t_wishbone_master_out;
signal fmc_wb_muxed_in : t_wishbone_master_in;
-- LEDs
signal led_divider : unsigned(22 downto 0);
signal spec_led : std_logic_vector(7 downto 0);
signal rx_err, rx_act, fd_txena : std_logic;
signal leds : std_logic_vector(31 downto 0);
signal led_divider : unsigned(22 downto 0);
signal leds : std_logic_vector(31 downto 0);
signal spec_led : std_logic_vector(7 downto 0);
signal fd_txd : std_logic;
--=================================================================================================
-- architecture begin
......@@ -278,9 +283,9 @@ begin
dp_master_o(1) => fmc_core_wb_out(1),
dp_master_i(0) => fmc_core_wb_in(0), -- access from MT CPU1 at base address 100'000
dp_master_i(1) => fmc_core_wb_in(1),
-- WISHBONE connection of the fmc_masterFIP_core to the host
-- WISHBONE connection of the fmc_masterFIP_core to the host
fmc0_host_wb_o => fmc_core_wb_out(2), -- access from PCIe host at base address 10'000
fmc0_host_wb_i => fmc_core_wb_in(2),
fmc0_host_wb_i => fmc_core_wb_in(2),
fmc0_host_irq_i => '0',
-- not used
clk_20m_vcxo_i => '0',
......@@ -297,8 +302,8 @@ begin
-- Note that to give access to the fmc_masterFIP_core to both CPU0 and CPU1, the SP of MT could
-- have been used instead of the DP and this crossbar; this though would have also affected
-- (potentially slowed down) the accesses to the MT Shared Memory.
-- Note also that CPU1 is only accessing the masterfip_leds register for debugging purposes.
-- The PCIe host is accessing the core directly only for testing purposes.
-- Note that in the MT firmware the CPU1 is only accessing the masterfip_leds register for debugging
-- purposes. The PCIe host is accessing the core directly only for testing purposes.
cmp_xwb_crossbar : xwb_crossbar
generic map
(g_num_masters => 3,
......@@ -342,7 +347,7 @@ begin
fd_wdgn_a_i => fd_wdgn_i,
fd_rstn_o => fd_rstn_o,
fd_txck_o => fd_txck_o,
fd_txd_o => fd_txd_o,
fd_txd_o => fd_txd,
fd_txena_o => fd_txena_o,
-- External Synch
ext_sync_term_en_o => ext_sync_term_en_o,
......@@ -376,6 +381,13 @@ begin
led_sync_act_n_o <= leds(4); -- probe on R7
led_sync_err_n_o <= leds(5); -- probe on R2
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
fd_txd_o <= fd_txd;
tp1_o <= fd_rxd_i;
tp2_o <= fd_txd;
tp3_o <= leds(8);
tp4_o <= leds(9);
---------------------------------------------------------------------------------------------------
-- SPEC front panel LEDs --
......
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