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MasterFIP - Gateware
Commit 71c1e137 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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-rx: rearranged bytes within a 32bit reg for the last reg of a frame 

-fmc_masterfip_csr.vhd: macrocyc, turnar and silen counters are 31bits not 32
parent 34a46a24
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rtl/fmc_masterFIP_core.vhd
View file @ 71c1e137
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rtl/fmc_masterfip_csr.vhd
View file @ 71c1e137
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fmc_masterfip_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
-- Created : 10/13/15 12:13:25
-- Created : 10/21/15 17:14:44
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
......@@ -65,11 +65,11 @@ entity fmc_masterfip_csr is
-- Port for BIT field: 'silence cnt start' in reg: 'silence lgth'
mf_silen_start_o : out std_logic;
-- Port for std_logic_vector field: 'macrocycle time counter' in reg: 'macrocycle time cnt'
mf_macrocyc_time_cnt_i : in std_logic_vector(31 downto 0);
mf_macrocyc_time_cnt_i : in std_logic_vector(30 downto 0);
-- Port for std_logic_vector field: 'turnaround time counter' in reg: 'turnaround time cnt'
mf_turnar_time_cnt_i : in std_logic_vector(31 downto 0);
mf_turnar_time_cnt_i : in std_logic_vector(30 downto 0);
-- Port for std_logic_vector field: 'silence time counter' in reg: 'silence time cnt'
mf_silen_time_cnt_i : in std_logic_vector(31 downto 0);
mf_silen_time_cnt_i : in std_logic_vector(30 downto 0);
-- Port for std_logic_vector field: 'ext_sync_tstamp' in reg: 'ext sync tstamp'
mf_ext_sync_tstamp_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: 'tx rst' in reg: 'tx ctrl'
......@@ -820,19 +820,22 @@ begin
when "00001001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_macrocyc_time_cnt_i;
rddata_reg(30 downto 0) <= mf_macrocyc_time_cnt_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_turnar_time_cnt_i;
rddata_reg(30 downto 0) <= mf_turnar_time_cnt_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_silen_time_cnt_i;
rddata_reg(30 downto 0) <= mf_silen_time_cnt_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001100" =>
......
rtl/masterFIP_pkg.vhd
View file @ 71c1e137
......@@ -213,9 +213,9 @@ package masterFIP_pkg is
mf_turnar_start_o : out std_logic;
mf_silen_lgth_o : out std_logic_vector(30 downto 0);
mf_silen_start_o : out std_logic;
mf_macrocyc_time_cnt_i : in std_logic_vector(31 downto 0);
mf_turnar_time_cnt_i : in std_logic_vector(31 downto 0);
mf_silen_time_cnt_i : in std_logic_vector(31 downto 0);
mf_macrocyc_time_cnt_i : in std_logic_vector(30 downto 0);
mf_turnar_time_cnt_i : in std_logic_vector(30 downto 0);
mf_silen_time_cnt_i : in std_logic_vector(30 downto 0);
mf_tx_ctrl_rst_o : out std_logic;
mf_tx_ctrl_start_o : out std_logic;
......
rtl/masterfip_rx.vhd
View file @ 71c1e137
......@@ -119,10 +119,6 @@ entity masterfip_rx is port(
rx_ctrl_byte_o : out std_logic_vector(7 downto 0); -- frame CTRL byte
rx_pdu_byte_o : out std_logic_vector(7 downto 0); -- frame CTRL byte
rx_lgth_byte_o : out std_logic_vector(7 downto 0); -- frame CTRL byte
rx_frame_o : out rx_frame_t; -- frame DATA bytes
-- structure with 66 words of 32-bit each
-- this represents the max length of a frame
......@@ -152,14 +148,14 @@ architecture struc of masterfip_rx is
signal s_fd_rxd_filt, s_rxd_filt_edge_p : std_logic;
signal s_fd_rxd_filt_f_edge_p, s_fd_rxd_filt_r_edge_p : std_logic;
-- wf_rx_deserializer
signal rx_byte_ready_p : std_logic;
signal rx_byte_ready_p, rx_fss_crc_fes_ok_p : std_logic;
signal rx_byte : std_logic_vector (7 downto 0);
-- retreived bytes into 32-bit regs
signal byte0, byte1, byte2, byte3 : std_logic_vector(7 downto 0);
signal byte0, byte1, byte2, byte3 : std_logic_vector(7 downto 0) := (others => '0');
signal word32 : std_logic_vector(31 downto 0);
signal word32_num : integer range 0 to 31;
-- bytes counter
signal rx_byte_index, rx_byte_index_d1 : unsigned(8 downto 0);
signal rx_byte_index, rx_byte_index_d1 : unsigned(8 downto 0) := (others => '0');
signal bytes_c_rst : std_logic;
......@@ -200,13 +196,14 @@ begin
-----------------------------------------------------------------
byte_o => rx_byte,
byte_ready_p_o => rx_byte_ready_p,
fss_crc_fes_ok_p_o => rx_fss_crc_fes_ok_p_o,
fss_crc_fes_ok_p_o => rx_fss_crc_fes_ok_p,
rx_osc_rst_o => s_rx_osc_rst,
fss_received_p_o => rx_fss_received_p_o,
crc_wrong_p_o => rx_crc_wrong_p_o);
-----------------------------------------------------------------
rx_byte_ready_p_o <= rx_byte_ready_p;
rx_byte_o <= rx_byte;
rx_fss_crc_fes_ok_p_o <= rx_fss_crc_fes_ok_p;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_rx_osc: wf_rx_osc
......@@ -268,7 +265,6 @@ begin
end if;
end process;
-------------------------------------------
word32 <= byte0 & byte1 & byte2 & byte3;
---------------------------------------------------------------------------------------------------
......@@ -296,11 +292,26 @@ begin
if rst_i = '1' or rx_rst_i = '1' then
word32_num <= 0;
rx_frame_o <= (others =>(others =>'0'));
else
if rx_byte_ready_p = '1' and (rx_byte_index_d1) > 0 and (rx_byte_index_d1) mod 4 = 0 then
else
if rx_fss_crc_fes_ok_p = '1' then
if (rx_byte_index-2) mod 4 = 0 or (rx_byte_index-2) mod 4 = 3 then
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3;
elsif (rx_byte_index-2) mod 4 = 2 then
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= "00000000" & byte0 & byte1 & byte2;--std_logic_vector(srl (unsigned(byte0 & byte1 & byte2 & byte3), 8));
else
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= word32;
rx_frame_o(word32_num) <= "0000000000000000" & byte0 & byte1;-- std_logic_vector(srl (unsigned(byte0 & byte1 & byte2 & byte3), 16));
end if;
elsif (rx_byte_ready_p = '1' and (rx_byte_index_d1) > 0 and (rx_byte_index_d1) mod 4 = 0) then
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3;
end if;
end if;
end if;
end process;
......
rtl/wbgen/fmc_masterfip_csr.wb
View file @ 71c1e137
......@@ -266,7 +266,7 @@ peripheral {
name = "macrocycle time counter";
description = "current value of the macrocycle time counter";
type = SLV;
size = 32;
size = 31;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
......@@ -281,7 +281,7 @@ peripheral {
name = "turnaround time counter";
description = "current value of the turnaround time counter";
type = SLV;
size = 32;
size = 31;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
......@@ -295,7 +295,7 @@ peripheral {
name = "silence time counter";
description = "current value of the silence time counter";
type = SLV;
size = 32;
size = 31;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
......
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