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MasterFIP - Gateware
Commit 76584c13 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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changed to gitlab mockturtle submodule

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.gitmodules
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...@@ -13,3 +13,6 @@ ...@@ -13,3 +13,6 @@
[submodule "ip_cores/etherbone-core"] [submodule "ip_cores/etherbone-core"]
path = ip_cores/etherbone-core path = ip_cores/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git url = git://ohwr.org/hdl-core-lib/etherbone-core.git
[submodule "ip_cores/mockturtle"]
path = ip_cores/mockturtle
url = https://gitlab.cern.ch/coht/mockturtle.git
mockturtle @ bb80c5b3
Subproject commit bb80c5b3009265db7d3fc595d859350a68cdf881
syn/spec/spec_masterfip_mt.par
View file @ 76584c13
Release 14.7 par P.20131013 (nt64) Release 14.7 par P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PCBE13457:: Wed Jul 26 12:07:41 2017 PCBE13457:: Thu Jan 17 18:18:19 2019
par -w -intstyle ise -ol high -xe n -mt off spec_masterfip_mt_map.ncd par -w -intstyle ise -ol high -xe n -mt off spec_masterfip_mt_map.ncd
spec_masterfip_mt.ncd spec_masterfip_mt.pcf spec_masterfip_mt.ncd spec_masterfip_mt.pcf
Constraints file: spec_masterfip_mt.pcf. Constraints file: spec_masterfip_mt.pcf.
Loading device for application Rf_Device from file '6slx45t.nph' in environment C:\EDA\Xilinx\14.7\ISE_DS\ISE\. Loading device for application Rf_Device from file '6slx45t.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
"spec_masterfip_mt" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -3 "spec_masterfip_mt" is an NCD, version 3.2, device xc6slx45t, package fgg484, speed -3
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
...@@ -111,7 +111,7 @@ Router effort level (-rl): High ...@@ -111,7 +111,7 @@ Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report. Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 18 secs Starting initial Timing Analysis. REAL time: 18 secs
Finished initial Timing Analysis. REAL time: 19 secs Finished initial Timing Analysis. REAL time: 18 secs
WARNING:Par:288 - The signal vc_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal vc_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal vc_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal vc_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
...@@ -189,25 +189,25 @@ Phase 1 : 110289 unrouted; REAL time: 20 secs ...@@ -189,25 +189,25 @@ Phase 1 : 110289 unrouted; REAL time: 20 secs
Phase 2 : 101662 unrouted; REAL time: 23 secs Phase 2 : 101662 unrouted; REAL time: 23 secs
Phase 3 : 51539 unrouted; REAL time: 1 mins 7 secs Phase 3 : 51539 unrouted; REAL time: 1 mins 12 secs
Phase 4 : 53338 unrouted; (Setup:0, Hold:3107, Component Switching Limit:0) REAL time: 1 mins 23 secs Phase 4 : 53338 unrouted; (Setup:0, Hold:3107, Component Switching Limit:0) REAL time: 1 mins 29 secs
Updating file: spec_masterfip_mt.ncd with current fully routed design. Updating file: spec_masterfip_mt.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 7 mins 42 secs Phase 5 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 8 mins 40 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 7 mins 42 secs Phase 6 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 8 mins 40 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 7 mins 42 secs Phase 7 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 8 mins 40 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 7 mins 42 secs Phase 8 : 0 unrouted; (Setup:0, Hold:2602, Component Switching Limit:0) REAL time: 8 mins 40 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 mins 43 secs Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 8 mins 41 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 7 mins 49 secs Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 8 mins 47 secs
Total REAL time to Router completion: 7 mins 49 secs Total REAL time to Router completion: 8 mins 47 secs
Total CPU time to Router completion: 7 mins 58 secs Total CPU time to Router completion: 8 mins 55 secs
Partition Implementation Status Partition Implementation Status
------------------------------- -------------------------------
...@@ -367,10 +367,10 @@ All signals are completely routed. ...@@ -367,10 +367,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 29 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. WARNING:Par:283 - There are 29 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 7 mins 56 secs Total REAL time to PAR completion: 8 mins 55 secs
Total CPU time to PAR completion: 8 mins 5 secs Total CPU time to PAR completion: 9 mins 3 secs
Peak Memory Usage: 889 MB Peak Memory Usage: 666 MB
Placer: Placement generated during map. Placer: Placement generated during map.
Routing: Completed - No errors found. Routing: Completed - No errors found.
......
syn/spec/spec_masterfip_mt.syr
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syn/spec/spec_masterfip_mt.twr
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-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Release 14.7 Trace (nt64) Release 14.7 Trace (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
C:\EDA\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n
3 -n 3 -fastpaths -xml spec_masterfip_mt.twx spec_masterfip_mt.ncd -o 3 -fastpaths -xml spec_masterfip_mt.twx spec_masterfip_mt.ncd -o
spec_masterfip_mt.twr spec_masterfip_mt.pcf spec_masterfip_mt.twr spec_masterfip_mt.pcf
Design file: spec_masterfip_mt.ncd Design file: spec_masterfip_mt.ncd
...@@ -1397,14 +1397,14 @@ Design statistics: ...@@ -1397,14 +1397,14 @@ Design statistics:
------------------------------------Footnotes----------------------------------- ------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays. 1) The minimum period statistic assumes all single cycle delays.
Analysis completed Wed Jul 26 12:16:14 2017 Analysis completed Thu Jan 17 18:27:56 2019
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Trace Settings: Trace Settings:
------------------------- -------------------------
Trace Settings Trace Settings
Peak Memory Usage: 702 MB Peak Memory Usage: 502 MB
syn/spec/spec_masterfip_mt.xise
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syn/spec/spec_masterfip_mt_map.mrp
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Release 14.7 Map P.20131013 (nt64) Release 14.7 Map P.20131013 (nt)
Xilinx Mapping Report File for Design 'spec_masterfip_mt' Xilinx Mapping Report File for Design 'spec_masterfip_mt'
Design Information Design Information
...@@ -11,7 +11,7 @@ Target Device : xc6slx45t ...@@ -11,7 +11,7 @@ Target Device : xc6slx45t
Target Package : fgg484 Target Package : fgg484
Target Speed : -3 Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $ Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Wed Jul 26 11:57:23 2017 Mapped Date : Thu Jan 17 18:07:58 2019
Design Summary Design Summary
-------------- --------------
...@@ -103,9 +103,9 @@ Specific Feature Utilization: ...@@ -103,9 +103,9 @@ Specific Feature Utilization:
Average Fanout of Non-Clock Nets: 5.30 Average Fanout of Non-Clock Nets: 5.30
Peak Memory Usage: 932 MB Peak Memory Usage: 698 MB
Total REAL time to MAP completion: 10 mins 15 secs Total REAL time to MAP completion: 10 mins 18 secs
Total CPU time to MAP completion (all processors): 12 mins 13 secs Total CPU time to MAP completion (all processors): 12 mins 34 secs
Table of Contents Table of Contents
----------------- -----------------
......
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