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MasterFIP - Gateware
Commit 76d20a64 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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ext_sync_pulse_oe_n controlled by MT, not fixed to '0'

parent 0c572bd8
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rtl/fmc_masterFIP_core.vhd
View file @ 76d20a64
......@@ -40,7 +40,7 @@
-- Figure 1: fmc_masterFIP_core architecture |
-- |
-- MASTERFIP WBGEN2 CSR: |
-- The mrfip_wbgen2_csr module has been generated through the wbgen2 application. |
-- The masterfip_wbgen2_csr module has been generated through the wbgen2 application.|
-- It establishes the interface with the processor, usually a Mock Turtle core. |
-- This interface contains a set of control and status registers for each one of the |
-- units of Figure 1; it also contains the WorldFIP frame PAYLOAD data for the TX |
......@@ -56,7 +56,7 @@
-- The masterfip_tx places a complete WorldFIP frame on the WorldFIP bus. |
-- The masterfip_tx ignores the frame type (ID_DAT/RT_DAT/RP_MSG etc..), or the |
-- macrocycle sequence and macrocycle timing; the processor (MT) is responsible for |
-- managing all these issues and for providing to the masterfip_tx the bytes to |
-- managing all these aspects and for providing to the masterfip_tx the bytes to |
-- serialise, along with a start pulse. |
-- The communication between the processor and the masterfip_tx is handled through a |
-- set of control (from the MT) and status (from the masterfip_tx) signals/registers |
......@@ -78,7 +78,7 @@
-- |
-- MASTERFIP RX: |
-- The masterfip_rx retrieves a WorldFIP frame from the WorldFIP bus. |
-- Similarly to the masterfip_tx, the masterfip_rx has no intelligence regarding the |
-- Similar to the masterfip_tx, the masterfip_rx has no intelligence regarding the |
-- macrocycle sequence; it is controlled and monitored by the processor (MT) through |
-- the masterfip_wbgen2_csr, where a set of control and status registers are defined.|
-- As long as it is not under reset, the masterfip_rx is probing the WorldFIP bus |
......
syn/spec/spec_masterfip_mt.par
View file @ 76d20a64
Release 14.7 par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PCBE13457:: Wed Mar 01 17:58:23 2017
PCBE13457:: Wed Mar 29 14:40:51 2017
par -w -intstyle ise -ol high -mt off spec_masterfip_mt_map.ncd
spec_masterfip_mt.ncd spec_masterfip_mt.pcf
......@@ -22,16 +22,16 @@ Device speed data version: "PRODUCTION 1.23 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 12,640 out of 54,576 23%
Number used as Flip Flops: 12,638
Number of Slice Registers: 12,630 out of 54,576 23%
Number used as Flip Flops: 12,628
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 2
Number of Slice LUTs: 15,700 out of 27,288 57%
Number used as logic: 12,406 out of 27,288 45%
Number using O6 output only: 10,273
Number of Slice LUTs: 15,771 out of 27,288 57%
Number used as logic: 12,467 out of 27,288 45%
Number using O6 output only: 10,336
Number using O5 output only: 395
Number using O5 and O6: 1,738
Number using O5 and O6: 1,736
Number used as ROM: 0
Number used as Memory: 2,828 out of 6,408 44%
Number used as Dual Port RAM: 2,828
......@@ -40,18 +40,18 @@ Slice Logic Utilization:
Number using O5 and O6: 32
Number used as Single Port RAM: 0
Number used as Shift Register: 0
Number used exclusively as route-thrus: 466
Number with same-slice register load: 436
Number with same-slice carry load: 30
Number used exclusively as route-thrus: 476
Number with same-slice register load: 448
Number with same-slice carry load: 28
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 5,340 out of 6,822 78%
Number of occupied Slices: 5,512 out of 6,822 80%
Number of MUXCYs used: 1,452 out of 13,644 10%
Number of LUT Flip Flop pairs used: 18,997
Number with an unused Flip Flop: 7,453 out of 18,997 39%
Number with an unused LUT: 3,297 out of 18,997 17%
Number of fully used LUT-FF pairs: 8,247 out of 18,997 43%
Number of LUT Flip Flop pairs used: 19,206
Number with an unused Flip Flop: 7,648 out of 19,206 39%
Number with an unused LUT: 3,435 out of 19,206 17%
Number of fully used LUT-FF pairs: 8,123 out of 19,206 42%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
......@@ -110,7 +110,7 @@ Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 19 secs
Starting initial Timing Analysis. REAL time: 18 secs
Finished initial Timing Analysis. REAL time: 19 secs
WARNING:Par:288 - The signal vc_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
......@@ -122,109 +122,105 @@ WARNING:Par:288 - The signal fmc_prsnt_m2c_n_i_IBUF has no load. PAR will not a
WARNING:Par:288 - The signal l2p_rdy_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal l_wr_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal l_wr_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem6_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem14_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem43_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem13_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem44_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem9_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem8_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem22_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem5_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem11_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem15_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem12_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem16_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem19_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem13_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem22_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem12_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem21_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem11_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem3_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem27_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem31_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem7_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem32_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem3_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem21_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem4_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem19_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem15_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem16_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem10_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem14_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem9_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem17_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem19_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem29_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem20_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem28_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem21_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem27_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem18_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem23_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem17_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem24_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem5_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem20_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem6_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem6_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem30_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem5_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem29_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem18_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem26_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem10_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMB_DPO
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem20_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMC_DPO
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem17_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem18_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem19_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem2_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem18_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem10_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem17_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem30_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem22_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem25_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem16_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem43_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem3_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem4_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem4_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem3_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem14_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem7_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem13_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem8_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem12_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem32_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem28_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMB_DPO
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem20_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMC_DPO
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem21_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem22_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem14_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem15_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem11_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem2_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem12_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem1_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem7_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem8_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem26_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem11_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem44_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMB_DPO
has no load. PAR will not attempt to route this signal.
......@@ -232,46 +228,50 @@ WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_w
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem23_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem15_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem24_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem13_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem10_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem8_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem1_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem9_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem7_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem5_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem31_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem4_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem25_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem6_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem16_RAMD_O
has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 110992 unrouted; REAL time: 21 secs
Phase 1 : 111392 unrouted; REAL time: 21 secs
Phase 2 : 102240 unrouted; REAL time: 24 secs
Phase 2 : 102625 unrouted; REAL time: 24 secs
Phase 3 : 52508 unrouted; REAL time: 1 mins 6 secs
Phase 3 : 52201 unrouted; REAL time: 1 mins 7 secs
Phase 4 : 53706 unrouted; (Setup:0, Hold:7811, Component Switching Limit:0) REAL time: 1 mins 23 secs
Phase 4 : 53520 unrouted; (Setup:0, Hold:7911, Component Switching Limit:0) REAL time: 1 mins 23 secs
Updating file: spec_masterfip_mt.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:772, Hold:7506, Component Switching Limit:0) REAL time: 7 mins 25 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:7822, Component Switching Limit:0) REAL time: 6 mins 37 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:7506, Component Switching Limit:0) REAL time: 9 mins 14 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:7822, Component Switching Limit:0) REAL time: 6 mins 37 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:7506, Component Switching Limit:0) REAL time: 9 mins 14 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:7822, Component Switching Limit:0) REAL time: 6 mins 37 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:7506, Component Switching Limit:0) REAL time: 9 mins 14 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:7822, Component Switching Limit:0) REAL time: 6 mins 37 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 9 mins 16 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 mins 38 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 9 mins 21 secs
Total REAL time to Router completion: 9 mins 21 secs
Total CPU time to Router completion: 9 mins 32 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 mins 44 secs
Total REAL time to Router completion: 6 mins 44 secs
Total CPU time to Router completion: 6 mins 53 secs
Partition Implementation Status
-------------------------------
......@@ -290,11 +290,11 @@ Generating Clock Report
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/clk_ | | | | | |
| sys | BUFGMUX_X2Y3| No | 4453 | 0.550 | 1.761 |
| sys | BUFGMUX_X2Y3| No | 4506 | 0.549 | 1.760 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/gen_ | | | | | |
|with_gennum.U_GN4124 | | | | | |
| _Core/sys_clk | BUFGMUX_X3Y13| No | 221 | 0.493 | 1.704 |
| _Core/sys_clk | BUFGMUX_X3Y13| No | 224 | 0.493 | 1.704 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/gen_ | | | | | |
|with_gennum.U_GN4124 | | | | | |
......@@ -320,13 +320,13 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_pllout_clk_sys_0 = PER | SETUP | 0.032ns| 9.968ns| 0| 0
IOD TIMEGRP "cmp_mock_turtle_pllo | HOLD | 0.248ns| | 0| 0
TS_cmp_mock_turtle_pllout_clk_sys_0 = PER | SETUP | 0.031ns| 9.969ns| 0| 0
IOD TIMEGRP "cmp_mock_turtle_pllo | HOLD | 0.388ns| | 0| 0
ut_clk_sys_0" TS_clk_125m_pllref_n_i / 0. | | | | |
8 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_gen_with_gennum_U_GN41 | SETUP | 0.035ns| 4.965ns| 0| 0
24_Core_cmp_clk_in_rx_pllout_x1 = | HOLD | 0.047ns| | 0| 0
TS_cmp_mock_turtle_gen_with_gennum_U_GN41 | SETUP | 0.040ns| 4.960ns| 0| 0
24_Core_cmp_clk_in_rx_pllout_x1 = | HOLD | 0.126ns| | 0| 0
PERIOD TIMEGRP "cmp_mock_turtle_ | | | | |
gen_with_gennum_U_GN4124_Core_cmp_clk_in_ | | | | |
rx_pllout_x1" TS_cmp_mock_turtle_ | | | | |
......@@ -387,8 +387,8 @@ Derived Constraints for TS_clk_125m_pllref_n_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk_125m_pllref_n_i | 8.000ns| 3.334ns| 7.974ns| 0| 0| 0| 4832627|
| TS_cmp_mock_turtle_pllout_clk_| 10.000ns| 9.968ns| N/A| 0| 0| 4832627| 0|
|TS_clk_125m_pllref_n_i | 8.000ns| 3.334ns| 7.975ns| 0| 0| 0| 4832382|
| TS_cmp_mock_turtle_pllout_clk_| 10.000ns| 9.969ns| N/A| 0| 0| 4832382| 0|
| sys_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
......@@ -398,15 +398,15 @@ Derived Constraints for TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_U_Node_Template_U_GN4124_Cor| 5.000ns| 0.925ns| 4.965ns| 0| 0| 0| 4827|
|TS_U_Node_Template_U_GN4124_Cor| 5.000ns| 0.925ns| 4.960ns| 0| 0| 0| 4827|
|e_cmp_clk_in_P_clk | | | | | | | |
| TS_cmp_mock_turtle_gen_with_ge| 5.000ns| 2.800ns| 4.965ns| 0| 0| 0| 4827|
| TS_cmp_mock_turtle_gen_with_ge| 5.000ns| 2.800ns| 4.960ns| 0| 0| 0| 4827|
| nnum_U_GN4124_Core_cmp_clk_in_| | | | | | | |
| buf_P_clk | | | | | | | |
| TS_cmp_mock_turtle_gen_with_g| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| ennum_U_GN4124_Core_cmp_clk_i| | | | | | | |
| n_rx_pllout_xs_int | | | | | | | |
| TS_cmp_mock_turtle_gen_with_g| 5.000ns| 4.965ns| N/A| 0| 0| 4827| 0|
| TS_cmp_mock_turtle_gen_with_g| 5.000ns| 4.960ns| N/A| 0| 0| 4827| 0|
| ennum_U_GN4124_Core_cmp_clk_i| | | | | | | |
| n_rx_pllout_x1 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
......@@ -425,10 +425,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 71 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 9 mins 27 secs
Total CPU time to PAR completion: 9 mins 39 secs
Total REAL time to PAR completion: 6 mins 50 secs
Total CPU time to PAR completion: 6 mins 59 secs
Peak Memory Usage: 918 MB
Peak Memory Usage: 891 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
syn/spec/spec_masterfip_mt.syr
View file @ 76d20a64
......@@ -4,13 +4,13 @@ Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
Total CPU time to Xst completion: 0.09 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
Total CPU time to Xst completion: 0.09 secs
--> Reading design: spec_masterfip_mt.prj
......@@ -1041,34 +1041,33 @@ Elaborating entity <wf_decr_counter> (architecture <rtl>) with generics from lib
Synthesizing Unit <spec_masterfip_mt>.
Related source file is "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd".
g_simulation = false
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <sp_master_o_adr> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <sp_master_o_sel> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <sp_master_o_dat> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <tm_dac_value_o> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <tm_dac_wr_o> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <tm_clk_aux_locked_o> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <tm_tai_o> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <tm_cycles_o> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <sim_slave_o_dat> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <led_red> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <led_green> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <sfp_txp_o> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <sfp_txn_o> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <sfp_tx_disable_o> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <uart_txd_o> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <sp_master_o_cyc> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <sp_master_o_stb> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <sp_master_o_we> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <tm_link_up_o> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <tm_time_valid_o> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <sim_slave_o_ack> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <sim_slave_o_err> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <sim_slave_o_rty> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <sim_slave_o_stall> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 372: Output port <sim_slave_o_int> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 439: Output port <sdb_sel_o> of the instance <cmp_wb_crossbar> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 462: Output port <ext_sync_dir_o> of the instance <cmp_masterFIP_core> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 462: Output port <ext_sync_oe_n_o> of the instance <cmp_masterFIP_core> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <sp_master_o_adr> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <sp_master_o_sel> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <sp_master_o_dat> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <tm_dac_value_o> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <tm_dac_wr_o> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <tm_clk_aux_locked_o> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <tm_tai_o> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <tm_cycles_o> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <sim_slave_o_dat> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <led_red> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <led_green> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <sfp_txp_o> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <sfp_txn_o> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <sfp_tx_disable_o> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <uart_txd_o> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <sp_master_o_cyc> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <sp_master_o_stb> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <sp_master_o_we> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <tm_link_up_o> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <tm_time_valid_o> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <sim_slave_o_ack> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <sim_slave_o_err> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <sim_slave_o_rty> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <sim_slave_o_stall> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 371: Output port <sim_slave_o_int> of the instance <cmp_mock_turtle> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 438: Output port <sdb_sel_o> of the instance <cmp_wb_crossbar> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "C:\masterFIP\fresh\masterfip-gw\top\spec\spec_masterfip_mt.vhd" line 461: Output port <ext_sync_dir_o> of the instance <cmp_masterFIP_core> is unconnected or connected to loadless signal.
Found 23-bit register for signal <led_divider>.
Found 8-bit register for signal <spec_led>.
Found 23-bit adder for signal <led_divider[22]_GND_14_o_add_0_OUT> created at line 1241.
......@@ -3945,6 +3944,7 @@ Unit <gc_dyn_extend_pulse> synthesized.
Synthesizing Unit <masterfip_wbgen2_csr>.
Related source file is "C:\masterFIP\fresh\masterfip-gw\rtl\masterfip_wbgen2_csr.vhd".
WARNING:Xst:647 - Input <wb_sel_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Found 7-bit register for signal <ack_sreg>.
Found 32-bit register for signal <rddata_reg>.
Found 32-bit register for signal <masterfip_tx_payld_reg1_int>.
Found 32-bit register for signal <masterfip_tx_payld_reg2_int>.
......@@ -4019,7 +4019,6 @@ WARNING:Xst:647 - Input <wb_sel_i> is never used. This port will be preserved an
Found 31-bit register for signal <masterfip_silen_lgth_int>.
Found 9-bit register for signal <masterfip_tx_ctrl_bytes_num_int>.
Found 8-bit register for signal <masterfip_tx_payld_ctrl_int>.
Found 8-bit register for signal <ack_sreg>.
Found 1-bit register for signal <ack_in_progress>.
Found 1-bit register for signal <masterfip_rst_core_int>.
Found 1-bit register for signal <masterfip_rst_fd_int>.
......@@ -4058,8 +4057,9 @@ WARNING:Xst:647 - Input <wb_sel_i> is never used. This port will be preserved an
Found 1-bit register for signal <regs_o_rx_ctrl_rst_o>.
WARNING:Xst:2404 - FFs/Latches <ack_sreg<9:9>> (without init value) have a constant value of 0 in block <masterfip_wbgen2_csr>.
WARNING:Xst:2404 - FFs/Latches <ack_sreg<8:8>> (without init value) have a constant value of 0 in block <masterfip_wbgen2_csr>.
WARNING:Xst:2404 - FFs/Latches <ack_sreg<7:7>> (without init value) have a constant value of 0 in block <masterfip_wbgen2_csr>.
Summary:
inferred 2354 D-type flip-flop(s).
inferred 2353 D-type flip-flop(s).
inferred 174 Multiplexer(s).
Unit <masterfip_wbgen2_csr> synthesized.
......@@ -4637,9 +4637,9 @@ Macro Statistics
6-bit register : 3
64-bit register : 2
66-bit register : 2
7-bit register : 3
7-bit register : 4
72-bit register : 1
8-bit register : 92
8-bit register : 91
9-bit register : 16
# Comparators : 108
1-bit comparator equal : 2
......@@ -4861,7 +4861,7 @@ WARNING:Xst:1710 - FF/Latch <local_regs_in_gpio_in_i_11> (without init value) ha
WARNING:Xst:1710 - FF/Latch <local_regs_in_gpio_in_i_10> (without init value) has a constant value of 0 in block <gen_cpus[1].U_CPU_Block>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <reg_to_mt_fd_wdg_tstamp_i_31> (without init value) has a constant value of 0 in block <cmp_masterFIP_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <reg_to_mt_fd_txer_tstamp_i_31> (without init value) has a constant value of 0 in block <cmp_masterFIP_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <cmp_masterfip_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <cmp_masterfip_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <d1_1> (without init value) has a constant value of 0 in block <gen_wr_node_without_white_rabbit.U_DAC_ARB>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <d2_15> (without init value) has a constant value of 0 in block <gen_wr_node_without_white_rabbit.U_DAC_ARB>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <d2_14> (without init value) has a constant value of 0 in block <gen_wr_node_without_white_rabbit.U_DAC_ARB>. This FF/Latch will be trimmed during the optimization process.
......@@ -5175,7 +5175,7 @@ WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <p2l_dma_stall_d_1>
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dma_ctrl_o_1> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dma_ctrl_o_0> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <U_Local_Registrers>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <cmp_masterfip_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <cmp_masterfip_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <U_wb_controller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <U_CPU_CSR>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <U_Local_Registrers>. This FF/Latch will be trimmed during the optimization process.
......@@ -5378,28 +5378,27 @@ WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dma_hstarth_o_19> (
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dma_hstarth_o_20> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dma_hstarth_o_21> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <dma_hstarth_o_22> (without init value) has a constant value of 0 in block <dma_controller_wb_slave_0>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <U_CPU_CSR>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <cmp_masterfip_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <U_Local_Registrers>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <U_CPU_CSR>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <U_Local_Registrers>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <cmp_masterfip_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <U_wb_controller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <U_Local_Registrers>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <U_CPU_CSR>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <cmp_masterfip_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <U_wb_controller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <cmp_masterfip_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <U_CPU_CSR>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <U_Local_Registrers>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <U_wb_controller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <U_CPU_CSR>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <cmp_masterfip_csr>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <U_Local_Registrers>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <U_Local_Registrers>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <U_wb_controller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <U_Local_Registrers>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <U_wb_controller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <U_Local_Registrers>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <U_CPU_CSR>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <U_wb_controller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <U_Local_Registrers>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <U_wb_controller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <U_Local_Registrers>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <U_wb_controller>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <U_CPU_CSR>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <U_Local_Registrers>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <U_Local_Registrers>. This FF/Latch will be trimmed during the optimization process.
......@@ -5453,7 +5452,7 @@ WARNING:Xst:2404 - FFs/Latches <irqs_i_reg<32:3>> (without init value) have a c
WARNING:Xst:2404 - FFs/Latches <ack_sreg<7:1>> (without init value) have a constant value of 0 in block <wb_slave_vic>.
WARNING:Xst:2404 - FFs/Latches <reg_to_mt_fd_txer_tstamp_i<31:31>> (without init value) have a constant value of 0 in block <fmc_masterFIP_core>.
WARNING:Xst:2404 - FFs/Latches <reg_to_mt_fd_wdg_tstamp_i<31:31>> (without init value) have a constant value of 0 in block <fmc_masterFIP_core>.
WARNING:Xst:2404 - FFs/Latches <ack_sreg<7:3>> (without init value) have a constant value of 0 in block <masterfip_wbgen2_csr>.
WARNING:Xst:2404 - FFs/Latches <ack_sreg<6:3>> (without init value) have a constant value of 0 in block <masterfip_wbgen2_csr>.
Synthesizing (advanced) Unit <fmc_masterFIP_core>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_extend> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
......@@ -9801,7 +9800,7 @@ Offset: 9.367ns (Levels of Logic = 15)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'cmp_mock_turtle/cmp_sys_clk_pll/CLKOUT0'
Total number of paths / destination ports: 24 / 18
Total number of paths / destination ports: 25 / 19
-------------------------------------------------------------------------
Offset: 8.083ns (Levels of Logic = 2)
Source: cmp_mock_turtle/U_Reset_Generator/U_EdgeDet_PCIe/ppulse_o (FF)
......@@ -9892,14 +9891,14 @@ cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_p2l_dma_master/cmp_to_wb_fifo/
=========================================================================
Total REAL time to Xst completion: 169.00 secs
Total CPU time to Xst completion: 168.70 secs
Total REAL time to Xst completion: 165.00 secs
Total CPU time to Xst completion: 164.24 secs
-->
Total memory usage is 628192 kilobytes
Total memory usage is 631272 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 3943 ( 0 filtered)
Number of infos : 536 ( 0 filtered)
Number of infos : 535 ( 0 filtered)
syn/spec/spec_masterfip_mt.twr
View file @ 76d20a64
This source diff could not be displayed because it is too large. You can view the blob instead.
syn/spec/spec_masterfip_mt_map.mrp
View file @ 76d20a64
This source diff could not be displayed because it is too large. You can view the blob instead.
top/spec/spec_masterfip_mt.vhd
View file @ 76d20a64
......@@ -31,7 +31,7 @@
-- |V| | | | . .|. .>| CPU0 | _____ | X | | G | | | |
-- |E| | | M | ____ . | |______| | | | b | | N | | | <-PCIe->|
-- |_| | | A | | | . | | SH. | | a | | 4 | | | host |
-- | | S |....|Xbar|... | ______ | MEM | | r | | 1 | | | |
-- | | S |. . |Xbar|. . | ______ | MEM | | r | | 1 | | | |
-- ext pulse --> | | T | |____| . | | | |_____| | | | 2 | | | |
-- | | E | . | DP | CPU1 | | | | 4 | | | |
-- | | R | . .|. .>|______| | | | | | | |
......@@ -191,7 +191,7 @@ entity spec_masterfip_mt is
tx_error_i : in std_logic; -- transmit error
vc_rdy_i : in std_logic_vector(1 downto 0); -- channel ready
-- DAC I2C (driven by MT for max stability on the 100 MHz clk)
-- DAC I2C (driven by MT to the VCXO mid range -fixed value- for max stability on the 100 MHz clk)
dac_cs_n_o : out std_logic_vector(1 downto 0); -- 0: select SPEC 25MHz OSC5 VCXO
dac_sclk_o : out std_logic; -- 1: select SPEC 20MHz OSC1 VCXO
dac_din_o : out std_logic;
......@@ -225,8 +225,8 @@ entity spec_masterfip_mt is
-- External synchronisation pulse (input signal and transceiver control)
ext_sync_term_en_o : out std_logic; -- enable 50 Ohm termin of the pulse
ext_sync_dir_o : out std_logic := '0'; -- direction fixed B -> A
ext_sync_oe_n_o : out std_logic := '0'; -- output fixed to enabled
ext_sync_i : in std_logic; -- sync pulse
ext_sync_oe_n_o : out std_logic; -- transceiver output enable
ext_sync_i : in std_logic; -- input sync pulse
-- FMC Front panel LEDs: controlled by the MT firmware, updated every macrocycle
led_rx_act_n_o : out std_logic;
......@@ -258,7 +258,7 @@ architecture rtl of spec_masterfip_mt is
-- MOCK TURTLE CONSTANTS --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- HMQ: It total 10 HMQs have been defined. Each HMQ has 4 entries of 128 x 32 bits, each.
-- HMQ: It total 10 HMQs have been defined. Each HMQ has 4 entries of 128 x 32 bits.
-- 8 "out HMQs" from the MT -> towards the host
-- - 0: HMQ from CPU0 with the WorldFIP payloads from periodic consumed variables
......@@ -271,7 +271,7 @@ architecture rtl of spec_masterfip_mt is
-- (aperiodic presence and identification)
-- - 5: HMQ for debugging data from CPU0 and CPU1 towards the host
-- - 6: HMQ for the responses of CPU0 to the commands of the host, see below "in HMQ0"
-- (e.g.: acknowledgement of the configuration???)
-- (acknowledgement of the configuration; load, start, stop, reset macrocycle)
-- - 7: HMQ for the responses of CPU1 to the commands of the host, see below "in HMQ1",
-- (e.g.: content of the report variable)
......@@ -354,7 +354,6 @@ begin
-- FIXED SIGNALS --
---------------------------------------------------------------------------------------------------
ext_sync_dir_o <= '0'; -- Direction fixed to: B -> A
ext_sync_oe_n_o <= '0'; -- Output fixed to: enabled
-- To be removed on hw V3
-- Note: For the hw v1 signals ext_sync_tst_n_o, adc_prim_conn_n_o and adc_sec_conn_n_o, in order
......@@ -485,7 +484,7 @@ begin
ext_sync_term_en_o => ext_sync_term_en_o,
ext_sync_a_i => ext_sync_i,
ext_sync_dir_o => open, -- hard-wired to '0'
ext_sync_oe_n_o => open, -- hard-wired to '0'
ext_sync_oe_n_o => ext_sync_oe_n_o,
-- LEDs
leds_o => leds,
-- WISHBONE interface with MT CPU0 and CPU1
......
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