Commit 86ec47a0 authored by Evangelia Gousiou's avatar Evangelia Gousiou

- integrated changes from evaC_dev branch

- general clean-up
- updated and renamed wbgen2 fileset.xml
parent 3de128f4
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......@@ -54,9 +54,13 @@ package wf_package is
---------------------------------------------------------------------------------------------------
-- 10ns clock for the masterFIP_core; same for the CPUs
constant c_QUARTZ_PERIOD : real := 10.0;
constant c_QUARTZ_PERIOD_NS : real := 10.0;
constant c_QUARTZ_FREQ_MHZ : real := 100.0;
constant c_QUARTZ_FREQ_MHZ_INT : integer := 100;
constant c_1SEC_CNT_LGTH : natural := 27;
constant c_1SEC_CLK_TICKS : unsigned := to_unsigned((1000000000 / integer(c_QUARTZ_PERIOD_NS)),
c_1SEC_CNT_LGTH);
---------------------------------------------------------------------------------------------------
-- Constants regarding the session timeout counters --
---------------------------------------------------------------------------------------------------
......@@ -81,7 +85,7 @@ package wf_package is
-- Constant regarding the deglitch filter --
---------------------------------------------------------------------------------------------------
constant c_DEGLITCH_THRESHOLD : natural := 4;
constant c_DEGLITCH_THRESHOLD : natural := 10;
---------------------------------------------------------------------------------------------------
......@@ -138,11 +142,13 @@ package wf_package is
-- transmission/ reception periods.
constant c_BIT_RATE_UCLK_TICKS_31_25Kbit: unsigned :=
to_unsigned((32000 / integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LGTH);
to_unsigned((32000 / integer(c_QUARTZ_PERIOD_NS)),c_PERIODS_COUNTER_LGTH);
constant c_BIT_RATE_UCLK_TICKS_1_Mbit: unsigned :=
to_unsigned((1000 / integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LGTH);
to_unsigned((1000 / integer(c_QUARTZ_PERIOD_NS)),c_PERIODS_COUNTER_LGTH);
constant c_BIT_RATE_UCLK_TICKS_2_5_Mbit: unsigned :=
to_unsigned((400 /integer(C_QUARTZ_PERIOD)),c_PERIODS_COUNTER_LGTH);
to_unsigned((400 /integer(c_QUARTZ_PERIOD_NS)),c_PERIODS_COUNTER_LGTH);
constant c_BIT_RATE_UCLK_TICKS_5_Mbit: unsigned :=
to_unsigned((200 /integer(c_QUARTZ_PERIOD_NS)),c_PERIODS_COUNTER_LGTH);
-- Creation of a table with the c_BIT_RATE_UCLK_TICKS info per bit rate
type t_uclk_ticks is array (Natural range <>) of unsigned (c_PERIODS_COUNTER_LGTH-1 downto 0);
......@@ -151,7 +157,7 @@ package wf_package is
(0 => (c_BIT_RATE_UCLK_TICKS_31_25Kbit),
1 => (c_BIT_RATE_UCLK_TICKS_1_Mbit),
2 => (c_BIT_RATE_UCLK_TICKS_2_5_Mbit),
3 => (c_BIT_RATE_UCLK_TICKS_2_5_Mbit));
3 => (c_BIT_RATE_UCLK_TICKS_5_Mbit));
---------------------------------------------------------------------------------------------------
......
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---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC masterFIP core registers
---------------------------------------------------------------------------------------
-- File : fmc_masterfip_csr_pkg.vhd
-- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
-- Created : 10/17/16 12:35:48
-- File : masterfip_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 02/09/17 10:52:07
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
......@@ -14,12 +14,12 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mrfip_wbgen2_pkg is
package masterfip_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_mrfip_in_registers is record
type t_masterfip_in_registers is record
ds1820_temper_i : std_logic_vector(15 downto 0);
ds1820_id_lsb_i : std_logic_vector(31 downto 0);
ds1820_id_msb_i : std_logic_vector(31 downto 0);
......@@ -31,7 +31,7 @@ package mrfip_wbgen2_pkg is
silen_time_cnt_i : std_logic_vector(30 downto 0);
tx_stat_stop_i : std_logic;
tx_stat_ena_i : std_logic;
tx_stat_curr_byte_indx_i : std_logic_vector(15 downto 0);
tx_stat_curr_byte_indx_i : std_logic_vector(8 downto 0);
fd_wdg_i : std_logic;
fd_cd_i : std_logic;
fd_wdg_tstamp_i : std_logic_vector(31 downto 0);
......@@ -40,7 +40,7 @@ package mrfip_wbgen2_pkg is
rx_stat_pream_ok_i : std_logic;
rx_stat_frame_ok_i : std_logic;
rx_stat_frame_crc_err_i : std_logic;
rx_stat_bytes_num_i : std_logic_vector(15 downto 0);
rx_stat_bytes_num_i : std_logic_vector(8 downto 0);
rx_stat_curr_word_indx_i : std_logic_vector(6 downto 0);
rx_stat_crc_err_cnt_i : std_logic_vector(31 downto 0);
rx_payld_ctrl_i : std_logic_vector(7 downto 0);
......@@ -113,7 +113,7 @@ package mrfip_wbgen2_pkg is
rx_payld_reg67_i : std_logic_vector(31 downto 0);
end record;
constant c_mrfip_in_registers_init_value: t_mrfip_in_registers := (
constant c_masterfip_in_registers_init_value: t_masterfip_in_registers := (
ds1820_temper_i => (others => '0'),
ds1820_id_lsb_i => (others => '0'),
ds1820_id_msb_i => (others => '0'),
......@@ -209,22 +209,21 @@ package mrfip_wbgen2_pkg is
-- Output registers (WB slave -> user design)
type t_mrfip_out_registers is record
type t_masterfip_out_registers is record
rst_core_o : std_logic;
rst_fd_o : std_logic;
dbg_o : std_logic_vector(31 downto 0);
adc_1v8_shdn_n_o : std_logic;
adc_m5v_shdn_n_o : std_logic;
adc_5v_en_n_o : std_logic;
adc_prim_conn_n_o : std_logic;
adc_sec_conn_n_o : std_logic;
dac_config_value_o : std_logic_vector(15 downto 0);
dac_config_load_o : std_logic;
ext_sync_term_en_o : std_logic;
ext_sync_dir_o : std_logic;
ext_sync_oe_n_o : std_logic;
ext_sync_tst_n_o : std_logic;
ext_sync_p_cnt_rst_o : std_logic;
led_rx_act_o : std_logic;
led_rx_err_o : std_logic;
led_tx_act_o : std_logic;
led_tx_err_o : std_logic;
led_ext_sync_used_o : std_logic;
led_ext_sync_act_o : std_logic;
led_ext_sync_err_o : std_logic;
led_dbg_o : std_logic_vector(23 downto 0);
ext_sync_ctrl_term_en_o : std_logic;
ext_sync_ctrl_dir_o : std_logic;
ext_sync_ctrl_oe_n_o : std_logic;
ext_sync_ctrl_p_cnt_rst_o : std_logic;
macrocyc_lgth_o : std_logic_vector(30 downto 0);
macrocyc_start_o : std_logic;
turnar_lgth_o : std_logic_vector(30 downto 0);
......@@ -233,7 +232,7 @@ package mrfip_wbgen2_pkg is
silen_start_o : std_logic;
tx_ctrl_rst_o : std_logic;
tx_ctrl_start_o : std_logic;
tx_ctrl_bytes_num_o : std_logic_vector(15 downto 0);
tx_ctrl_bytes_num_o : std_logic_vector(8 downto 0);
rx_ctrl_rst_o : std_logic;
tx_payld_ctrl_o : std_logic_vector(7 downto 0);
tx_payld_reg1_o : std_logic_vector(31 downto 0);
......@@ -305,22 +304,21 @@ package mrfip_wbgen2_pkg is
tx_payld_reg67_o : std_logic_vector(31 downto 0);
end record;
constant c_mrfip_out_registers_init_value: t_mrfip_out_registers := (
constant c_masterfip_out_registers_init_value: t_masterfip_out_registers := (
rst_core_o => '0',
rst_fd_o => '0',
dbg_o => (others => '0'),
adc_1v8_shdn_n_o => '0',
adc_m5v_shdn_n_o => '0',
adc_5v_en_n_o => '0',
adc_prim_conn_n_o => '0',
adc_sec_conn_n_o => '0',
dac_config_value_o => (others => '0'),
dac_config_load_o => '0',
ext_sync_term_en_o => '0',
ext_sync_dir_o => '0',
ext_sync_oe_n_o => '0',
ext_sync_tst_n_o => '0',
ext_sync_p_cnt_rst_o => '0',
led_rx_act_o => '0',
led_rx_err_o => '0',
led_tx_act_o => '0',
led_tx_err_o => '0',
led_ext_sync_used_o => '0',
led_ext_sync_act_o => '0',
led_ext_sync_err_o => '0',
led_dbg_o => (others => '0'),
ext_sync_ctrl_term_en_o => '0',
ext_sync_ctrl_dir_o => '0',
ext_sync_ctrl_oe_n_o => '0',
ext_sync_ctrl_p_cnt_rst_o => '0',
macrocyc_lgth_o => (others => '0'),
macrocyc_start_o => '0',
turnar_lgth_o => (others => '0'),
......@@ -400,12 +398,12 @@ package mrfip_wbgen2_pkg is
tx_payld_reg66_o => (others => '0'),
tx_payld_reg67_o => (others => '0')
);
function "or" (left, right: t_mrfip_in_registers) return t_mrfip_in_registers;
function "or" (left, right: t_masterfip_in_registers) return t_masterfip_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body mrfip_wbgen2_pkg is
package body masterfip_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
......@@ -426,8 +424,8 @@ end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_mrfip_in_registers) return t_mrfip_in_registers is
variable tmp: t_mrfip_in_registers;
function "or" (left, right: t_masterfip_in_registers) return t_masterfip_in_registers is
variable tmp: t_masterfip_in_registers;
begin
tmp.ds1820_temper_i := f_x_to_zero(left.ds1820_temper_i) or f_x_to_zero(right.ds1820_temper_i);
tmp.ds1820_id_lsb_i := f_x_to_zero(left.ds1820_id_lsb_i) or f_x_to_zero(right.ds1820_id_lsb_i);
......
......@@ -30,223 +30,227 @@ wait %d900
-------------------------------------------------------------------------------
--------------- RESETS ---------------
-- reset inactive
wr 0000000000030000 F CAFE0003
wr 0000000000010000 F CAFE0000
wait %d20
-- reset active
wr 0000000000030000 F CAFE0000
wait %d20
-- core and FD reset active
wr 000000000010000 F CAFE0003
wait %d40
-- FD reset active
wr 0000000000010000 F CAFE0002
wait %d40
-- reset inactive
wr 0000000000030000 F CAFE0003
wr 0000000000010000 F CAFE0000
wait %d20
----- CHECK COUNTERS FUNCTINALITY -----
-- macrocycle cnt start
--wr 000000000003001C F 80004880
--wr 000000000001001C F 80004880
--wait %d20
--wr 000000000003001C F 00002A6D
--wr 000000000001001C F 00002A6D
-- turnar counter top
--wr 0000000000030020 F 000007D0
--wr 0000000000010020 F 000007D0
--wait %d20
-- silen counter top
--wr 0000000000030024 F 00000FA0
--wr 000000000010024 F 00000FA0
--wait %d20
--------------- ID_DAT ---------------
-- tx_rst
wr 0000000000030048 F 00000001
wr 0000000000010040 F 00000001
wait %d10
wr 0000000000030048 F 00000000
wr 0000000000010040 F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000030180 F 00000003
wr 0000000000010178 F 00000003
wait %d20
-- data bytes varid = 0503 for agent to consume
wr 0000000000030184 F 00000305
wr 000000000001017C F 00000305
wait %d20
-- tx_start
wr 0000000000030048 F 00000202
wr 0000000000010040 F 00000202
wait %d20000
--------------- RP_DAT ---------------
-- tx_rst
wr 0000000000030048 F 00000001
wr 0000000000010040 F 00000001
wait %d10
wr 0000000000030048 F 00000000
wr 0000000000010040 F 00000000
wait %d20
-- control byte of rp_dat
wr 0000000000030180 F 00000002
wr 0000000000010178 F 00000002
wait %d20
-- data bytes
wr 0000000000030184 F BBAA0340
wr 000000000001017C F BBAA0340
wait %d20
wr 0000000000030188 F EEDDCC05
wr 0000000000010180 F EEDDCC05
wait %d20
-- tx_start
wr 0000000000030048 F 00000502
wr 0000000000010040 F 00000502
wait %d20000
wr 0000000000030048 F 00000000
wr 0000000000010040 F 00000000
wait %d20000
--------------- ID_DAT ---------------
-- tx_rst
wr 0000000000030048 F 00000001
wr 0000000000010040 F 00000001
wait %d10
wr 0000000000030048 F 00000000
wr 0000000000010040 F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000030180 F 00000003
wr 0000000000010178 F 00000003
wait %d20
-- data bytes varid = 1403 for agent to send identification
wr 0000000000030184 F 00000310 -------------------------0314
wr 000000000001017C F 00000310 -------------------------0314
wait %d20
-- tx_start
wr 0000000000030048 F 00000202
wr 0000000000010040 F 00000202
wait %d200
-- deactivate tx_start
wr 0000000000030048 F 00000000
wr 0000000000010040 F 00000000
-- release rx_rst
wr 0000000000030048 F 00000000
wr 0000000000010040 F 00000000
wait %d40000
-- read received data
rd 0000000000030070 F 00000002
rd 0000000000010070 F 00000002
wait %d20
rd 0000000000030048 F 03800550
rd 0000000000010040 F 03800550
wait %d40000
--------------- ID_DAT ---------------
tx_rst
wr 0000000000030048 F 00000001
wr 0000000000010040 F 00000001
wait %d10
wr 0000000000030048 F 00000000
wr 0000000000010040 F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000030180 F 00000003
wr 0000000000010178 F 00000003
wait %d20
-- data bytes varid = 0603 for agent to produce
wr 0000000000030184 F 00000306
wr 000000000001017C F 00000306
wait %d20
-- tx_start
wr 0000000000030048 F 00000202
wr 0000000000010040 F 00000202
wait %d20
-- deactivate tx_start
wr 0000000000030048 F 00000000
wr 0000000000010040 F 00000000
-- release rx_rst
wr 0000000000030048 F 00000000
wr 0000000000010040 F 00000000
wait %d40000
-- read received data
rd 0000000000030070 F 00000000 FFFFFFFF -- XXXXXX02 FFFFFFFF
rd 0000000000010070 F 00000000 FFFFFFFF -- XXXXXX02 FFFFFFFF
wait %d20
rd 0000000000030058 F 00000000 FFFFFFFF -- BC870940 FFFFFFFF
rd 0000000000010058 F 00000000 FFFFFFFF -- BC870940 FFFFFFFF
wait %d20
rd 000000000003005C F 00000000 FFFFFFFF -- B07D75EF FFFFFFFF
rd 000000000001005C F 00000000 FFFFFFFF -- B07D75EF FFFFFFFF
wait %d20
rd 0000000000030060 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010060 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030068 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010068 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 000000000003006C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 000000000001006C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030070 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010070 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030074 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010074 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030078 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010078 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 000000000003007C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 000000000001007C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030080 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010080 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030084 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010084 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030088 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010088 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 000000000003008C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 000000000001008C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030090 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010090 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030094 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010094 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030098 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000010098 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 000000000003009C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 000000000001009C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300A0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100A0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300A4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100A4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300A8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100A8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300AC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100AC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300B0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100B0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300B4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100B4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300B8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100B8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300BC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100BC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300C0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100C0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300C4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100C4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300C8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100C8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300CC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100CC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300D0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100D0 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300D4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100D4 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300D8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100D8 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 00000000000300DC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 00000000000100DC F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
wait %d40000
--------------- RP_FIN ---------------
-- control byte of rp_fin
wr 0000000000030180 F 00000040
wr 0000000000010178 F 00000040
wait %d20
-- rx_rst
wr 0000000000030048 F 00000001
wr 0000000000010040 F 00000001
wait %d20
-- tx_start
wr 0000000000030048 F 00000002
wr 0000000000010040 F 00000002
wait %d20000
\ No newline at end of file
......@@ -24,23 +24,35 @@ use IEEE.numeric_std.all;
library nanoFIP_lib;
use nanoFIP_lib.all;
library work;
use work.wishbone_pkg.all;
use work.spec_node_pkg.all;
use work.wrn_mqueue_pkg.all;
use work.wr_node_pkg.all;
use work.masterFIP_pkg.all;
use work.masterfip_wbgen2_pkg.all;
use work.gencores_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity tb_masterFIP is
end tb_masterFIP;
architecture behavioral of tb_masterFIP is
component spec_masterFIP
component spec_masterfip_mt
generic(
g_span : integer :=32;
g_width : integer :=32;
values_for_simul : boolean :=FALSE
--g_span : integer :=32;
--g_width : integer :=32;
g_simulation : boolean :=TRUE
);
port(
-- interface with GNUM circuit
rst_n_a_i : in std_logic;
l_rst_n_i : in std_logic;
-- P2L Direction
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_clkp_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clkn_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
p2l_dframe_i: in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
......@@ -50,8 +62,8 @@ architecture behavioral of tb_masterFIP is
rx_error_o : out std_logic; -- Receive Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Virtual channel ready
-- L2P Direction
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
l2p_clkp_o : out std_logic; -- Transmitter Source Synchronous Clock+
l2p_clkn_o : out std_logic; -- Transmitter Source Synchronous Clock-
l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
l2p_dframe_o: out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
......@@ -60,13 +72,13 @@ architecture behavioral of tb_masterFIP is
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i: in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
--irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
ext_sync_i : in std_logic;
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
......@@ -79,10 +91,10 @@ architecture behavioral of tb_masterFIP is
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
pcb_ver_i : in std_logic_vector(3 downto 0);
prsnt_m2c_n_i : in std_logic;
fmc_prsnt_m2c_n_i : in std_logic;
clk_20m_vcxo_i : in std_logic
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic
);
end component;
......@@ -365,6 +377,8 @@ signal spec_led_red : std_logic;
signal consu_data : std_logic_vector (15 downto 0);
signal nanoFIP_rxcdn, nanoFIP_txena, nanoFIP_txck, nanoFIP_rstno ,nanoFIP_wdgn : std_logic;
signal nanoFIP_clk : std_logic;
signal clk_125m_pllref_p : std_logic := '1';
signal clk_125m_pllref_n : std_logic := '0';
signal ext_sync : std_logic := '0';
......@@ -436,7 +450,7 @@ signal spare : std_logic;
signal m_id : std_logic_vector (3 downto 0); --! Model identification settings
signal c_id : std_logic_vector (3 downto 0); --! Constructor identification settings
signal p3_lgth : std_logic_vector (2 downto 0); --! Produced variable data length
signal slone : std_logic; --! Stand-alone mode
signal slone : std_logic; --! Stand-alone mode
signal nostat : std_logic; --! No NanoFIP status transmission
-----------------------------------------------------------------------------
......@@ -450,17 +464,17 @@ signal spare : std_logic;
begin
dut: spec_masterFIP
dut: spec_masterfip_mt
generic map(
g_span => 32,
g_width => 32,
values_for_simul => TRUE
--g_span => 32,
--g_width => 32,
g_simulation => TRUE
)
port map(
-- interface with GNUM circuit
rst_n_a_i => rst_n,
p2l_clk_p_i => p2l_clkp,
p2l_clk_n_i => p2l_clkn,
l_rst_n_i => rst_n,
p2l_clkp_i => p2l_clkp,
p2l_clkn_i => p2l_clkn,
p2l_data_i => p2l_data,
p2l_dframe_i => p2l_dframe,
p2l_valid_i => p2l_valid,
......@@ -469,8 +483,8 @@ begin
p_wr_rdy_o => p_wr_rdy,
rx_error_o => rx_error,
vc_rdy_i => vc_rdy,
l2p_clk_p_o => l2p_clkp,
l2p_clk_n_o => l2p_clkn,
l2p_clkp_o => l2p_clkp,
l2p_clkn_o => l2p_clkn,
l2p_data_o => l2p_data,
l2p_dframe_o => l2p_dframe,
l2p_valid_o => l2p_valid,
......@@ -480,7 +494,7 @@ begin
p_rd_d_rdy_i => p_rd_d_rdy,
tx_error_i => tx_error,
ext_sync_i => ext_sync,
ext_sync_i => ext_sync,
speed_b0_i => '1',
speed_b1_i => '0',
......@@ -495,10 +509,10 @@ begin
fd_txena_o => fd_txena,
-- other signals on the spec card
pcb_ver_i => (others => '0'),
prsnt_m2c_n_i => '0',
fmc_prsnt_m2c_n_i => '0',
clk_20m_vcxo_i => spec_clk_i);
clk_125m_pllref_p_i => clk_125m_pllref_p,
clk_125m_pllref_n_i => clk_125m_pllref_n);
......@@ -729,8 +743,9 @@ begin
spec_clock: process
begin
spec_clk_i <= not (spec_clk_i) after 1 ns;
wait for spec_clk_period/2;
clk_125m_pllref_p <= not (clk_125m_pllref_p) after 1 ns;
clk_125m_pllref_n <= not (clk_125m_pllref_n) after 1 ns;
wait for pll_clk_period/2;
end process;
-- nanoFIP_clock: process
......
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......@@ -71,8 +71,8 @@ NET "ext_sync_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_tst_n_o" LOC = U8;
NET "ext_sync_tst_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_oe_o" LOC = W6;
NET "ext_sync_oe_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_oe_n_o" LOC = W6;
NET "ext_sync_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_dir_o" LOC = Y6;
NET "ext_sync_dir_o" IOSTANDARD = "LVCMOS25";
......
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