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MasterFIP - Gateware
Commit 8a4e7097 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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sim not dependent on proasic3

parent f667cd35
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Showing with 85 additions and 256 deletions
sim/spec/tb_masterfip.do
View file @ 8a4e7097
......@@ -21,8 +21,8 @@ vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_private_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd"
vcom -explicit -93 "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/generic/inferred_sync_fifo.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/generic/inferred_async_fifo.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd"
vcom -explicit -93 "../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd"
......@@ -79,7 +79,7 @@ vlog "../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/l
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/generic/generic_shiftreg_fifo.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_eb_cycle_gen.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_lr_wbgen2_pkg.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_csr_wbgen2_pkg.vhd"
......@@ -131,11 +131,9 @@ vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_s
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
vlib proasic3
vcom -explicit -93 "../../../../../Microsemi/Libero_v11.4/Designer/lib/vtl/95/proasic3.vhd"
vlib nanoFIP_lib
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_package.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/dualram_512x8.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_package.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/dualram_512x8.vhd"
vcom -explicit -93 "../../rtl/masterfip_wbgen2_pkg.vhd"
vcom -explicit -93 "../../ip_cores/nanofip/src/wf_incr_counter.vhd"
vcom -explicit -93 "../../ip_cores/nanofip/src/wf_decr_counter.vhd"
......@@ -167,10 +165,10 @@ vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_pr
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_incr_counter.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_dualram_512x8_clka_rd_clkb_wr.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_decr_counter.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_crc.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_incr_counter.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_dualram_512x8_clka_rd_clkb_wr.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_decr_counter.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_crc.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/util.vhd"
vcom -explicit -93 "../../rtl/masterFIP_pkg.vhd"
vcom -explicit -93 "../../ip_cores/nanofip/src/wf_tx_serializer.vhd"
......@@ -198,17 +196,17 @@ vcom -explicit -93 "../../ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_co
vcom -explicit -93 "../../ip_cores/etherbone-core/hdl/eb_master_core/eb_master_top.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd"
vcom -explicit -93 "../../sim/spec/testbench/tb_package.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_tx_serializer.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_tx_osc.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_status_bytes_gen.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_rx_osc.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_rx_deserializer.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_rx_deglitcher.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_prod_permit.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_prod_data_lgth_calc.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_prod_bytes_retriever.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_cons_outcome.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_cons_bytes_processor.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_tx_serializer.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_tx_osc.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_status_bytes_gen.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_rx_osc.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_rx_deserializer.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_rx_deglitcher.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_prod_permit.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_prod_data_lgth_calc.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_prod_bytes_retriever.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_cons_outcome.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_cons_bytes_processor.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/textutil.vhd"
vcom -explicit -93 "../../sim/spec/testbench/encounter.vhd"
vcom -explicit -93 "../../rtl/masterfip_wbgen2_csr.vhd"
......@@ -231,27 +229,28 @@ vcom -explicit -93 "../../sim/spec/testbench/wishbone_monitor.vhd"
vcom -explicit -93 "../../sim/spec/testbench/wishbone_interface.vhd"
vcom -explicit -93 "../../sim/spec/testbench/user_sequencer.vhd"
vcom -explicit -93 "../../sim/spec/testbench/user_config.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_wb_controller.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_reset_unit.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_production.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_model_constr_decoder.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_jtag_controller.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_fd_transmitter.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_fd_receiver.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_engine_control.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/wf_consumption.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_wb_controller.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_reset_unit.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_production.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_model_constr_decoder.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_jtag_controller.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_fd_transmitter.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_fd_receiver.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_engine_control.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/wf_consumption.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/mem_model.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/cmd_router1.vhd"
vcom -explicit -93 "../../rtl/fmc_masterFIP_core.vhd"
vcom -explicit -93 "../../ip_cores/wr-node-core/hdl/top/spec/node_template/spec_node_template.vhd"
vcom -explicit -93 "../../top/spec/spec_masterfip_mt.vhd"
vcom -explicit -93 "../../sim/spec/testbench/user_interface.vhd"
vcom -explicit -93 -work nanoFIP_lib "../../sim/spec/testbench/nanoFIP_lib/nanofip.vhd"
vcom -explicit -93 -work nanofip_lib "../../sim/spec/testbench/nanofip_lib/nanofip.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/gn412x_bfm.vhd"
vcom -explicit -93 "../../sim/spec/testbench/gnum_model/cmd_router.vhd"
vcom -explicit -93 "../../sim/spec/testbench/board_settings.vhd"
vcom -explicit -93 "../../sim/spec/testbench/tb_masterFIP.vhd"
vlog "C:/EDA/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v"
vlog $env(XILINX)/verilog/src/glbl.v
#
# Call vsim to invoke simulator
#
......
syn/spec/spec_masterfip_mt.xise
View file @ 8a4e7097
......@@ -68,6 +68,7 @@
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Custom Do File Behavioral" xil_pn:value="../../sim/spec/tb_masterfip.do" xil_pn:valueState="non-default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
......@@ -276,8 +277,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_masterFIP/dut" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.spec_masterfip_mt" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_masterFIP" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.tb_masterFIP" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -300,7 +301,7 @@
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.spec_masterfip_mt" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.tb_masterFIP" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
......@@ -317,10 +318,10 @@
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Float" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Automatic Do File" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
......
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