Commit 9922c526 authored by Evangelia Gousiou's avatar Evangelia Gousiou

changed implementation parameters (starting placer cost table) to meet timing

parent 2b615c20
This diff is collapsed.
......@@ -9899,12 +9899,12 @@ cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_p2l_dma_master/cmp_to_wb_fifo/
=========================================================================
Total REAL time to Xst completion: 170.00 secs
Total CPU time to Xst completion: 169.77 secs
Total REAL time to Xst completion: 172.00 secs
Total CPU time to Xst completion: 172.57 secs
-->
Total memory usage is 626616 kilobytes
Total memory usage is 630904 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 3946 ( 0 filtered)
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......@@ -307,7 +307,7 @@
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="3" xil_pn:valueState="non-default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="default"/>
......
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