Skip to content

M
MasterFIP - Gateware
Commit 9aa29601 authored by Evangelia Gousiou's avatar Evangelia Gousiou
Browse files
Options

- changes on the test bench; added nanoFIP node as a library 

- added 2 out HMQs
- changed cpu_mem_sizes
- added crossbar that gives access to both CPUs to the fmc_masterfip_core
- added logic for the fd_wdgn and fd_txerr handling
- relevant changes on fmc_masterfip_csr.wb regs
parent 6ddb678f
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 3577 additions and 2805 deletions
rtl/fmc_masterFIP_core.vhd
View file @ 9aa29601
......@@ -218,7 +218,7 @@ architecture rtl of fmc_masterFIP_core is
signal tx_rst, tx_host_rst, tx_host_rst_p, fd_txd, fd_txck : std_logic;
signal tx_frame : tx_frame_t;
signal tx_ctrl_byte : std_logic_vector(7 downto 0);
signal tx_bytes_num, tx_byte_index : std_logic_vector(8 downto 0); -- up to 263 bytes
signal tx_bytes_num, tx_byte_index : std_logic_vector(15 downto 0); -- up to 263 bytes
-- rx
signal rx_host_rst, rx_host_rst_p, rx_rst : std_logic;
signal rx_fss_received_p, rx_fss_received : std_logic;
......@@ -227,6 +227,10 @@ architecture rtl of fmc_masterFIP_core is
signal rx_frame : rx_frame_t;
signal rx_ctrl_byte, rx_byte : std_logic_vector(7 downto 0);
signal rx_byte_index, rx_bytes_num : std_logic_vector(15 downto 0);
-- fd_wdgn, fd_txer
signal fd_wdgn_tstamp, fd_txer_tstamp : std_logic_vector(30 downto 0);
signal fd_wdg, fd_wdgn_p,fd_txer,fd_txer_p, fd_txer_cnt_reinit : std_logic;
signal fd_txer_cnt : std_logic_vector(31 downto 0);
-- ADC
signal adc_sec_conn_n, adc_prim_conn_n : std_logic;
-- ext_sync
......@@ -320,12 +324,16 @@ begin
mf_tx_ctrl_start_o => tx_start, -- tx start serializing a frame; then converted to 1-tick-long pulse
mf_tx_ctrl_bytes_num_o => tx_bytes_num, -- number of bytes to serialize; sampled upon tx_start
-- tx status
mf_tx_stat_stop_i => tx_completed, -- 16x25ns long pulse upon the end of delivery of a frame
mf_tx_stat_byte_index_i => tx_byte_index, -- index of current byte being serialized
mf_tx_stat_stop_i => tx_completed, -- 16x10ns long pulse upon the end of delivery of a frame
mf_tx_stat_curr_byte_indx_i => tx_byte_index, -- index of current byte being serialized
mf_tx_stat_ena_i => fd_txena, -- FIELDRIVE txena, signal generated by the tx_serializer
mf_fd_wdgn_i => fd_wdgn_i, -- FIELDRIVE watchdog, signal comes from the FIELDRIVE
mf_fd_txer_i => fd_txer_i, -- FIELDRIVE txerr, signal comes from the FIELDRIVE
-- rx control/status
-- fd_wdgn
mf_fd_wdgn_tstamp_i => fd_wdgn_tstamp,
mf_fd_wdgn_act_i => fd_wdg,
-- fd_txer
mf_fd_txer_cnt_i => fd_txer_cnt,
mf_fd_txer_tstamp_i => fd_txer_tstamp,
-- rx control
mf_rx_ctrl_rst_o => rx_host_rst, -- note: this is not a pulse
-- rx status
mf_rx_stat_pream_ok_i => rx_fss_received,
......@@ -539,6 +547,11 @@ begin
---------------------------------------------------------------------------------------------------
-- macrocycle counter --
---------------------------------------------------------------------------------------------------
-- in an application where an external synchronization pulse is expected for every macrocyle,
-- the macrocyc_lgth is set slightly larger than the external synchronization period; therefore
-- th macrocycle counter should not be reaching zero; if it reaches zero, it means that the
-- external synchronization pulse did not arrive in time
-- counter counting the macrocycle time
cmp_macrocycle_time_cnt: decr_counter
generic map(width => 31)
......@@ -561,29 +574,6 @@ begin
data_i => macrocyc_host_load,
ppulse_o => macrocyc_host_load_p);
-- in an application where an external synchronization pulse is expected for every macrocyle,
-- the macrocyc_lgth is set slightly larger than the external synchronization period; therefore
-- th macrocycle counter should not be reaching zero; if it reaches zero, it means that the
-- external synchronization pulse did not arrive in time
cmp_out_of_sync_led: gc_extend_pulse
generic map
(g_width => 1000000)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => macrocyc_cnt_zero_p,
extended_o => out_of_sync_led);
cmp_sync_led: gc_extend_pulse
generic map
(g_width => 1000000)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => ext_sync_p,
extended_o => sync_led);
-- counter counting the number of macrocycles; when it fills up it restarts
cmp_macrocycles_cnt:incr_counter
generic map(g_counter_lgth => 32)
......@@ -709,7 +699,7 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- extending the rx_crc_wrong_p until a core_rst or rx_rst is received
-- extending the until a core_rst or rx_rst is received
p_rx_crc_wrong_extend : process(clk_i)
begin
if rising_edge(clk_i) then
......@@ -801,17 +791,113 @@ begin
data_i => tx_host_rst,
ppulse_o => tx_host_rst_p);
-- extension of the tx_completed_p so as to ensure capturing by the wrnc
-- TODO: keep high and only reset upon reading from the MT
cmp_tx_extend_p : gc_extend_pulse
generic map (g_width => 32) -- 32 ticks long
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- extending the tx_completed_p until a core_rst or rx_rst is received
p_tx_completed_extend : process(clk_i)
begin
if rising_edge(clk_i) then
if(core_rst_n = '0' or tx_host_rst_p = '1' or tx_start_p = '1') then
tx_completed <= '0';
else
if tx_completed_p = '1' then
tx_completed <= '1';
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- FielDrive TXERR, WDGN --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- edge detection on the fd_wdgn_i signal
cmp_fd_wdgn_i_pulse_detect: gc_sync_ffs
generic map(g_sync_edge => "negative")
port map
(clk_i => clk_i,
rst_n_i => rst_n,
data_i => fd_wdgn_i,
ppulse_o => fd_wdgn_p);
-- process that registers the macrocycle_cnt value upon the last fd_wdgn_p of a macrocycle
p_fd_wdgn_capture : process(clk_i)
begin
if rising_edge(clk_i) then
if(core_rst_n = '0' or macrocyc_load_p = '1' or fd_host_rstn = '0') then
fd_wdg <= '0';
fd_wdgn_tstamp <= macrocyc_cnt;
else
if fd_wdgn_p = '1' then
fd_wdg <= '1';
fd_wdgn_tstamp <= macrocyc_cnt;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- edge detection on the fd_txer_i signal
cmp_fd_txer_i_pulse_detect: gc_sync_ffs
generic map(g_sync_edge => "negative")
port map
(clk_i => clk_i,
rst_n_i => rst_n,
data_i => fd_txer_i,
ppulse_o => fd_txer_p);
-- counter counting the number of fd_wdgn_p
cmp_fd_wdgn_cnt:incr_counter
generic map(g_counter_lgth => 32)
port map
(clk_i => clk_i,
counter_incr_i => fd_txer_p,
counter_reinit_i => fd_txer_cnt_reinit,
counter_is_full_o => open,
counter_o => fd_txer_cnt);
fd_txer_cnt_reinit <= '1' when core_rst_n = '0' or macrocyc_load_p = '1' or fd_host_rstn = '0'
else '0';
-- process that registers the macrocycle_cnt value upon the last fd_txer_p of a macrocycle
p_fd_txer_capture : process(clk_i)
begin
if rising_edge(clk_i) then
if(core_rst_n = '0' or macrocyc_load_p = '1' or fd_host_rstn = '0') then
fd_txer <= '1';
fd_txer_tstamp <= macrocyc_cnt;
else
if fd_txer_p = '1' then
fd_txer <= '0';
fd_txer_tstamp <= macrocyc_cnt;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- LEDs --
---------------------------------------------------------------------------------------------------
cmp_out_of_sync_led: gc_extend_pulse
generic map
(g_width => 1000000)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => tx_completed_p,
extended_o => tx_completed);
pulse_i => macrocyc_cnt_zero_p,
extended_o => out_of_sync_led);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_sync_led: gc_extend_pulse
generic map
(g_width => 1000000)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => ext_sync_p,
extended_o => sync_led);
---------------------------------------------------------------------------------------------------
-- aux --
---------------------------------------------------------------------------------------------------
......
rtl/fmc_masterfip_csr.vhd
View file @ 9aa29601
This diff is collapsed.
rtl/masterFIP_pkg.vhd
View file @ 9aa29601
......@@ -226,13 +226,16 @@ package masterFIP_pkg is
mf_tx_ctrl_rst_o : out std_logic;
mf_tx_ctrl_start_o : out std_logic;
mf_tx_ctrl_bytes_num_o : out std_logic_vector(8 downto 0);
mf_tx_ctrl_bytes_num_o : out std_logic_vector(15 downto 0);
mf_tx_stat_stop_i : in std_logic;
mf_tx_stat_byte_index_i : in std_logic_vector(8 downto 0);
mf_tx_stat_curr_byte_indx_i : in std_logic_vector(15 downto 0);
mf_tx_stat_ena_i : in std_logic;
mf_fd_wdgn_i : in std_logic;
mf_fd_txer_i : in std_logic;
mf_fd_wdgn_tstamp_i : in std_logic_vector(30 downto 0);
mf_fd_wdgn_act_i : in std_logic;
mf_fd_txer_cnt_i : in std_logic_vector(31 downto 0);
mf_fd_txer_tstamp_i : in std_logic_vector(30 downto 0);
mf_rx_ctrl_rst_o : out std_logic;
mf_rx_stat_pream_ok_i : in std_logic;
......@@ -493,11 +496,11 @@ package masterFIP_pkg is
speed_i : in std_logic_vector (1 downto 0);
rst_i : in std_logic;
tx_start_p_i : in std_logic;
tx_bytes_num_i : in std_logic_vector (8 downto 0);
tx_bytes_num_i : in std_logic_vector (15 downto 0);
tx_frame_i : in tx_frame_t;
tx_ctrl_byte_i : in std_logic_vector (7 downto 0);
-----------------------------------------------------------------
tx_byte_index_o : out std_logic_vector (8 downto 0);
tx_byte_index_o : out std_logic_vector (15 downto 0);
tx_end_p_o : out std_logic;
tx_data_o : out std_logic;
tx_enable_o : out std_logic;
......
rtl/masterfip_tx.vhd
View file @ 9aa29601
......@@ -107,7 +107,7 @@ entity masterfip_tx is port(
-- this represents the max length of a frame
-- upon tx_start_p_i only tx_bytes_num_i are read and transmitted
tx_bytes_num_i : in std_logic_vector(8 downto 0); -- number of bytes to be serialized
tx_bytes_num_i : in std_logic_vector(15 downto 0); -- number of bytes to be serialized
tx_ctrl_byte_i : in std_logic_vector(7 downto 0); -- frame CTRL byte
......@@ -115,7 +115,7 @@ entity masterfip_tx is port(
-- OUTPUTS
tx_byte_index_o : out std_logic_vector(8 downto 0); -- index of the byte currently being serialized (0-262)
tx_byte_index_o : out std_logic_vector(15 downto 0); -- index of the byte currently being serialized (0-262)
tx_end_p_o : out std_logic; -- pulse upon termination of a transmission (CRC & FES included)
......@@ -134,13 +134,13 @@ end entity masterfip_tx;
architecture struc of masterfip_tx is
-- frame bytes
signal prod_bytes_c : unsigned(8 downto 0);
signal prod_bytes_c : unsigned(15 downto 0);
signal ctrl_byte, tx_byte : std_logic_vector(7 downto 0);
signal prod_frame : tx_frame_t;
signal word32_num : integer range 0 to 66;
signal word32 : std_logic_vector(31 downto 0);
-- bytes counter
signal bytes_num : std_logic_vector(8 downto 0);
signal bytes_num : std_logic_vector(15 downto 0);
signal prod_data_lgth_match : std_logic;
signal last_data_byte_p, last_data_byte_p_d : std_logic;
-- wf_tx_osc
......@@ -205,7 +205,7 @@ begin
-- Instantiation of a wf_incr_counter for the counting of the number of the bytes that are
-- being serialized.
cmp_tx_bytes_cnt: wf_incr_counter
generic map(g_counter_lgth => 9)
generic map(g_counter_lgth => 16)
port map(
uclk_i => clk_i,
counter_reinit_i => tx_start_p_i,
......
rtl/wbgen/fmc_masterfip_csr.h
View file @ 9aa29601
This diff is collapsed.
rtl/wbgen/fmc_masterfip_csr.htm
View file @ 9aa29601
This diff is collapsed.
rtl/wbgen/fmc_masterfip_csr.wb
View file @ 9aa29601
......@@ -222,7 +222,10 @@ peripheral {
field {
name = "speed";
description = "WorldFIP speed: 00: 31.25Kbps | 01: 1Mbps | 10: 2.5 Mbps | 11: 5 Mbps";
description = "WorldFIP speed: 00: 31.25Kbps\
01: 1Mbps\
10: 2.5 Mbps\
11: 5 Mbps";
type = SLV;
size = 2;
access_bus = READ_ONLY;
......@@ -394,7 +397,7 @@ peripheral {
note that the max WorldFIP frame size = 263 bytes (without preamble, CRC, postamble)";
prefix = "bytes_num";
type = SLV;
size = 9;
size = 16;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
......@@ -411,25 +414,14 @@ peripheral {
field {
name = "tx ended";
description = "indication that the serializer finished the delivery of a frame";
description = "indication that the serializer finished the delivery of a frame\
the bit stays active until a rstn_core or a tx_ctrl_rst or a tx_ctrl_strt";
prefix = "stop";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "tx current byte";
description = "index of the byte currently being serialized.\
note that the max WorldFIP frame size = 263 bytes (without preamble, CRC, postamble)";
prefix = "byte_index";
type = SLV;
size = 9;
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "tx enable";
description = "fieldrive fd_txena signal;\
......@@ -441,37 +433,85 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "tx status current byte index";
description = "index of the current byte being serialized;\
the counting starts from 0 after the preamble...";
prefix = "curr_byte_indx";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
-------------------------------------------------------------------------------
-- fieldrive status signals --
-------------------------------------------------------------------------------
reg {
name = "fieldrive status";
prefix = "fd";
name = "fieldrive wdgn";
prefix = "fd_wdgn";
field {
name = "fd watchdog";
description = "fd_wdgn input from the fieldrive chip\
read 0: no problemo i think\
read 1: something 's wrong...";
prefix = "wdgn";
type = BIT;
name = "fd_wdgn_tstamp";
description = "timestamp of the moment in the macrocycle when the fd_wdgn\
was activated.\
The field is automatically cleared upon a new macrocycle or\
upon a rstn_fd or rstn_core";
prefix = "tstamp";
type = SLV;
size = 31;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "fd transmitter error";
description = "fd_txer input from the fieldrive chip\
read 0: no problemo i think\
read 1: something 's wrong...";
prefix = "txer";
name = "fd_wdg_act";
description = "read 1: the fd_wdgn has been activated\
read 0: no problemo\
Note that if triggered, the fd_wdgn stays active until a fd_rstn";
prefix = "act";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
reg {
name = "fieldrive txer cnt";
prefix = "fd_txer_cnt";
field {
name = "fd_txer_cnt";
description = "counter of the number of fd_txer rising edges that appear in this\
current macrocycle.\
The field is automatically cleared upon a new macrocycle or\
upon a rstn_fd or rstn_core";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "fieldrive txer tstamp";
prefix = "fd_txer_tstamp";
field {
name = "fd_txer_tstamp";
description = "timestamp of the last moment in the macrocycle when the fd_txer\
was activated.\
The field is automatically cleared upon a new macrocycle or\
upon a rstn_fd or rstn_core";
type = SLV;
size = 31;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
-------------------------------------------------------------------------------
-- deserializer ctrl --
......@@ -504,8 +544,9 @@ peripheral {
field {
name = "rx preamble detected";
description = "indication that the deserializer has detected a preamble;\
the bit stays high until a reset of the deserializer (this takes place\
automatically upon the activation of the serializer, or upon a mf_rx_ctrl_rst)";
the bit stays active until a reset of the deserializer (this takes place\
automatically upon the activation of the serializer, or upon a rx_ctrl_rst\
or upon a core_rstn)";
prefix = "pream_ok";
type = BIT;
access_bus = READ_ONLY;
......@@ -517,7 +558,8 @@ peripheral {
description = "indication that the deserializer has finished with the reception of a complete frame;\
the preamble, CRC and postambe of the frame are all ok\
the bit stays high until a reset of the deserializer (this takes place\
automatically upon the activation of the serializer, or upon a rx_rst)";
automatically upon the activation of the serializer, or upon a rx_ctrl_rst\
or upon a rstn_core)";
prefix = "frame_ok";
type = BIT;
access_bus = READ_ONLY;
......
sim/spec/data_vectors/masterFIP_test.vec
View file @ 9aa29601
......@@ -60,101 +60,101 @@ wait %d20
--------------- ID_DAT ---------------
-- tx_rst
wr 000000000003003C F 00000001
wr 0000000000030038 F 00000001
wait %d10
wr 000000000003003C F 00000000
wr 0000000000030038 F 00000000
wait %d20
-- control byte of id_dat
wr 000000000003015C F 00000003
wr 0000000000030160 F 00000003
wait %d20
-- data bytes varid = 0503 for agent to consume
wr 0000000000030160 F 00000305
wr 0000000000030164 F 00000305
wait %d20
-- tx_start
wr 000000000003003C F 00000202
wr 0000000000030038 F 00000202
wait %d20000
--------------- RP_DAT ---------------
-- tx_rst
wr 000000000003003C F 00000001
wr 0000000000030038 F 00000001
wait %d10
wr 000000000003003C F 00000000
wr 0000000000030038 F 00000000
wait %d20
-- control byte of rp_dat
wr 000000000003015C F 00000002
wr 0000000000030160 F 00000002
wait %d20
-- data bytes
wr 0000000000030160 F BBAA0340 -- for 2 data bytes: BBAA0340 | for 8 data bytes: BBAA0940
wr 0000000000030164 F BBAA0340 -- for 2 data bytes: BBAA0340 | for 8 data bytes: BBAA0940
wait %d20
wr 000000000003015c F EEDDCC05 -- for 2 data bytes: EEDDCC05 | for 8 data bytes: FFEEDDCC
wr 0000000000030168 F EEDDCC05 -- for 2 data bytes: EEDDCC05 | for 8 data bytes: FFEEDDCC
-- tx_start
wr 000000000003003C F 00000502 -- for 2 data bytes: 00000502 | for 8 data bytes: 00000B02
wr 0000000000030038 F 00000502 -- for 2 data bytes: 00000502 | for 8 data bytes: 00000B02
wait %d40000
--------------- ID_DAT ---------------
-- tx_rst
wr 000000000003003C F 00000001
wr 0000000000030038 F 00000001
wait %d10
wr 000000000003003C F 00000000
wr 0000000000030038 F 00000000
wait %d20
-- control byte of id_dat
wr 000000000003015C F 00000003
wr 0000000000030160 F 00000003
wait %d20
-- data bytes varid = 1403 for agent to send identification
wr 0000000000030160 F 00000314
wr 0000000000030164 F 00000314
wait %d20
-- tx_start
wr 000000000003003C F 00000202
wr 0000000000030038 F 00000202
wait %d20
-- deactivate tx_start
wr 000000000003003C F 00000000
wr 0000000000030038 F 00000000
-- release rx_rst
wr 0000000000030048 F 00000000
wr 0000000000030044 F 00000000
wait %d40000
-- read received data
rd 0000000000030050 F 00000002
wait %d20
rd 000000000003004c F 03800550
rd 0000000000030044 F 03800550
wait %d40000
--------------- ID_DAT ---------------
tx_rst
wr 000000000003003C F 00000001
wr 0000000000030038 F 00000001
wait %d10
wr 000000000003003C F 00000000
wr 0000000000030038 F 00000000
wait %d20
-- control byte of id_dat
wr 000000000003015C F 00000003
wr 0000000000030160 F 00000003
wait %d20
-- data bytes varid = 0603 for agent to produce
wr 0000000000030160 F 00000306
wr 0000000000030164 F 00000306
wait %d20
-- tx_start
wr 000000000003003C F 00000202
wr 0000000000030038 F 00000202
wait %d20
-- deactivate tx_start
wr 000000000003003C F 00000000
wr 0000000000030038 F 00000000
-- release rx_rst
wr 0000000000030048 F 00000000
wr 0000000000030044 F 00000000
wait %d40000
-- read received data
......@@ -244,5 +244,5 @@ wr 0000000000030048 F 00000001
wait %d20
-- tx_start
wr 000000000003003C F 00000002
wr 0000000000030038 F 00000002
wait %d20000
\ No newline at end of file
sim/spec/data_vectors/user_logic_config.txt
View file @ 9aa29601
10 ns -- User clock period (should not be modified during test)
10 ns -- Wishbone interface clock period (should not be modified during test)
25 ns -- User clock period (should not be modified during test)
25 ns -- Wishbone interface clock period (should not be modified during test)
3 us -- Power-on reset length
1 us -- User reset length
1 us -- Wishbone interface reset length
20000 ms -- validity time: time for which the configuration above is valid
20000 ms -- validity time: time for which the configuration above is valid
sim/spec/testbench/nanoFIP/wf_dualram_512x8_clka_rd_clkb_wr.vhd → sim/spec/testbench/nanoFIP_lib/wf_dualram_512x8_clka_rd_clkb_wr.vhd
View file @ 9aa29601
......@@ -129,7 +129,7 @@ begin
-- end generate;
--------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- for triplication: Combinatorial Majority_Voter
-- for triplication: Majority_Voter: data_porta_o <= (s_data_o_A_array(0) and s_data_o_A_array(1)) or
......
sim/spec/testbench/tb_masterFIP.vhd
View file @ 9aa29601
......@@ -21,6 +21,9 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library nanoFIP_lib;
use nanoFIP_lib.all;
entity tb_masterFIP is
end tb_masterFIP;
......
syn/spec/spec_masterfip.xise
View file @ 9aa29601
This diff is collapsed.
top/spec/spec_masterfip.vhd
View file @ 9aa29601
......@@ -148,8 +148,6 @@ entity spec_masterfip is
speed_b0_i : in std_logic; -- WorldFIP bus Speed
speed_b1_i : in std_logic;
bus_term_en_n_o : out std_logic; -- WorldFIP bus termination
fd_rxcdn_i : in std_logic; -- FielDrive
fd_rxd_i : in std_logic;
fd_txer_i : in std_logic;
......@@ -430,8 +428,6 @@ begin
-- Bus speed
speed_b0_i => speed_b0_i,
speed_b1_i => speed_b1_i,
-- Bus termination
bus_term_en_n_o => bus_term_en_n_o,
-- FielDrive
fd_rxcdn_i => fd_rxcdn_i,
fd_rxd_i => fd_rxd_i,
......
top/spec_mt/spec_masterfip_mt.vhd
View file @ 9aa29601
......@@ -141,34 +141,33 @@ architecture rtl of spec_masterfip_mt is
-- Mock Turtle constants
-- eva: check comments on the WRNC..
-- HMQ out : 6
-- HMQ in : 2
constant c_hmq_config : t_wrn_mqueue_config :=
(out_slot_count => 6,
(out_slot_count => 8,
out_slot_config =>
(0 => (width => 128, entries => 4), -- output of the MT CPU0 with all WorldFIP consumed data
1 => (width => 128, entries => 4), -- output of the MT CPU0 with interrupts
2 => (width => 128, entries => 4), -- output of the MT CPU0 with ack of commands for bus configuration
3 => (width => 128, entries => 4), -- output of the MT CPU1 with ack of commands for bus configuration
4 => (width => 128, entries => 4),
5 => (width => 128, entries => 4),
(0 => (width => 128, entries => 4), -- output of the MT CPU0 with WorldFIP periodic consumed variables
1 => (width => 128, entries => 4), -- output of the MT CPU0 with WorldFIP aperiodic consumed variables
2 => (width => 128, entries => 4), -- output of the MT CPU0 with WorldFIP aperiodic messages
3 => (width => 128, entries => 4), -- output of the MT CPU1 with WorldFIP SMMPS periodic variables
4 => (width => 128, entries => 4), -- output of the MT CPU0 with WorldFIP SMMPS aperiodic variables
5 => (width => 128, entries => 4), -- output of the MT CPU0 with IRQs to the application (variable/messages programmed with an irq flag)
6 => (width => 128, entries => 4), -- output of the MT CPU0 command response
7 => (width => 128, entries => 4), -- output of the MT CPU1 command response
others => (0, 0)),
in_slot_count => 2,
in_slot_config =>
(0 => (width => 128, entries => 4), -- input to MT CPU0 with commands from the host for the bus configuration
1 => (width => 128, entries => 4), -- input to MT CPU1 with commands from the host for...
(0 => (width => 128, entries => 4), -- input to MT CPU0 with commands from the host for the bus configuration (commands like: PROGRAM_BA,HW_RESET, BA_START, BA_RUNNING)
1 => (width => 128, entries => 4), -- input to MT CPU1 with commands from the host for the control of CPU0 (handles commands like: BA_STOP,SET_VAR_PAYLOAD, SET_MSG_PAYLOAD, GET_REPORT, GET_PRESENT_LIST, GET_IDENT_VAR)
-- (change of payload, stop BA, reset CPU0 etc through shared mem, host asking for report)
others => (0, 0)));
-- eva: do we need the rmq??
-- Remote Message Queue, for playing with White Rabbit/Etherbone
-- 1) outgoing path (CPU -> WR Network): 16 entries x 128 words
-- 2) incoming path (WR Network -> CPU): 16 entries x 128 words.
-- RMQs not used
constant c_rmq_config : t_wrn_mqueue_config :=
(out_slot_count => 1,
out_slot_config =>
(0 => (width => 128, entries => 4),
others => (0, 0)),
in_slot_count => 1,
in_slot_config =>
(0 => (width => 128, entries => 4),
others => (0, 0)));
(out_slot_count => 0,
out_slot_config => (others => (0, 0)),
in_slot_count => 0,
in_slot_config => (others => (0, 0)));
constant c_node_config : t_wr_node_config :=
(app_id => x"0f1dc03e",
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment