Commit 9b3f06b2 authored by Evangelia Gousiou's avatar Evangelia Gousiou

updated simulations

parent 9922c526
......@@ -431,7 +431,7 @@ begin
counter_is_full_o => num_of_macrocyc_cnt_full,
counter_o => reg_to_mt.macrocyc_num_cnt_i);
-- -- -- -- -- -- -- -- -- -- --
num_of_macrocyc_cnt_reinit <= core_rst_n or num_of_macrocyc_cnt_full;
num_of_macrocyc_cnt_reinit <= core_rst or num_of_macrocyc_cnt_full;
---------------------------------------------------------------------------------------------------
......@@ -787,7 +787,7 @@ begin
-- after the board power-up/ reset.
cmp_onewire: gc_ds182x_interface
generic map (freq => c_QUARTZ_FREQ_MHZ_INT)
generic map (freq => C_QUARTZ_FREQ_MHZ_INT)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
......@@ -800,7 +800,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- pps generator based on the 100 MHz clk
cmp_pps_gen: wf_decr_counter
generic map(g_counter_lgth => c_1SEC_CNT_LGTH)
generic map(g_counter_lgth => C_1SEC_CNT_LGTH)
port map
(uclk_i => clk_i,
counter_rst_i => core_rst,
......
......@@ -102,16 +102,10 @@ package masterFIP_pkg is
type tx_frame_t is array (C_MAX_FRAME_WORDS-1 downto 0) of data_word;
---------------------------------------------------------------------------------------------------
-- Constants regarding the One-Wire interface --
---------------------------------------------------------------------------------------------------
-- constant c_FMC_ONEWIRE_NB : integer := 1;
---------------------------------------------------------------------------------------------------
-- Constant regarding the deglitch filters --
---------------------------------------------------------------------------------------------------
-- constant c_DEGLITCH_THRESHOLD : natural := 10; -- declared in the wf_package
-- constant C_DEGLITCH_THRESHOLD : natural := 10; -- declared in the wf_package
---------------------------------------------------------------------------------------------------
......@@ -121,37 +115,37 @@ package masterFIP_pkg is
---------------------------------------------------------------------------------------------------
component fmc_masterFIP_core is
generic
(g_span : integer := 32;
g_width : integer := 32;
values_for_simul : boolean := FALSE);
(g_span : integer := 32;
g_width : integer := 32;
g_simul : boolean := FALSE);
port
(clk_i : in std_logic;
rst_n_i : in std_logic;
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
onewire_b : inout std_logic;
fd_rxcdn_a_i : in std_logic;
fd_rxd_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_wdgn_a_i : in std_logic;
fd_rstn_o : out std_logic;
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
ext_sync_term_en_o : out std_logic;
ext_sync_dir_o : out std_logic;
ext_sync_oe_n_o : out std_logic;
ext_sync_a_i : in std_logic;
leds_o : out std_logic_vector(g_width-1 downto 0);
wb_adr_i : in std_logic_vector(g_span-1 downto 0);
wb_dat_i : in std_logic_vector(g_width-1 downto 0);
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_we_i : in std_logic;
wb_cyc_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_dat_o : out std_logic_vector(g_width-1 downto 0));
(clk_i : in std_logic;
rst_n_i : in std_logic;
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
onewire_b : inout std_logic;
fd_rxcdn_a_i : in std_logic;
fd_rxd_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_wdgn_a_i : in std_logic;
fd_rstn_o : out std_logic;
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
ext_sync_term_en_o : out std_logic;
ext_sync_dir_o : out std_logic;
ext_sync_oe_n_o : out std_logic;
ext_sync_a_i : in std_logic;
leds_o : out std_logic_vector(g_width-1 downto 0);
wb_adr_i : in std_logic_vector(g_span-1 downto 0);
wb_dat_i : in std_logic_vector(g_width-1 downto 0);
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_we_i : in std_logic;
wb_cyc_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_dat_o : out std_logic_vector(g_width-1 downto 0));
end component;
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_csr.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 07/14/17 20:28:20
-- Created : 07/17/17 17:07:34
-- Version : 0x00020000
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 07/14/17 20:28:20
-- Created : 07/17/17 17:07:34
-- Version : 0x00020000
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
......
This diff is collapsed.
This diff is collapsed.
......@@ -30,19 +30,19 @@ wait %d900
-------------------------------------------------------------------------------
--------------- RESETS ---------------
-- reset inactive
wr 0000000000010000 F CAFE0000
wr 0000000000010004 F CAFE0000
wait %d20
-- core and FD reset active
wr 000000000010000 F CAFE0003
wr 0000000000010004 F CAFE0003
wait %d40
-- FD reset active
wr 0000000000010000 F CAFE0002
wr 0000000000010004 F CAFE0002
wait %d40
-- reset inactive
wr 0000000000010000 F CAFE0000
wr 0000000000010004 F CAFE0000
wait %d20
......@@ -64,105 +64,105 @@ wait %d20
--------------- ID_DAT ---------------
-- tx_rst
wr 0000000000010040 F 00000001
wr 0000000000010044 F 00000001
wait %d10
wr 0000000000010040 F 00000000
wr 0000000000010044 F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000010178 F 00000003
wr 000000000001017C F 00000003
wait %d20
-- data bytes varid = 0503 for agent to consume
wr 000000000001017C F 00000305
wr 0000000000010180 F 00000305
wait %d20
-- tx_start
wr 0000000000010040 F 00000202
wr 0000000000010044 F 00000202
wait %d20000
--------------- RP_DAT ---------------
-- tx_rst
wr 0000000000010040 F 00000001
wr 0000000000010044 F 00000001
wait %d10
wr 0000000000010040 F 00000000
wr 0000000000010044 F 00000000
wait %d20
-- control byte of rp_dat
wr 0000000000010178 F 00000002
wr 000000000001017C F 00000002
wait %d20
-- data bytes
wr 000000000001017C F BBAA0340
wr 0000000000010180 F BBAA0340
wait %d20
wr 0000000000010180 F EEDDCC05
wr 0000000000010184 F EEDDCC05
wait %d20
-- tx_start
wr 0000000000010040 F 00000502
wr 0000000000010044 F 00000502
wait %d20000
wr 0000000000010040 F 00000000
wr 0000000000010044 F 00000000
wait %d20000
--------------- ID_DAT ---------------
-- tx_rst
wr 0000000000010040 F 00000001
wr 0000000000010044 F 00000001
wait %d10
wr 0000000000010040 F 00000000
wr 0000000000010044 F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000010178 F 00000003
wr 000000000001017C F 00000003
wait %d20
-- data bytes varid = 1403 for agent to send identification
wr 000000000001017C F 00000310 -------------------------0314
wr 0000000000010180 F 00000310 -------------------------0314
wait %d20
-- tx_start
wr 0000000000010040 F 00000202
wr 0000000000010044 F 00000202
wait %d200
-- deactivate tx_start
wr 0000000000010040 F 00000000
wr 0000000000010044 F 00000000
-- release rx_rst
wr 0000000000010040 F 00000000
wr 0000000000010044 F 00000000
wait %d40000
-- read received data
rd 0000000000010070 F 00000002
rd 0000000000010074 F 00000002
wait %d20
rd 0000000000010040 F 03800550
rd 0000000000010044 F 03800550
wait %d40000
--------------- ID_DAT ---------------
tx_rst
wr 0000000000010040 F 00000001
wr 0000000000010044 F 00000001
wait %d10
wr 0000000000010040 F 00000000
wr 0000000000010044 F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000010178 F 00000003
wr 000000000001017C F 00000003
wait %d20
-- data bytes varid = 0603 for agent to produce
wr 000000000001017C F 00000306
wr 0000000000010180 F 00000306
wait %d20
-- tx_start
wr 0000000000010040 F 00000202
wr 0000000000010044 F 00000202
wait %d20
-- deactivate tx_start
wr 0000000000010040 F 00000000
wr 0000000000010044 F 00000000
-- release rx_rst
wr 0000000000010040 F 00000000
wr 0000000000010044 F 00000000
wait %d40000
-- read received data
......@@ -244,13 +244,13 @@ wait %d40000
--------------- RP_FIN ---------------
-- control byte of rp_fin
wr 0000000000010178 F 00000040
wr 000000000001017C F 00000040
wait %d20
-- rx_rst
wr 0000000000010040 F 00000001
wr 0000000000010044 F 00000001
wait %d20
-- tx_start
wr 0000000000010040 F 00000002
wr 0000000000010044 F 00000002
wait %d20000
\ No newline at end of file
......@@ -65,7 +65,7 @@ architecture behavioral of tb_masterFIP is
generic(
--g_span : integer :=32;
--g_width : integer :=32;
g_simulation : boolean :=TRUE
g_simul : boolean :=TRUE
);
port(
-- interface with GNUM circuit
......@@ -427,7 +427,7 @@ begin
generic map(
--g_span => 32,
--g_width => 32,
g_simulation => TRUE
g_simul => TRUE
)
port map(
-- interface with GNUM circuit
......
This diff is collapsed.
This source diff could not be displayed because it is too large. You can view the blob instead.
This source diff could not be displayed because it is too large. You can view the blob instead.
This diff is collapsed.
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -155,7 +155,7 @@ use work.masterfip_wbgen2_pkg.all; -- for the masterfip_wbgen2_csr records
entity spec_masterfip_mt is
generic (g_simulation : boolean := false);
generic (g_simul : boolean := false);
port
(-- Carrier signals
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -370,7 +370,7 @@ begin
---------------------------------------------------------------------------------------------------
cmp_mock_turtle : spec_node_template
generic map
(g_simulation => g_simulation,
(g_simulation => g_simul,
g_with_wr_phy => false, -- no White Rabbit support, dah
g_with_white_rabbit => false,
g_double_wrnode_core_clock => false,
......@@ -462,7 +462,7 @@ begin
generic map
(g_span => 32,
g_width => 32,
values_for_simul => g_simulation)
g_simul => g_simul)
port map
(clk_i => clk_100m_sys,
rst_n_i => rst_n_sys,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment