Commit 9b3f06b2 authored by Evangelia Gousiou's avatar Evangelia Gousiou

updated simulations

parent 9922c526
......@@ -431,7 +431,7 @@ begin
counter_is_full_o => num_of_macrocyc_cnt_full,
counter_o => reg_to_mt.macrocyc_num_cnt_i);
-- -- -- -- -- -- -- -- -- -- --
num_of_macrocyc_cnt_reinit <= core_rst_n or num_of_macrocyc_cnt_full;
num_of_macrocyc_cnt_reinit <= core_rst or num_of_macrocyc_cnt_full;
---------------------------------------------------------------------------------------------------
......@@ -787,7 +787,7 @@ begin
-- after the board power-up/ reset.
cmp_onewire: gc_ds182x_interface
generic map (freq => c_QUARTZ_FREQ_MHZ_INT)
generic map (freq => C_QUARTZ_FREQ_MHZ_INT)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
......@@ -800,7 +800,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- pps generator based on the 100 MHz clk
cmp_pps_gen: wf_decr_counter
generic map(g_counter_lgth => c_1SEC_CNT_LGTH)
generic map(g_counter_lgth => C_1SEC_CNT_LGTH)
port map
(uclk_i => clk_i,
counter_rst_i => core_rst,
......
......@@ -102,16 +102,10 @@ package masterFIP_pkg is
type tx_frame_t is array (C_MAX_FRAME_WORDS-1 downto 0) of data_word;
---------------------------------------------------------------------------------------------------
-- Constants regarding the One-Wire interface --
---------------------------------------------------------------------------------------------------
-- constant c_FMC_ONEWIRE_NB : integer := 1;
---------------------------------------------------------------------------------------------------
-- Constant regarding the deglitch filters --
---------------------------------------------------------------------------------------------------
-- constant c_DEGLITCH_THRESHOLD : natural := 10; -- declared in the wf_package
-- constant C_DEGLITCH_THRESHOLD : natural := 10; -- declared in the wf_package
---------------------------------------------------------------------------------------------------
......@@ -121,37 +115,37 @@ package masterFIP_pkg is
---------------------------------------------------------------------------------------------------
component fmc_masterFIP_core is
generic
(g_span : integer := 32;
g_width : integer := 32;
values_for_simul : boolean := FALSE);
(g_span : integer := 32;
g_width : integer := 32;
g_simul : boolean := FALSE);
port
(clk_i : in std_logic;
rst_n_i : in std_logic;
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
onewire_b : inout std_logic;
fd_rxcdn_a_i : in std_logic;
fd_rxd_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_wdgn_a_i : in std_logic;
fd_rstn_o : out std_logic;
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
ext_sync_term_en_o : out std_logic;
ext_sync_dir_o : out std_logic;
ext_sync_oe_n_o : out std_logic;
ext_sync_a_i : in std_logic;
leds_o : out std_logic_vector(g_width-1 downto 0);
wb_adr_i : in std_logic_vector(g_span-1 downto 0);
wb_dat_i : in std_logic_vector(g_width-1 downto 0);
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_we_i : in std_logic;
wb_cyc_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_dat_o : out std_logic_vector(g_width-1 downto 0));
(clk_i : in std_logic;
rst_n_i : in std_logic;
speed_b0_i : in std_logic;
speed_b1_i : in std_logic;
onewire_b : inout std_logic;
fd_rxcdn_a_i : in std_logic;
fd_rxd_a_i : in std_logic;
fd_txer_a_i : in std_logic;
fd_wdgn_a_i : in std_logic;
fd_rstn_o : out std_logic;
fd_txck_o : out std_logic;
fd_txd_o : out std_logic;
fd_txena_o : out std_logic;
ext_sync_term_en_o : out std_logic;
ext_sync_dir_o : out std_logic;
ext_sync_oe_n_o : out std_logic;
ext_sync_a_i : in std_logic;
leds_o : out std_logic_vector(g_width-1 downto 0);
wb_adr_i : in std_logic_vector(g_span-1 downto 0);
wb_dat_i : in std_logic_vector(g_width-1 downto 0);
wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_we_i : in std_logic;
wb_cyc_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_dat_o : out std_logic_vector(g_width-1 downto 0));
end component;
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_csr.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 07/14/17 20:28:20
-- Created : 07/17/17 17:07:34
-- Version : 0x00020000
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 07/14/17 20:28:20
-- Created : 07/17/17 17:07:34
-- Version : 0x00020000
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
......
/*
Register definitions for slave core: FMC masterFIP core registers
* File : masterfip_wbgen2_csr.h
* Author : auto-generated by wbgen2 from masterfip_csr.wb
* Created : 07/17/17 17:07:35
* Version : 0x00020000
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_MASTERFIP_CSR_WB
#define __WBGEN2_REGDEFS_MASTERFIP_CSR_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* version definition */
#define WBGEN2_MASTERFIP_VERSION 0x00020000
/* definitions for register: Version register */
/* definitions for field: Version identifier in reg: Version register */
#define MASTERFIP_VER_ID_MASK WBGEN2_GEN_MASK(0, 32)
#define MASTERFIP_VER_ID_SHIFT 0
#define MASTERFIP_VER_ID_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define MASTERFIP_VER_ID_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: rst */
/* definitions for field: reset of the masterFIP core in reg: rst */
#define MASTERFIP_RST_CORE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: reset of the FielDrive chip in reg: rst */
#define MASTERFIP_RST_FD WBGEN2_GEN_MASK(1, 1)
/* definitions for register: core id */
/* definitions for register: leds and debug */
/* definitions for field: rx act green led in reg: leds and debug */
#define MASTERFIP_LED_RX_ACT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: rx err red led in reg: leds and debug */
#define MASTERFIP_LED_RX_ERR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: tx act green led in reg: leds and debug */
#define MASTERFIP_LED_TX_ACT WBGEN2_GEN_MASK(2, 1)
/* definitions for field: tx err red led in reg: leds and debug */
#define MASTERFIP_LED_TX_ERR WBGEN2_GEN_MASK(3, 1)
/* definitions for field: ext sync act green led in reg: leds and debug */
#define MASTERFIP_LED_EXT_SYNC_ACT WBGEN2_GEN_MASK(4, 1)
/* definitions for field: ext sync err red led in reg: leds and debug */
#define MASTERFIP_LED_EXT_SYNC_ERR WBGEN2_GEN_MASK(5, 1)
/* definitions for field: dbg in reg: leds and debug */
#define MASTERFIP_LED_DBG_MASK WBGEN2_GEN_MASK(8, 24)
#define MASTERFIP_LED_DBG_SHIFT 8
#define MASTERFIP_LED_DBG_W(value) WBGEN2_GEN_WRITE(value, 8, 24)
#define MASTERFIP_LED_DBG_R(reg) WBGEN2_GEN_READ(reg, 8, 24)
/* definitions for register: fmc temperature */
/* definitions for register: fmc unique id lsb */
/* definitions for register: fmc unique id msb */
/* definitions for register: ext sync ctrl */
/* definitions for field: termination enable in reg: ext sync ctrl */
#define MASTERFIP_EXT_SYNC_CTRL_TERM_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: transceiver direction in reg: ext sync ctrl */
#define MASTERFIP_EXT_SYNC_CTRL_DIR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: transceiver output enable negative logic in reg: ext sync ctrl */
#define MASTERFIP_EXT_SYNC_CTRL_OE_N WBGEN2_GEN_MASK(2, 1)
/* definitions for field: pulses counter reset in reg: ext sync ctrl */
#define MASTERFIP_EXT_SYNC_CTRL_P_CNT_RST WBGEN2_GEN_MASK(8, 1)
/* definitions for field: counting options in reg: ext sync ctrl */
#define MASTERFIP_EXT_SYNC_CTRL_OPT WBGEN2_GEN_MASK(16, 1)
/* definitions for field: safe window in reg: ext sync ctrl */
#define MASTERFIP_EXT_SYNC_CTRL_SAFE_WIND WBGEN2_GEN_MASK(24, 1)
/* definitions for register: ext sync pulses cnt */
/* definitions for register: bus speed */
/* definitions for register: macrocycle lgth */
/* definitions for field: macrocycle lgth in reg: macrocycle lgth */
#define MASTERFIP_MACROCYC_LGTH_MASK WBGEN2_GEN_MASK(0, 31)
#define MASTERFIP_MACROCYC_LGTH_SHIFT 0
#define MASTERFIP_MACROCYC_LGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 31)
#define MASTERFIP_MACROCYC_LGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 31)
/* definitions for field: macrocycle cnt start in reg: macrocycle lgth */
#define MASTERFIP_MACROCYC_START WBGEN2_GEN_MASK(31, 1)
/* definitions for register: macrocycle time cnt */
/* definitions for register: macrocycles number cnt */
/* definitions for register: turnaround lgth */
/* definitions for field: turnaround time in reg: turnaround lgth */
#define MASTERFIP_TURNAR_LGTH_MASK WBGEN2_GEN_MASK(0, 31)
#define MASTERFIP_TURNAR_LGTH_SHIFT 0
#define MASTERFIP_TURNAR_LGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 31)
#define MASTERFIP_TURNAR_LGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 31)
/* definitions for field: turnaround cnt start in reg: turnaround lgth */
#define MASTERFIP_TURNAR_START WBGEN2_GEN_MASK(31, 1)
/* definitions for register: turnaround time cnt */
/* definitions for register: silence lgth */
/* definitions for field: silence time in reg: silence lgth */
#define MASTERFIP_SILEN_LGTH_MASK WBGEN2_GEN_MASK(0, 31)
#define MASTERFIP_SILEN_LGTH_SHIFT 0
#define MASTERFIP_SILEN_LGTH_W(value) WBGEN2_GEN_WRITE(value, 0, 31)
#define MASTERFIP_SILEN_LGTH_R(reg) WBGEN2_GEN_READ(reg, 0, 31)
/* definitions for field: silence cnt start in reg: silence lgth */
#define MASTERFIP_SILEN_START WBGEN2_GEN_MASK(31, 1)
/* definitions for register: silence time cnt */
/* definitions for register: tx ctrl */
/* definitions for field: tx rst in reg: tx ctrl */
#define MASTERFIP_TX_CTRL_RST WBGEN2_GEN_MASK(0, 1)
/* definitions for field: tx strt in reg: tx ctrl */
#define MASTERFIP_TX_CTRL_START WBGEN2_GEN_MASK(1, 1)
/* definitions for field: tx number of bytes in reg: tx ctrl */
#define MASTERFIP_TX_CTRL_BYTES_NUM_MASK WBGEN2_GEN_MASK(8, 16)
#define MASTERFIP_TX_CTRL_BYTES_NUM_SHIFT 8
#define MASTERFIP_TX_CTRL_BYTES_NUM_W(value) WBGEN2_GEN_WRITE(value, 8, 16)
#define MASTERFIP_TX_CTRL_BYTES_NUM_R(reg) WBGEN2_GEN_READ(reg, 8, 16)
/* definitions for register: tx status */
/* definitions for field: tx ended in reg: tx status */
#define MASTERFIP_TX_STAT_STOP WBGEN2_GEN_MASK(0, 1)
/* definitions for field: tx enable in reg: tx status */
#define MASTERFIP_TX_STAT_ENA WBGEN2_GEN_MASK(8, 1)
/* definitions for field: tx status current byte index in reg: tx status */
#define MASTERFIP_TX_STAT_CURR_BYTE_INDX_MASK WBGEN2_GEN_MASK(16, 16)
#define MASTERFIP_TX_STAT_CURR_BYTE_INDX_SHIFT 16
#define MASTERFIP_TX_STAT_CURR_BYTE_INDX_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define MASTERFIP_TX_STAT_CURR_BYTE_INDX_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: FielDrive wdgn, cdn */
/* definitions for field: FielDrive watchdog in reg: FielDrive wdgn, cdn */
#define MASTERFIP_FD_WDG WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FielDrive carrier detect in reg: FielDrive wdgn, cdn */
#define MASTERFIP_FD_CD WBGEN2_GEN_MASK(1, 1)
/* definitions for register: FielDrive wdg timestamp */
/* definitions for register: FielDrive txer cnt */
/* definitions for register: FielDrive txer tstamp */
/* definitions for register: rx ctrl */
/* definitions for field: rx rst in reg: rx ctrl */
#define MASTERFIP_RX_CTRL_RST WBGEN2_GEN_MASK(0, 1)
/* definitions for register: rx status */
/* definitions for field: rx Preamble(FSS) detected in reg: rx status */
#define MASTERFIP_RX_STAT_PREAM_OK WBGEN2_GEN_MASK(0, 1)
/* definitions for field: rx CTRL byte detected in reg: rx status */
#define MASTERFIP_RX_STAT_CTRL_BYTE_OK WBGEN2_GEN_MASK(1, 1)
/* definitions for field: rx frame ok in reg: rx status */
#define MASTERFIP_RX_STAT_FRAME_OK WBGEN2_GEN_MASK(2, 1)
/* definitions for field: rx frame crc error in reg: rx status */
#define MASTERFIP_RX_STAT_FRAME_CRC_ERR WBGEN2_GEN_MASK(3, 1)
/* definitions for field: rx bytes number error in reg: rx status */
#define MASTERFIP_RX_STAT_BYTES_NUM_ERR WBGEN2_GEN_MASK(4, 1)
/* definitions for field: rx number of payload bytes in reg: rx status */
#define MASTERFIP_RX_STAT_BYTES_NUM_MASK WBGEN2_GEN_MASK(8, 16)
#define MASTERFIP_RX_STAT_BYTES_NUM_SHIFT 8
#define MASTERFIP_RX_STAT_BYTES_NUM_W(value) WBGEN2_GEN_WRITE(value, 8, 16)
#define MASTERFIP_RX_STAT_BYTES_NUM_R(reg) WBGEN2_GEN_READ(reg, 8, 16)
/* definitions for register: rx current word index */
/* definitions for register: rx num of frames with CRC error */
/* definitions for register: rx payload ctrl byte */
/* definitions for register: rx payload reg1 */
/* definitions for register: rx payload reg2 */
/* definitions for register: rx payload reg3 */
/* definitions for register: rx payload reg4 */
/* definitions for register: rx payload reg5 */
/* definitions for register: rx payload reg6 */
/* definitions for register: rx payload reg7 */
/* definitions for register: rx payload reg8 */
/* definitions for register: rx payload reg9 */
/* definitions for register: rx payload reg10 */
/* definitions for register: rx payload reg11 */
/* definitions for register: rx payload reg12 */
/* definitions for register: rx payload reg13 */
/* definitions for register: rx payload reg14 */
/* definitions for register: rx payload reg15 */
/* definitions for register: rx payload reg16 */
/* definitions for register: rx payload reg17 */
/* definitions for register: rx payload reg18 */
/* definitions for register: rx payload reg19 */
/* definitions for register: rx payload reg20 */
/* definitions for register: rx payload reg21 */
/* definitions for register: rx payload reg22 */
/* definitions for register: rx payload reg23 */
/* definitions for register: rx payload reg24 */
/* definitions for register: rx payload reg25 */
/* definitions for register: rx payload reg26 */
/* definitions for register: rx payload reg27 */
/* definitions for register: rx payload reg28 */
/* definitions for register: rx payload reg29 */
/* definitions for register: rx payload reg30 */
/* definitions for register: rx payload reg31 */
/* definitions for register: rx payload reg32 */
/* definitions for register: rx payload reg33 */
/* definitions for register: rx payload reg34 */
/* definitions for register: rx payload reg35 */
/* definitions for register: rx payload reg36 */
/* definitions for register: rx payload reg37 */
/* definitions for register: rx payload reg38 */
/* definitions for register: rx payload reg39 */
/* definitions for register: rx payload reg40 */
/* definitions for register: rx payload reg41 */
/* definitions for register: rx payload reg42 */
/* definitions for register: rx payload reg43 */
/* definitions for register: rx payload reg44 */
/* definitions for register: rx payload reg45 */
/* definitions for register: rx payload reg46 */
/* definitions for register: rx payload reg47 */
/* definitions for register: rx payload reg48 */
/* definitions for register: rx payload reg49 */
/* definitions for register: rx payload reg50 */
/* definitions for register: rx payload reg51 */
/* definitions for register: rx payload reg52 */
/* definitions for register: rx payload reg53 */
/* definitions for register: rx payload reg54 */
/* definitions for register: rx payload reg55 */
/* definitions for register: rx payload reg56 */
/* definitions for register: rx payload reg57 */
/* definitions for register: rx payload reg58 */
/* definitions for register: rx payload reg59 */
/* definitions for register: rx payload reg60 */
/* definitions for register: rx payload reg61 */
/* definitions for register: rx payload reg62 */
/* definitions for register: rx payload reg63 */
/* definitions for register: rx payload reg64 */
/* definitions for register: rx payload reg65 */
/* definitions for register: rx payload reg66 */
/* definitions for register: rx payload reg67 */
/* definitions for register: tx ctrl byte */
/* definitions for register: tx payload reg1 */
/* definitions for register: tx payload reg2 */
/* definitions for register: tx payload reg3 */
/* definitions for register: tx payload reg4 */
/* definitions for register: tx payload reg5 */
/* definitions for register: tx payload reg6 */
/* definitions for register: tx payload reg7 */
/* definitions for register: tx payload reg8 */
/* definitions for register: tx payload reg9 */
/* definitions for register: tx payload reg10 */
/* definitions for register: tx payload reg11 */
/* definitions for register: tx payload reg12 */
/* definitions for register: tx payload reg13 */
/* definitions for register: tx payload reg14 */
/* definitions for register: tx payload reg15 */
/* definitions for register: tx payload reg16 */
/* definitions for register: tx payload reg17 */
/* definitions for register: tx payload reg18 */
/* definitions for register: tx payload reg19 */
/* definitions for register: tx payload reg20 */
/* definitions for register: tx payload reg21 */
/* definitions for register: tx payload reg22 */
/* definitions for register: tx payload reg23 */
/* definitions for register: tx payload reg24 */
/* definitions for register: tx payload reg25 */
/* definitions for register: tx payload reg26 */
/* definitions for register: tx payload reg27 */
/* definitions for register: tx payload reg28 */
/* definitions for register: tx payload reg29 */
/* definitions for register: tx payload reg30 */
/* definitions for register: tx payload reg31 */
/* definitions for register: tx payload reg32 */
/* definitions for register: tx payload reg33 */
/* definitions for register: tx payload reg34 */
/* definitions for register: tx payload reg35 */
/* definitions for register: tx payload reg36 */
/* definitions for register: tx payload reg37 */
/* definitions for register: tx payload reg38 */
/* definitions for register: tx payload reg39 */
/* definitions for register: tx payload reg40 */
/* definitions for register: tx payload reg41 */
/* definitions for register: tx payload reg42 */
/* definitions for register: tx payload reg43 */
/* definitions for register: tx payload reg44 */
/* definitions for register: tx payload reg45 */
/* definitions for register: tx payload reg46 */
/* definitions for register: tx payload reg47 */
/* definitions for register: tx payload reg48 */
/* definitions for register: tx payload reg49 */
/* definitions for register: tx payload reg50 */
/* definitions for register: tx payload reg51 */
/* definitions for register: tx payload reg52 */
/* definitions for register: tx payload reg53 */
/* definitions for register: tx payload reg54 */
/* definitions for register: tx payload reg55 */
/* definitions for register: tx payload reg56 */
/* definitions for register: tx payload reg57 */
/* definitions for register: tx payload reg58 */
/* definitions for register: tx payload reg59 */
/* definitions for register: tx payload reg60 */
/* definitions for register: tx payload reg61 */
/* definitions for register: tx payload reg62 */
/* definitions for register: tx payload reg63 */
/* definitions for register: tx payload reg64 */
/* definitions for register: tx payload reg65 */
/* definitions for register: tx payload reg66 */
/* definitions for register: tx payload reg67 */
/* [0x0]: REG Version register */
#define MASTERFIP_REG_VER 0x00000000
/* [0x4]: REG rst */
#define MASTERFIP_REG_RST 0x00000004
/* [0x8]: REG core id */
#define MASTERFIP_REG_ID 0x00000008
/* [0xc]: REG leds and debug */
#define MASTERFIP_REG_LED 0x0000000c
/* [0x10]: REG fmc temperature */
#define MASTERFIP_REG_DS1820_TEMPER 0x00000010
/* [0x14]: REG fmc unique id lsb */
#define MASTERFIP_REG_DS1820_ID_LSB 0x00000014
/* [0x18]: REG fmc unique id msb */
#define MASTERFIP_REG_DS1820_ID_MSB 0x00000018
/* [0x1c]: REG ext sync ctrl */
#define MASTERFIP_REG_EXT_SYNC_CTRL 0x0000001c
/* [0x20]: REG ext sync pulses cnt */
#define MASTERFIP_REG_EXT_SYNC_P_CNT 0x00000020
/* [0x24]: REG bus speed */
#define MASTERFIP_REG_SPEED 0x00000024
/* [0x28]: REG macrocycle lgth */
#define MASTERFIP_REG_MACROCYC 0x00000028
/* [0x2c]: REG macrocycle time cnt */
#define MASTERFIP_REG_MACROCYC_TIME_CNT 0x0000002c
/* [0x30]: REG macrocycles number cnt */
#define MASTERFIP_REG_MACROCYC_NUM_CNT 0x00000030
/* [0x34]: REG turnaround lgth */
#define MASTERFIP_REG_TURNAR 0x00000034
/* [0x38]: REG turnaround time cnt */
#define MASTERFIP_REG_TURNAR_TIME_CNT 0x00000038
/* [0x3c]: REG silence lgth */
#define MASTERFIP_REG_SILEN 0x0000003c
/* [0x40]: REG silence time cnt */
#define MASTERFIP_REG_SILEN_TIME_CNT 0x00000040
/* [0x44]: REG tx ctrl */
#define MASTERFIP_REG_TX_CTRL 0x00000044
/* [0x48]: REG tx status */
#define MASTERFIP_REG_TX_STAT 0x00000048
/* [0x4c]: REG FielDrive wdgn, cdn */
#define MASTERFIP_REG_FD 0x0000004c
/* [0x50]: REG FielDrive wdg timestamp */
#define MASTERFIP_REG_FD_WDG_TSTAMP 0x00000050
/* [0x54]: REG FielDrive txer cnt */
#define MASTERFIP_REG_FD_TXER_CNT 0x00000054
/* [0x58]: REG FielDrive txer tstamp */
#define MASTERFIP_REG_FD_TXER_TSTAMP 0x00000058
/* [0x5c]: REG rx ctrl */
#define MASTERFIP_REG_RX_CTRL 0x0000005c
/* [0x60]: REG rx status */
#define MASTERFIP_REG_RX_STAT 0x00000060
/* [0x64]: REG rx current word index */
#define MASTERFIP_REG_RX_STAT_CURR_WORD_INDX 0x00000064
/* [0x68]: REG rx num of frames with CRC error */
#define MASTERFIP_REG_RX_STAT_CRC_ERR_CNT 0x00000068
/* [0x6c]: REG rx payload ctrl byte */
#define MASTERFIP_REG_RX_PAYLD_CTRL 0x0000006c
/* [0x70]: REG rx payload reg1 */
#define MASTERFIP_REG_RX_PAYLD_REG1 0x00000070
/* [0x74]: REG rx payload reg2 */
#define MASTERFIP_REG_RX_PAYLD_REG2 0x00000074
/* [0x78]: REG rx payload reg3 */
#define MASTERFIP_REG_RX_PAYLD_REG3 0x00000078
/* [0x7c]: REG rx payload reg4 */
#define MASTERFIP_REG_RX_PAYLD_REG4 0x0000007c
/* [0x80]: REG rx payload reg5 */
#define MASTERFIP_REG_RX_PAYLD_REG5 0x00000080
/* [0x84]: REG rx payload reg6 */
#define MASTERFIP_REG_RX_PAYLD_REG6 0x00000084
/* [0x88]: REG rx payload reg7 */
#define MASTERFIP_REG_RX_PAYLD_REG7 0x00000088
/* [0x8c]: REG rx payload reg8 */
#define MASTERFIP_REG_RX_PAYLD_REG8 0x0000008c
/* [0x90]: REG rx payload reg9 */
#define MASTERFIP_REG_RX_PAYLD_REG9 0x00000090
/* [0x94]: REG rx payload reg10 */
#define MASTERFIP_REG_RX_PAYLD_REG10 0x00000094
/* [0x98]: REG rx payload reg11 */
#define MASTERFIP_REG_RX_PAYLD_REG11 0x00000098
/* [0x9c]: REG rx payload reg12 */
#define MASTERFIP_REG_RX_PAYLD_REG12 0x0000009c
/* [0xa0]: REG rx payload reg13 */
#define MASTERFIP_REG_RX_PAYLD_REG13 0x000000a0
/* [0xa4]: REG rx payload reg14 */
#define MASTERFIP_REG_RX_PAYLD_REG14 0x000000a4
/* [0xa8]: REG rx payload reg15 */
#define MASTERFIP_REG_RX_PAYLD_REG15 0x000000a8
/* [0xac]: REG rx payload reg16 */
#define MASTERFIP_REG_RX_PAYLD_REG16 0x000000ac
/* [0xb0]: REG rx payload reg17 */
#define MASTERFIP_REG_RX_PAYLD_REG17 0x000000b0
/* [0xb4]: REG rx payload reg18 */
#define MASTERFIP_REG_RX_PAYLD_REG18 0x000000b4
/* [0xb8]: REG rx payload reg19 */
#define MASTERFIP_REG_RX_PAYLD_REG19 0x000000b8
/* [0xbc]: REG rx payload reg20 */
#define MASTERFIP_REG_RX_PAYLD_REG20 0x000000bc
/* [0xc0]: REG rx payload reg21 */
#define MASTERFIP_REG_RX_PAYLD_REG21 0x000000c0
/* [0xc4]: REG rx payload reg22 */
#define MASTERFIP_REG_RX_PAYLD_REG22 0x000000c4
/* [0xc8]: REG rx payload reg23 */
#define MASTERFIP_REG_RX_PAYLD_REG23 0x000000c8
/* [0xcc]: REG rx payload reg24 */
#define MASTERFIP_REG_RX_PAYLD_REG24 0x000000cc
/* [0xd0]: REG rx payload reg25 */
#define MASTERFIP_REG_RX_PAYLD_REG25 0x000000d0
/* [0xd4]: REG rx payload reg26 */
#define MASTERFIP_REG_RX_PAYLD_REG26 0x000000d4
/* [0xd8]: REG rx payload reg27 */
#define MASTERFIP_REG_RX_PAYLD_REG27 0x000000d8
/* [0xdc]: REG rx payload reg28 */
#define MASTERFIP_REG_RX_PAYLD_REG28 0x000000dc
/* [0xe0]: REG rx payload reg29 */
#define MASTERFIP_REG_RX_PAYLD_REG29 0x000000e0
/* [0xe4]: REG rx payload reg30 */
#define MASTERFIP_REG_RX_PAYLD_REG30 0x000000e4
/* [0xe8]: REG rx payload reg31 */
#define MASTERFIP_REG_RX_PAYLD_REG31 0x000000e8
/* [0xec]: REG rx payload reg32 */
#define MASTERFIP_REG_RX_PAYLD_REG32 0x000000ec
/* [0xf0]: REG rx payload reg33 */
#define MASTERFIP_REG_RX_PAYLD_REG33 0x000000f0
/* [0xf4]: REG rx payload reg34 */
#define MASTERFIP_REG_RX_PAYLD_REG34 0x000000f4
/* [0xf8]: REG rx payload reg35 */
#define MASTERFIP_REG_RX_PAYLD_REG35 0x000000f8
/* [0xfc]: REG rx payload reg36 */
#define MASTERFIP_REG_RX_PAYLD_REG36 0x000000fc
/* [0x100]: REG rx payload reg37 */
#define MASTERFIP_REG_RX_PAYLD_REG37 0x00000100
/* [0x104]: REG rx payload reg38 */
#define MASTERFIP_REG_RX_PAYLD_REG38 0x00000104
/* [0x108]: REG rx payload reg39 */
#define MASTERFIP_REG_RX_PAYLD_REG39 0x00000108
/* [0x10c]: REG rx payload reg40 */
#define MASTERFIP_REG_RX_PAYLD_REG40 0x0000010c
/* [0x110]: REG rx payload reg41 */
#define MASTERFIP_REG_RX_PAYLD_REG41 0x00000110
/* [0x114]: REG rx payload reg42 */
#define MASTERFIP_REG_RX_PAYLD_REG42 0x00000114
/* [0x118]: REG rx payload reg43 */
#define MASTERFIP_REG_RX_PAYLD_REG43 0x00000118
/* [0x11c]: REG rx payload reg44 */
#define MASTERFIP_REG_RX_PAYLD_REG44 0x0000011c
/* [0x120]: REG rx payload reg45 */
#define MASTERFIP_REG_RX_PAYLD_REG45 0x00000120
/* [0x124]: REG rx payload reg46 */
#define MASTERFIP_REG_RX_PAYLD_REG46 0x00000124
/* [0x128]: REG rx payload reg47 */
#define MASTERFIP_REG_RX_PAYLD_REG47 0x00000128
/* [0x12c]: REG rx payload reg48 */
#define MASTERFIP_REG_RX_PAYLD_REG48 0x0000012c
/* [0x130]: REG rx payload reg49 */
#define MASTERFIP_REG_RX_PAYLD_REG49 0x00000130
/* [0x134]: REG rx payload reg50 */
#define MASTERFIP_REG_RX_PAYLD_REG50 0x00000134
/* [0x138]: REG rx payload reg51 */
#define MASTERFIP_REG_RX_PAYLD_REG51 0x00000138
/* [0x13c]: REG rx payload reg52 */
#define MASTERFIP_REG_RX_PAYLD_REG52 0x0000013c
/* [0x140]: REG rx payload reg53 */
#define MASTERFIP_REG_RX_PAYLD_REG53 0x00000140
/* [0x144]: REG rx payload reg54 */
#define MASTERFIP_REG_RX_PAYLD_REG54 0x00000144
/* [0x148]: REG rx payload reg55 */
#define MASTERFIP_REG_RX_PAYLD_REG55 0x00000148
/* [0x14c]: REG rx payload reg56 */
#define MASTERFIP_REG_RX_PAYLD_REG56 0x0000014c
/* [0x150]: REG rx payload reg57 */
#define MASTERFIP_REG_RX_PAYLD_REG57 0x00000150
/* [0x154]: REG rx payload reg58 */
#define MASTERFIP_REG_RX_PAYLD_REG58 0x00000154
/* [0x158]: REG rx payload reg59 */
#define MASTERFIP_REG_RX_PAYLD_REG59 0x00000158
/* [0x15c]: REG rx payload reg60 */
#define MASTERFIP_REG_RX_PAYLD_REG60 0x0000015c
/* [0x160]: REG rx payload reg61 */
#define MASTERFIP_REG_RX_PAYLD_REG61 0x00000160
/* [0x164]: REG rx payload reg62 */
#define MASTERFIP_REG_RX_PAYLD_REG62 0x00000164
/* [0x168]: REG rx payload reg63 */
#define MASTERFIP_REG_RX_PAYLD_REG63 0x00000168
/* [0x16c]: REG rx payload reg64 */
#define MASTERFIP_REG_RX_PAYLD_REG64 0x0000016c
/* [0x170]: REG rx payload reg65 */
#define MASTERFIP_REG_RX_PAYLD_REG65 0x00000170
/* [0x174]: REG rx payload reg66 */
#define MASTERFIP_REG_RX_PAYLD_REG66 0x00000174
/* [0x178]: REG rx payload reg67 */
#define MASTERFIP_REG_RX_PAYLD_REG67 0x00000178
/* [0x17c]: REG tx ctrl byte */
#define MASTERFIP_REG_TX_PAYLD_CTRL 0x0000017c
/* [0x180]: REG tx payload reg1 */
#define MASTERFIP_REG_TX_PAYLD_REG1 0x00000180
/* [0x184]: REG tx payload reg2 */
#define MASTERFIP_REG_TX_PAYLD_REG2 0x00000184
/* [0x188]: REG tx payload reg3 */
#define MASTERFIP_REG_TX_PAYLD_REG3 0x00000188
/* [0x18c]: REG tx payload reg4 */
#define MASTERFIP_REG_TX_PAYLD_REG4 0x0000018c
/* [0x190]: REG tx payload reg5 */
#define MASTERFIP_REG_TX_PAYLD_REG5 0x00000190
/* [0x194]: REG tx payload reg6 */
#define MASTERFIP_REG_TX_PAYLD_REG6 0x00000194
/* [0x198]: REG tx payload reg7 */
#define MASTERFIP_REG_TX_PAYLD_REG7 0x00000198
/* [0x19c]: REG tx payload reg8 */
#define MASTERFIP_REG_TX_PAYLD_REG8 0x0000019c
/* [0x1a0]: REG tx payload reg9 */
#define MASTERFIP_REG_TX_PAYLD_REG9 0x000001a0
/* [0x1a4]: REG tx payload reg10 */
#define MASTERFIP_REG_TX_PAYLD_REG10 0x000001a4
/* [0x1a8]: REG tx payload reg11 */
#define MASTERFIP_REG_TX_PAYLD_REG11 0x000001a8
/* [0x1ac]: REG tx payload reg12 */
#define MASTERFIP_REG_TX_PAYLD_REG12 0x000001ac
/* [0x1b0]: REG tx payload reg13 */
#define MASTERFIP_REG_TX_PAYLD_REG13 0x000001b0
/* [0x1b4]: REG tx payload reg14 */
#define MASTERFIP_REG_TX_PAYLD_REG14 0x000001b4
/* [0x1b8]: REG tx payload reg15 */
#define MASTERFIP_REG_TX_PAYLD_REG15 0x000001b8
/* [0x1bc]: REG tx payload reg16 */
#define MASTERFIP_REG_TX_PAYLD_REG16 0x000001bc
/* [0x1c0]: REG tx payload reg17 */
#define MASTERFIP_REG_TX_PAYLD_REG17 0x000001c0
/* [0x1c4]: REG tx payload reg18 */
#define MASTERFIP_REG_TX_PAYLD_REG18 0x000001c4
/* [0x1c8]: REG tx payload reg19 */
#define MASTERFIP_REG_TX_PAYLD_REG19 0x000001c8
/* [0x1cc]: REG tx payload reg20 */
#define MASTERFIP_REG_TX_PAYLD_REG20 0x000001cc
/* [0x1d0]: REG tx payload reg21 */
#define MASTERFIP_REG_TX_PAYLD_REG21 0x000001d0
/* [0x1d4]: REG tx payload reg22 */
#define MASTERFIP_REG_TX_PAYLD_REG22 0x000001d4
/* [0x1d8]: REG tx payload reg23 */
#define MASTERFIP_REG_TX_PAYLD_REG23 0x000001d8
/* [0x1dc]: REG tx payload reg24 */
#define MASTERFIP_REG_TX_PAYLD_REG24 0x000001dc
/* [0x1e0]: REG tx payload reg25 */
#define MASTERFIP_REG_TX_PAYLD_REG25 0x000001e0
/* [0x1e4]: REG tx payload reg26 */
#define MASTERFIP_REG_TX_PAYLD_REG26 0x000001e4
/* [0x1e8]: REG tx payload reg27 */
#define MASTERFIP_REG_TX_PAYLD_REG27 0x000001e8
/* [0x1ec]: REG tx payload reg28 */
#define MASTERFIP_REG_TX_PAYLD_REG28 0x000001ec
/* [0x1f0]: REG tx payload reg29 */
#define MASTERFIP_REG_TX_PAYLD_REG29 0x000001f0
/* [0x1f4]: REG tx payload reg30 */
#define MASTERFIP_REG_TX_PAYLD_REG30 0x000001f4
/* [0x1f8]: REG tx payload reg31 */
#define MASTERFIP_REG_TX_PAYLD_REG31 0x000001f8
/* [0x1fc]: REG tx payload reg32 */
#define MASTERFIP_REG_TX_PAYLD_REG32 0x000001fc
/* [0x200]: REG tx payload reg33 */
#define MASTERFIP_REG_TX_PAYLD_REG33 0x00000200
/* [0x204]: REG tx payload reg34 */
#define MASTERFIP_REG_TX_PAYLD_REG34 0x00000204
/* [0x208]: REG tx payload reg35 */
#define MASTERFIP_REG_TX_PAYLD_REG35 0x00000208
/* [0x20c]: REG tx payload reg36 */
#define MASTERFIP_REG_TX_PAYLD_REG36 0x0000020c
/* [0x210]: REG tx payload reg37 */
#define MASTERFIP_REG_TX_PAYLD_REG37 0x00000210
/* [0x214]: REG tx payload reg38 */
#define MASTERFIP_REG_TX_PAYLD_REG38 0x00000214
/* [0x218]: REG tx payload reg39 */
#define MASTERFIP_REG_TX_PAYLD_REG39 0x00000218
/* [0x21c]: REG tx payload reg40 */
#define MASTERFIP_REG_TX_PAYLD_REG40 0x0000021c
/* [0x220]: REG tx payload reg41 */
#define MASTERFIP_REG_TX_PAYLD_REG41 0x00000220
/* [0x224]: REG tx payload reg42 */
#define MASTERFIP_REG_TX_PAYLD_REG42 0x00000224
/* [0x228]: REG tx payload reg43 */
#define MASTERFIP_REG_TX_PAYLD_REG43 0x00000228
/* [0x22c]: REG tx payload reg44 */
#define MASTERFIP_REG_TX_PAYLD_REG44 0x0000022c
/* [0x230]: REG tx payload reg45 */
#define MASTERFIP_REG_TX_PAYLD_REG45 0x00000230
/* [0x234]: REG tx payload reg46 */
#define MASTERFIP_REG_TX_PAYLD_REG46 0x00000234
/* [0x238]: REG tx payload reg47 */
#define MASTERFIP_REG_TX_PAYLD_REG47 0x00000238
/* [0x23c]: REG tx payload reg48 */
#define MASTERFIP_REG_TX_PAYLD_REG48 0x0000023c
/* [0x240]: REG tx payload reg49 */
#define MASTERFIP_REG_TX_PAYLD_REG49 0x00000240
/* [0x244]: REG tx payload reg50 */
#define MASTERFIP_REG_TX_PAYLD_REG50 0x00000244
/* [0x248]: REG tx payload reg51 */
#define MASTERFIP_REG_TX_PAYLD_REG51 0x00000248
/* [0x24c]: REG tx payload reg52 */
#define MASTERFIP_REG_TX_PAYLD_REG52 0x0000024c
/* [0x250]: REG tx payload reg53 */
#define MASTERFIP_REG_TX_PAYLD_REG53 0x00000250
/* [0x254]: REG tx payload reg54 */
#define MASTERFIP_REG_TX_PAYLD_REG54 0x00000254
/* [0x258]: REG tx payload reg55 */
#define MASTERFIP_REG_TX_PAYLD_REG55 0x00000258
/* [0x25c]: REG tx payload reg56 */
#define MASTERFIP_REG_TX_PAYLD_REG56 0x0000025c
/* [0x260]: REG tx payload reg57 */
#define MASTERFIP_REG_TX_PAYLD_REG57 0x00000260
/* [0x264]: REG tx payload reg58 */
#define MASTERFIP_REG_TX_PAYLD_REG58 0x00000264
/* [0x268]: REG tx payload reg59 */
#define MASTERFIP_REG_TX_PAYLD_REG59 0x00000268
/* [0x26c]: REG tx payload reg60 */
#define MASTERFIP_REG_TX_PAYLD_REG60 0x0000026c
/* [0x270]: REG tx payload reg61 */
#define MASTERFIP_REG_TX_PAYLD_REG61 0x00000270
/* [0x274]: REG tx payload reg62 */
#define MASTERFIP_REG_TX_PAYLD_REG62 0x00000274
/* [0x278]: REG tx payload reg63 */
#define MASTERFIP_REG_TX_PAYLD_REG63 0x00000278
/* [0x27c]: REG tx payload reg64 */
#define MASTERFIP_REG_TX_PAYLD_REG64 0x0000027c
/* [0x280]: REG tx payload reg65 */
#define MASTERFIP_REG_TX_PAYLD_REG65 0x00000280
/* [0x284]: REG tx payload reg66 */
#define MASTERFIP_REG_TX_PAYLD_REG66 0x00000284
/* [0x288]: REG tx payload reg67 */
#define MASTERFIP_REG_TX_PAYLD_REG67 0x00000288
#endif
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -30,19 +30,19 @@ wait %d900
-------------------------------------------------------------------------------
--------------- RESETS ---------------
-- reset inactive
wr 0000000000010000 F CAFE0000
wr 0000000000010004 F CAFE0000
wait %d20
-- core and FD reset active
wr 000000000010000 F CAFE0003
wr 0000000000010004 F CAFE0003
wait %d40
-- FD reset active
wr 0000000000010000 F CAFE0002
wr 0000000000010004 F CAFE0002
wait %d40
-- reset inactive
wr 0000000000010000 F CAFE0000
wr 0000000000010004 F CAFE0000
wait %d20
......@@ -64,105 +64,105 @@ wait %d20
--------------- ID_DAT ---------------
-- tx_rst
wr 0000000000010040 F 00000001
wr 0000000000010044 F 00000001
wait %d10
wr 0000000000010040 F 00000000
wr 0000000000010044 F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000010178 F 00000003
wr 000000000001017C F 00000003
wait %d20
-- data bytes varid = 0503 for agent to consume
wr 000000000001017C F 00000305
wr 0000000000010180 F 00000305
wait %d20
-- tx_start
wr 0000000000010040 F 00000202
wr 0000000000010044 F 00000202
wait %d20000
--------------- RP_DAT ---------------
-- tx_rst
wr 0000000000010040 F 00000001
wr 0000000000010044 F 00000001
wait %d10
wr 0000000000010040 F 00000000
wr 0000000000010044 F 00000000
wait %d20
-- control byte of rp_dat
wr 0000000000010178 F 00000002
wr 000000000001017C F 00000002
wait %d20
-- data bytes
wr 000000000001017C F BBAA0340
wr 0000000000010180 F BBAA0340
wait %d20
wr 0000000000010180 F EEDDCC05
wr 0000000000010184 F EEDDCC05
wait %d20
-- tx_start
wr 0000000000010040 F 00000502
wr 0000000000010044 F 00000502
wait %d20000
wr 0000000000010040 F 00000000
wr 0000000000010044 F 00000000
wait %d20000
--------------- ID_DAT ---------------
-- tx_rst
wr 0000000000010040 F 00000001
wr 0000000000010044 F 00000001
wait %d10
wr 0000000000010040 F 00000000
wr 0000000000010044 F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000010178 F 00000003
wr 000000000001017C F 00000003
wait %d20
-- data bytes varid = 1403 for agent to send identification
wr 000000000001017C F 00000310 -------------------------0314
wr 0000000000010180 F 00000310 -------------------------0314
wait %d20
-- tx_start
wr 0000000000010040 F 00000202
wr 0000000000010044 F 00000202
wait %d200
-- deactivate tx_start
wr 0000000000010040 F 00000000
wr 0000000000010044 F 00000000
-- release rx_rst
wr 0000000000010040 F 00000000
wr 0000000000010044 F 00000000
wait %d40000
-- read received data
rd 0000000000010070 F 00000002
rd 0000000000010074 F 00000002
wait %d20
rd 0000000000010040 F 03800550
rd 0000000000010044 F 03800550
wait %d40000
--------------- ID_DAT ---------------
tx_rst
wr 0000000000010040 F 00000001
wr 0000000000010044 F 00000001
wait %d10
wr 0000000000010040 F 00000000
wr 0000000000010044 F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000010178 F 00000003
wr 000000000001017C F 00000003
wait %d20
-- data bytes varid = 0603 for agent to produce
wr 000000000001017C F 00000306
wr 0000000000010180 F 00000306
wait %d20
-- tx_start
wr 0000000000010040 F 00000202
wr 0000000000010044 F 00000202
wait %d20
-- deactivate tx_start
wr 0000000000010040 F 00000000
wr 0000000000010044 F 00000000
-- release rx_rst
wr 0000000000010040 F 00000000
wr 0000000000010044 F 00000000
wait %d40000
-- read received data
......@@ -244,13 +244,13 @@ wait %d40000
--------------- RP_FIN ---------------
-- control byte of rp_fin
wr 0000000000010178 F 00000040
wr 000000000001017C F 00000040
wait %d20
-- rx_rst
wr 0000000000010040 F 00000001
wr 0000000000010044 F 00000001
wait %d20
-- tx_start
wr 0000000000010040 F 00000002
wr 0000000000010044 F 00000002
wait %d20000
\ No newline at end of file
......@@ -65,7 +65,7 @@ architecture behavioral of tb_masterFIP is
generic(
--g_span : integer :=32;
--g_width : integer :=32;
g_simulation : boolean :=TRUE
g_simul : boolean :=TRUE
);
port(
-- interface with GNUM circuit
......@@ -427,7 +427,7 @@ begin
generic map(
--g_span => 32,
--g_width => 32,
g_simulation => TRUE
g_simul => TRUE
)
port map(
-- interface with GNUM circuit
......
Release 14.7 par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PCBE13457:: Sun Jul 16 16:03:27 2017
PCBE13457:: Mon Jul 17 17:24:32 2017
par -w -intstyle ise -ol high -xe n -mt off spec_masterfip_mt_map.ncd
spec_masterfip_mt.ncd spec_masterfip_mt.pcf
......@@ -22,36 +22,36 @@ Device speed data version: "PRODUCTION 1.23 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 12,671 out of 54,576 23%
Number used as Flip Flops: 12,669
Number of Slice Registers: 12,613 out of 54,576 23%
Number used as Flip Flops: 12,611
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 2
Number of Slice LUTs: 14,799 out of 27,288 54%
Number used as logic: 11,505 out of 27,288 42%
Number using O6 output only: 8,528
Number using O5 output only: 392
Number using O5 and O6: 2,585
Number of Slice LUTs: 14,543 out of 27,288 53%
Number used as logic: 11,408 out of 27,288 41%
Number using O6 output only: 8,452
Number using O5 output only: 403
Number using O5 and O6: 2,553
Number used as ROM: 0
Number used as Memory: 2,828 out of 6,408 44%
Number used as Dual Port RAM: 2,828
Number using O6 output only: 2,796
Number used as Memory: 2,680 out of 6,408 41%
Number used as Dual Port RAM: 2,680
Number using O6 output only: 2,560
Number using O5 output only: 0
Number using O5 and O6: 32
Number using O5 and O6: 120
Number used as Single Port RAM: 0
Number used as Shift Register: 0
Number used exclusively as route-thrus: 466
Number with same-slice register load: 437
Number with same-slice carry load: 29
Number used exclusively as route-thrus: 455
Number with same-slice register load: 425
Number with same-slice carry load: 30
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 5,128 out of 6,822 75%
Number of MUXCYs used: 1,452 out of 13,644 10%
Number of LUT Flip Flop pairs used: 18,215
Number with an unused Flip Flop: 7,445 out of 18,215 40%
Number with an unused LUT: 3,416 out of 18,215 18%
Number of fully used LUT-FF pairs: 7,354 out of 18,215 40%
Number of occupied Slices: 5,220 out of 6,822 76%
Number of MUXCYs used: 1,464 out of 13,644 10%
Number of LUT Flip Flop pairs used: 18,162
Number with an unused Flip Flop: 7,391 out of 18,162 40%
Number with an unused LUT: 3,619 out of 18,162 19%
Number of fully used LUT-FF pairs: 7,152 out of 18,162 39%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
......@@ -67,8 +67,8 @@ IO Utilization:
IOB Flip Flops: 10
Specific Feature Utilization:
Number of RAMB16BWERs: 88 out of 116 75%
Number of RAMB8BWERs: 22 out of 232 9%
Number of RAMB16BWERs: 85 out of 116 73%
Number of RAMB8BWERs: 25 out of 232 10%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
......@@ -111,7 +111,7 @@ Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 18 secs
Finished initial Timing Analysis. REAL time: 18 secs
Finished initial Timing Analysis. REAL time: 19 secs
WARNING:Par:288 - The signal vc_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal vc_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
......@@ -122,156 +122,92 @@ WARNING:Par:288 - The signal fmc_prsnt_m2c_n_i_IBUF has no load. PAR will not a
WARNING:Par:288 - The signal l2p_rdy_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal l_wr_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal l_wr_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem19_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem21_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem15_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem17_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem12_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem22_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem16_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem11_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem13_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem9_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem10_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem31_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem32_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem29_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem7_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem3_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem18_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem14_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem16_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem15_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem5_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem22_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem28_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem27_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem8_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem23_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem24_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem5_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem14_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem13_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem6_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem7_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem8_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem3_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem4_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem21_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem9_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem10_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem30_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem26_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem4_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem20_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem6_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem2_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem1_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem17_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem18_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem19_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem20_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem11_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem12_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem25_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMB_DPO
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMC_DPO
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMB_DPO
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMC_DPO
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem43_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem44_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram4_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram5_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram5_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram4_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram2_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram3_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram2_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[1].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram3_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram2_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram3_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram4_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram1_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram3_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_1
/Mram_ram5_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram2_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram4_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
cmp_mock_turtle/gen_wr_node_without_white_rabbit.U_WR_Node/gen_cpus[0].U_CPU_Block/U_TheCoreCPU/gen_without_double_core_clock.U_CPU/reg_0
/Mram_ram5_RAMD_D1_O has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 104653 unrouted; REAL time: 20 secs
Phase 1 : 103063 unrouted; REAL time: 20 secs
Phase 2 : 95364 unrouted; REAL time: 23 secs
Phase 2 : 93875 unrouted; REAL time: 24 secs
Phase 3 : 45823 unrouted; REAL time: 59 secs
Phase 3 : 45591 unrouted; REAL time: 1 mins 3 secs
Phase 4 : 46888 unrouted; (Setup:0, Hold:8079, Component Switching Limit:0) REAL time: 1 mins 13 secs
Phase 4 : 46846 unrouted; (Setup:0, Hold:481, Component Switching Limit:0) REAL time: 1 mins 21 secs
Updating file: spec_masterfip_mt.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:7921, Component Switching Limit:0) REAL time: 6 mins 22 secs
Phase 5 : 0 unrouted; (Setup:198, Hold:481, Component Switching Limit:0) REAL time: 7 mins 2 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:7921, Component Switching Limit:0) REAL time: 6 mins 22 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:481, Component Switching Limit:0) REAL time: 9 mins 53 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:7921, Component Switching Limit:0) REAL time: 6 mins 22 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:481, Component Switching Limit:0) REAL time: 9 mins 53 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:7921, Component Switching Limit:0) REAL time: 6 mins 22 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:481, Component Switching Limit:0) REAL time: 9 mins 53 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 mins 23 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 9 mins 55 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 6 mins 28 secs
Total REAL time to Router completion: 6 mins 28 secs
Total CPU time to Router completion: 6 mins 37 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 10 mins
Total REAL time to Router completion: 10 mins
Total CPU time to Router completion: 10 mins 6 secs
Partition Implementation Status
-------------------------------
......@@ -290,11 +226,11 @@ Generating Clock Report
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/clk_ | | | | | |
| sys | BUFGMUX_X2Y3| No | 4214 | 0.548 | 1.759 |
| sys | BUFGMUX_X2Y3| No | 4273 | 0.548 | 1.759 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/gen_ | | | | | |
|with_gennum.U_GN4124 | | | | | |
| _Core/sys_clk | BUFGMUX_X3Y13| No | 216 | 0.493 | 1.704 |
| _Core/sys_clk | BUFGMUX_X3Y13| No | 190 | 0.491 | 1.704 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/gen_ | | | | | |
|with_gennum.U_GN4124 | | | | | |
......@@ -320,13 +256,13 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_pllout_clk_sys_0 = PER | SETUP | 0.040ns| 9.960ns| 0| 0
TS_cmp_mock_turtle_pllout_clk_sys_0 = PER | SETUP | 0.028ns| 9.972ns| 0| 0
IOD TIMEGRP "cmp_mock_turtle_pllo | HOLD | 0.290ns| | 0| 0
ut_clk_sys_0" TS_clk_125m_pllref_n_i / 0. | | | | |
8 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_gen_with_gennum_U_GN41 | SETUP | 0.129ns| 4.871ns| 0| 0
24_Core_cmp_clk_in_rx_pllout_x1 = | HOLD | 0.153ns| | 0| 0
TS_cmp_mock_turtle_gen_with_gennum_U_GN41 | SETUP | 0.034ns| 4.966ns| 0| 0
24_Core_cmp_clk_in_rx_pllout_x1 = | HOLD | 0.136ns| | 0| 0
PERIOD TIMEGRP "cmp_mock_turtle_ | | | | |
gen_with_gennum_U_GN4124_Core_cmp_clk_in_ | | | | |
rx_pllout_x1" TS_cmp_mock_turtle_ | | | | |
......@@ -393,8 +329,8 @@ Derived Constraints for TS_clk_125m_pllref_n_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk_125m_pllref_n_i | 8.000ns| 3.334ns| 7.968ns| 0| 0| 0| 4840982|
| TS_cmp_mock_turtle_pllout_clk_| 10.000ns| 9.960ns| N/A| 0| 0| 4840982| 0|
|TS_clk_125m_pllref_n_i | 8.000ns| 3.334ns| 7.978ns| 0| 0| 0| 4844863|
| TS_cmp_mock_turtle_pllout_clk_| 10.000ns| 9.972ns| N/A| 0| 0| 4844863| 0|
| sys_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
......@@ -404,15 +340,15 @@ Derived Constraints for TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_U_Node_Template_U_GN4124_Cor| 5.000ns| 0.925ns| 4.871ns| 0| 0| 0| 4827|
|TS_U_Node_Template_U_GN4124_Cor| 5.000ns| 0.925ns| 4.966ns| 0| 0| 0| 3371|
|e_cmp_clk_in_P_clk | | | | | | | |
| TS_cmp_mock_turtle_gen_with_ge| 5.000ns| 2.800ns| 4.871ns| 0| 0| 0| 4827|
| TS_cmp_mock_turtle_gen_with_ge| 5.000ns| 2.800ns| 4.966ns| 0| 0| 0| 3371|
| nnum_U_GN4124_Core_cmp_clk_in_| | | | | | | |
| buf_P_clk | | | | | | | |
| TS_cmp_mock_turtle_gen_with_g| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| ennum_U_GN4124_Core_cmp_clk_i| | | | | | | |
| n_rx_pllout_xs_int | | | | | | | |
| TS_cmp_mock_turtle_gen_with_g| 5.000ns| 4.871ns| N/A| 0| 0| 4827| 0|
| TS_cmp_mock_turtle_gen_with_g| 5.000ns| 4.966ns| N/A| 0| 0| 3371| 0|
| ennum_U_GN4124_Core_cmp_clk_i| | | | | | | |
| n_rx_pllout_x1 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
......@@ -429,19 +365,19 @@ Generating Pad Report.
All signals are completely routed.
WARNING:Par:283 - There are 71 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
WARNING:Par:283 - There are 29 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 6 mins 35 secs
Total CPU time to PAR completion: 6 mins 43 secs
Total REAL time to PAR completion: 10 mins 7 secs
Total CPU time to PAR completion: 10 mins 12 secs
Peak Memory Usage: 871 MB
Peak Memory Usage: 907 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 73
Number of warning messages: 31
Number of info messages: 1
Writing design to file spec_masterfip_mt.ncd
......
This source diff could not be displayed because it is too large. You can view the blob instead.
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -20,8 +20,9 @@
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type=""/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type=""/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_functions.v" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>
<properties>
......@@ -383,50 +384,14 @@
</libraries>
<files>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_wishbone_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="93"/>
<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/nanofip/src/wf_rx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="149"/>
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_iram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="107"/>
<association xil_pn:name="Implementation" xil_pn:seqID="107"/>
......@@ -439,26 +404,10 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="92"/>
<association xil_pn:name="Implementation" xil_pn:seqID="92"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/nanofip/src/wf_tx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="148"/>
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_irq_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_eb_cycle_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
......@@ -471,10 +420,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="132"/>
<association xil_pn:name="Implementation" xil_pn:seqID="130"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_csr_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
......@@ -489,11 +434,7 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="90"/>
......@@ -503,38 +444,14 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="89"/>
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/>
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="188"/>
<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="134"/>
<association xil_pn:name="Implementation" xil_pn:seqID="132"/>
......@@ -543,10 +460,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="179"/>
<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/wr_node_core_with_etherbone.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="182"/>
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
......@@ -555,33 +468,9 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="115"/>
<association xil_pn:name="Implementation" xil_pn:seqID="113"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/top/spec/node_template/spec_reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="180"/>
......@@ -591,10 +480,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="150"/>
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/nanofip/src/wf_incr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="123"/>
<association xil_pn:name="Implementation" xil_pn:seqID="121"/>
......@@ -623,22 +508,10 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/>
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -659,38 +532,18 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="135"/>
<association xil_pn:name="Implementation" xil_pn:seqID="133"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="133"/>
<association xil_pn:name="Implementation" xil_pn:seqID="131"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
......@@ -707,98 +560,38 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="114"/>
<association xil_pn:name="Implementation" xil_pn:seqID="112"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_private_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/top/spec/node_template/spec_node_template.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="207"/>
<association xil_pn:name="Implementation" xil_pn:seqID="171"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="104"/>
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="91"/>
<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
</file>
<file xil_pn:name="../../rtl/masterFIP_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="142"/>
<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../rtl/incr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="143"/>
<association xil_pn:name="Implementation" xil_pn:seqID="136"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
......@@ -807,29 +600,13 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="178"/>
<association xil_pn:name="Implementation" xil_pn:seqID="157"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="136"/>
<association xil_pn:name="Implementation" xil_pn:seqID="134"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="187"/>
......@@ -839,14 +616,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="206"/>
<association xil_pn:name="Implementation" xil_pn:seqID="170"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="67"/>
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
......@@ -867,14 +636,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="144"/>
<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/wr_node_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
......@@ -887,22 +648,14 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="181"/>
<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_lm32_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="96"/>
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="55"/>
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
......@@ -911,10 +664,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/nanofip/src/wf_decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="124"/>
<association xil_pn:name="Implementation" xil_pn:seqID="122"/>
......@@ -927,18 +676,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../ip_cores/nanofip/src/wf_crc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="125"/>
<association xil_pn:name="Implementation" xil_pn:seqID="123"/>
......@@ -947,41 +684,21 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="177"/>
<association xil_pn:name="Implementation" xil_pn:seqID="156"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="57"/>
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="54"/>
......@@ -994,10 +711,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="208"/>
<association xil_pn:name="Implementation" xil_pn:seqID="172"/>
</file>
<file xil_pn:name="../../top/spec/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_ds182x_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="190"/>
<association xil_pn:name="Implementation" xil_pn:seqID="169"/>
......@@ -1297,10 +1010,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="153"/>
<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
......@@ -1319,7 +1028,7 @@
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="71"/>
......@@ -1345,14 +1054,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="183"/>
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwb_fabric_sink.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwb_fabric_source.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/xwrf_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="122"/>
<association xil_pn:name="Implementation" xil_pn:seqID="120"/>
......@@ -1365,22 +1066,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/timing/hpll_period_detect.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/timing/multi_dmtd_with_deglitcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/timing/pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/timing/pulse_stamper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="145"/>
<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
......@@ -1389,14 +1074,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="184"/>
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tlu/tlu.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tlu/tlu_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tlu/tlu_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -1407,53 +1084,13 @@
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="492"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="492"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_channel.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_offset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_sdp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_search.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_walker.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_wb_event.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/eca_wr_time.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_eca/wr_eca.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
......@@ -1469,11 +1106,7 @@
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_flow_control.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_leds_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
......@@ -1489,11 +1122,7 @@
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rmon_counters.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
......@@ -1505,7 +1134,7 @@
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_bypass_queue.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
......@@ -1545,11 +1174,11 @@
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
......@@ -1583,10 +1212,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="120"/>
<association xil_pn:name="Implementation" xil_pn:seqID="118"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_packet_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
<association xil_pn:name="Implementation" xil_pn:seqID="79"/>
......@@ -1615,30 +1240,14 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="118"/>
<association xil_pn:name="Implementation" xil_pn:seqID="116"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/si570_if_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/wr_si57x_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_si57x_interface/xwr_si57x_interface.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_bangbang_pd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_period_detect.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
<association xil_pn:name="Implementation" xil_pn:seqID="75"/>
......@@ -1655,34 +1264,14 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="117"/>
<association xil_pn:name="Implementation" xil_pn:seqID="115"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/dec_8b10b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/enc_8b10b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_tbi_phy/wr_tbi_phy.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wb_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="146"/>
<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_periph.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="121"/>
<association xil_pn:name="Implementation" xil_pn:seqID="119"/>
......@@ -1703,57 +1292,127 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="189"/>
<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.ngc" xil_pn:type="FILE_NGC">
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="419"/>
<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="420"/>
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="421"/>
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="422"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dcache.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="424"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_debug.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="425"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_decoder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="426"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_64x512.ngc" xil_pn:type="FILE_NGC">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="427"/>
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="428"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_64x512.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_icache.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="430"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_64x512.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_interrupt.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="432"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc" xil_pn:type="FILE_NGC">
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_jtag.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="433"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="126"/>
<association xil_pn:name="Implementation" xil_pn:seqID="124"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_load_store_unit.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="434"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="435"/>
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="436"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="437"/>
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="438"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="439"/>
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="441"/>
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="442"/>
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="444"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.xise" xil_pn:type="FILE_COREGENISE">
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_64x512.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_64x512.xise" xil_pn:type="FILE_COREGENISE">
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_64x512.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="446"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="448"/>
<association xil_pn:name="Implementation" xil_pn:seqID="124"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="449"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="450"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
</files>
<bindings>
......
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -155,7 +155,7 @@ use work.masterfip_wbgen2_pkg.all; -- for the masterfip_wbgen2_csr records
entity spec_masterfip_mt is
generic (g_simulation : boolean := false);
generic (g_simul : boolean := false);
port
(-- Carrier signals
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -370,7 +370,7 @@ begin
---------------------------------------------------------------------------------------------------
cmp_mock_turtle : spec_node_template
generic map
(g_simulation => g_simulation,
(g_simulation => g_simul,
g_with_wr_phy => false, -- no White Rabbit support, dah
g_with_white_rabbit => false,
g_double_wrnode_core_clock => false,
......@@ -462,7 +462,7 @@ begin
generic map
(g_span => 32,
g_width => 32,
values_for_simul => g_simulation)
g_simul => g_simul)
port map
(clk_i => clk_100m_sys,
rst_n_i => rst_n_sys,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment