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MasterFIP - Gateware
Commit a6c43633 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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added fd_cdn register; added wbgen2_pkg; restructuring

parent bf741228
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rtl/fmc_masterFIP_core.vhd
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rtl/fmc_masterfip_csr.vhd
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rtl/masterFIP_pkg.vhd
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rtl/masterfip_rx.vhd
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......@@ -302,21 +302,34 @@ begin
rx_frame_o <= (others =>(others =>'0'));
else
-- upon rx_fss_crc_fes_ok_p, the last 32bit word will contain for sure CRC0 and CRC1
-- and it may also contain one or two bytes of data.
-- the last word will always include as last bytes, byte1 and byte0: the two CRC bytes.
-- it could also include one or two useful data bytes
if rx_fss_crc_fes_ok_p = '1' then
-- upon rx_fss_crc_fes_ok_p, the last 32bit word will contain for sure CRC0, CRC1 and FES
-- and it may also contain up to one byte of data.
if (rx_byte_index-3) mod 4 = 1 then
if word32_num = 0 then -- only in the case of RP_FIN, where there are not enough bytes to create a word; needed for keeping the MT sw generic
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3; -- byte3 is the data byte; the other ones can be "0"
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3; --
elsif (rx_byte_index-2) mod 4 = 3 then -- [CRC|CRC|BYTE|BYTE]
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3; -- byte 3 and byte 2 are useful
elsif (rx_byte_index-2) mod 4 = 2 then -- [0|CRC|CRC|BYTE]
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= "00000000" & byte0 & byte1 & byte2;-- one useful data byte: byte2 last byte
-- for [CRC|BYTE|BYTE|BYTE] upon rx_fss_crc_fes_ok_p a new word has been created
end if;
elsif (rx_byte_ready_p = '1' and (rx_byte_index_d1) > 0 and (rx_byte_index_d1) mod 4 = 0) then -- for all the other bytes
elsif (rx_byte_ready_p = '1' and (rx_byte_index_d1) > 0 and (rx_byte_index_d1) mod 4 = 0) then
word32_num <= word32_num + 1;
rx_frame_o(word32_num) <= byte0 & byte1 & byte2 & byte3;
end if;
end if;
end if;
end process;
rx_word_index_o <= std_logic_vector(to_unsigned(word32_num,7));
......
rtl/mf_wbgen2_pkg.vhd 0 → 100644
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rtl/wbgen/fmc_masterfip_csr.h
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rtl/wbgen/fmc_masterfip_csr.htm
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rtl/wbgen/fmc_masterfip_csr.wb
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sim/spec/data_vectors/board_settings_config.txt
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......@@ -7,8 +7,8 @@ sd1 -- m_id_2 can take the values (gnd, vcc, sd0, sd1)
sd0 -- m_id_1 can take the values (gnd, vcc, sd0, sd1)
vcc -- m_id_0 can take the values (gnd, vcc, sd0, sd1)
1 -- nostat: nanoFIP status enabled(0), nanoFIP status disabled(1)
001 -- produced variable length: 2 bytes(000), 8 bytes(001), 16 bytes(010), 32 bytes(011), 64 bytes(100), 124 bytes(101)
000 -- produced variable length: 2 bytes(000), 8 bytes(001), 16 bytes(010), 32 bytes(011), 64 bytes(100), 124 bytes(101)
01 -- rate: 31.25 kbits(00), 1 Mbit(01), 2.5 Mbits(10)
0 -- mode (slone): memory mode(0), stand alone(1)
03 -- station_adr (8-bit bus in hexadecimal format)
20000 ms -- time for which the configuration above is valid
20000 ms -- time for which the configuration above is validboard
\ No newline at end of file
sim/spec/data_vectors/masterFIP_test.vec
View file @ a6c43633
......@@ -60,110 +60,109 @@ wait %d20
--------------- ID_DAT ---------------
-- tx_rst
wr 000000000003003C F 00000001
wr 0000000000030048 F 00000001
wait %d10
wr 000000000003003C F 00000000
wr 0000000000030048 F 00000000
wait %d20
-- control byte of id_dat
wr 000000000003016C F 00000003
wr 0000000000030180 F 00000003
wait %d20
-- data bytes varid = 0503 for agent to consume
wr 0000000000030170 F 00000305
wr 0000000000030184 F 00000305
wait %d20
-- tx_start
wr 000000000003003C F 00000202
wr 0000000000030048 F 00000202
wait %d20000
--------------- RP_DAT ---------------
-- tx_rst
wr 000000000003003C F 00000001
wr 0000000000030048 F 00000001
wait %d10
wr 000000000003003C F 00000000
wr 0000000000030048 F 00000000
wait %d20
-- control byte of rp_dat
wr 000000000003016C F 00000002
wr 0000000000030180 F 00000002
wait %d20
-- data bytes
wr 0000000000030170 F BBAA0940 -- for 2 data bytes: BBAA0340 | for 8 data bytes: BBAA0940
wr 0000000000030184 F BBAA0340
wait %d20
wr 0000000000030174 F FFEEDDCC -- for 2 data bytes: EEDDCC05 | for 8 data bytes: FFEEDDCC
wait %d20
wr 0000000000030178 F 00052B1A -- for 2 data bytes: 00000000 | for 8 data bytes: 00052B1A
wr 0000000000030188 F EEDDCC05
wait %d20
-- tx_start
wr 000000000003003C F 00000B02 -- for 2 data bytes: 00000502 | for 8 data bytes: 00000B02
wr 0000000000030048 F 00000502
wait %d20000
wr 000000000003003C F 00000000
wr 0000000000030048 F 00000000
wait %d20000
--------------- ID_DAT ---------------
-- tx_rst
wr 000000000003003C F 00000001
wr 0000000000030048 F 00000001
wait %d10
wr 000000000003003C F 00000000
wr 0000000000030048 F 00000000
wait %d20
-- control byte of id_dat
wr 000000000003016C F 00000003
wr 0000000000030180 F 00000003
wait %d20
-- data bytes varid = 1403 for agent to send identification
wr 0000000000030170 F 00000314 -------------------------0314
wr 0000000000030184 F 00000310 -------------------------0314
wait %d20
-- tx_start
wr 000000000003003C F 00000202
wr 0000000000030048 F 00000202
wait %d200
-- deactivate tx_start
wr 000000000003003C F 00000000
wr 0000000000030048 F 00000000
-- release rx_rst
wr 0000000000030048 F 00000000
wait %d40000
-- read received data
rd 0000000000030054 F 00000002
rd 0000000000030070 F 00000002
wait %d20
rd 0000000000030048 F 03800550
wait %d40000
--------------- ID_DAT ---------------
tx_rst
wr 000000000003003C F 00000001
wr 0000000000030048 F 00000001
wait %d10
wr 000000000003003C F 00000000
wr 0000000000030048 F 00000000
wait %d20
-- control byte of id_dat
wr 000000000003016C F 00000003
wr 0000000000030180 F 00000003
wait %d20
-- data bytes varid = 0603 for agent to produce
wr 0000000000030170 F 00000306
wr 0000000000030184 F 00000306
wait %d20
-- tx_start
wr 000000000003003C F 00000202
wr 0000000000030048 F 00000202
wait %d20
-- deactivate tx_start
wr 000000000003003C F 00000000
wr 0000000000030048 F 00000000
-- release rx_rst
wr 0000000000030048 F 00000000
wait %d40000
-- read received data
rd 0000000000030054 F 00000000 FFFFFFFF -- XXXXXX02 FFFFFFFF
rd 0000000000030070 F 00000000 FFFFFFFF -- XXXXXX02 FFFFFFFF
wait %d20
rd 0000000000030058 F 00000000 FFFFFFFF -- BC870940 FFFFFFFF
wait %d20
......@@ -241,7 +240,7 @@ wait %d40000
--------------- RP_FIN ---------------
-- control byte of rp_fin
wr 000000000003016C F 00000040
wr 0000000000030180 F 00000040
wait %d20
-- rx_rst
......@@ -249,5 +248,5 @@ wr 0000000000030048 F 00000001
wait %d20
-- tx_start
wr 000000000003003C F 00000002
wr 0000000000030048 F 00000002
wait %d20000
\ No newline at end of file
sim/spec/testbench/tb_masterFIP.vhd
View file @ a6c43633
......@@ -424,7 +424,7 @@ signal spare : std_logic;
signal adr : std_logic_vector(9 downto 0);
signal cyc : std_logic;
signal dat_to_fip : std_logic_vector(15 downto 0);
signal dat_to_fip, dat_to_fip_tmp : std_logic_vector(15 downto 0);
signal rst : std_logic := '0';
signal stb : std_logic;
......@@ -506,8 +506,8 @@ begin
port map(
uclk_i => nanoFIP_clk,
c_id_i => c_id,
m_id_i => m_id,
c_id_i => "1011",
m_id_i => "0101",
p3_lgth_i => p3_lgth,
rate_i => rate,
subs_i => subs,
......@@ -557,6 +557,7 @@ begin
jc_tdi_o => open,
jc_tck_o => open);
dat_to_fip <= dat_to_fip_tmp when slone = '0' else dat_from_fip;
user_logic: user_interface
port map(
......@@ -579,7 +580,7 @@ begin
adr_o => adr,
cyc_o => cyc,
dat_o => dat_to_fip,
dat_o => dat_to_fip_tmp,
rst_o => rst,
stb_o => stb,
wclk_o => wclk,
......
sim/spec/testbench/user_interface.vhd
View file @ a6c43633
......@@ -40,31 +40,6 @@ end user_interface;
architecture archi of user_interface is
component slone_interface
port(
launch_slone_read : in std_logic;
launch_slone_write : in std_logic;
uclk : in std_logic;
ureset : in std_logic;
dat_o : out std_logic_vector(15 downto 0);
slone_access_read : out std_logic;
slone_access_write : out std_logic
);
end component;
component slone_monitor
port(
dat_i : in std_logic_vector(15 downto 0);
dat_o : in std_logic_vector(15 downto 0);
slone_access_read : in std_logic;
slone_access_write : in std_logic;
uclk : in std_logic;
ureset : in std_logic;
var_id : in std_logic_vector(1 downto 0)
);
end component;
component user_sequencer
port(
uclk_period : in time;
......@@ -78,8 +53,7 @@ architecture archi of user_interface is
p3_lgth_i : in std_logic_vector(2 downto 0);
block_size : out std_logic_vector(6 downto 0);
launch_slone_read : out std_logic;
launch_slone_write : out std_logic;
launch_wb_read : out std_logic;
launch_wb_write : out std_logic;
transfer_length : out std_logic_vector(6 downto 0);
......@@ -87,24 +61,7 @@ architecture archi of user_interface is
var_id : out std_logic_vector(1 downto 0)
);
end component;
component user_access_monitor is
port(
cyc : in std_logic;
uclk_period : in time;
urstn_from_nf : in std_logic;
slone_access_read : in std_logic;
slone_access_write : in std_logic;
var1_rdy_i : in std_logic;
var2_rdy_i : in std_logic;
var3_rdy_i : in std_logic;
var_id : in std_logic_vector(1 downto 0);
var1_acc_o : out std_logic;
var2_acc_o : out std_logic;
var3_acc_o : out std_logic
);
end component;
component wishbone_interface
port(
......@@ -244,15 +201,6 @@ begin
wait for config_validity_time - preset_length;
end process;
slone_output_detector: process
begin
if launch_slone_write ='1' then
slone_output <= TRUE;
elsif memory_output then
slone_output <= FALSE;
end if;
wait until uclk ='1';
end process;
memory_output_detector: process
begin
......@@ -264,30 +212,6 @@ begin
wait until wclk ='1';
end process;
sa_interface: slone_interface
port map(
launch_slone_read => launch_slone_read,
launch_slone_write => launch_slone_write,
uclk => uclk,
ureset => ureset,
dat_o => data_from_slone,
slone_access_read => slone_access_read,
slone_access_write => slone_access_write
);
sa_monitor: slone_monitor
port map(
dat_i => dat_i,
dat_o => data_from_slone,
slone_access_read => slone_access_read,
slone_access_write => slone_access_write,
uclk => uclk,
ureset => ureset,
var_id => var_id
);
user_sequence: user_sequencer
port map(
uclk_period => uclk_period,
......@@ -300,8 +224,7 @@ begin
p3_lgth_i => p3_lgth_i,
block_size => block_size,
launch_slone_read => launch_slone_read,
launch_slone_write => launch_slone_write,
launch_wb_read => launch_wb_read,
launch_wb_write => launch_wb_write,
transfer_length => transfer_length,
......@@ -310,22 +233,6 @@ begin
);
user_acc_monitor: user_access_monitor
port map(
cyc => cyc,
uclk_period => uclk_period,
urstn_from_nf => urstn_from_nf,
slone_access_read => slone_access_read,
slone_access_write => slone_access_write,
var1_rdy_i => var1_rdy_i,
var2_rdy_i => var2_rdy_i,
var3_rdy_i => var3_rdy_i,
var_id => var_id,
var1_acc_o => var1_acc_o,
var2_acc_o => var2_acc_o,
var3_acc_o => var3_acc_o
);
wb_interface: wishbone_interface
port map(
......@@ -382,8 +289,13 @@ begin
stb_o <= stb;
we_o <= we;
dat_o <= data_from_slone when slone_output
else x"00" & data_from_wb when memory_output
dat_o <= x"00" & data_from_wb when memory_output
else (others=>'0');
var1_acc_o <= launch_wb_read;
var2_acc_o <= '0';
var3_acc_o <= launch_wb_write;
end archi;
sim/spec/testbench/user_sequencer.vhd
View file @ a6c43633
......@@ -32,8 +32,6 @@ entity user_sequencer is
p3_lgth_i : in std_logic_vector(2 downto 0);
block_size : out std_logic_vector(6 downto 0);
launch_slone_read : out std_logic;
launch_slone_write : out std_logic;
launch_wb_read : out std_logic;
launch_wb_write : out std_logic;
transfer_length : out std_logic_vector(6 downto 0);
......@@ -198,9 +196,6 @@ begin
end process;
launch_slone_read <= '0'; -- slone data are automatically copied from in to out
launch_slone_write <= '0'; -- slone data are automatically copied from in to out
launch_wb_read <= var1_rdy_p;-- or var2_rdy_i; --launch_wb_rd;
launch_wb_write <= transport var1_rdy_p after 10 us;
......@@ -222,15 +217,9 @@ begin
var_id <= "00"; -- not used
reporting: process(launch_slone_rd, launch_slone_wr, launch_wb_rd, launch_wb_wr)
reporting: process(launch_wb_rd, launch_wb_wr)
begin
if launch_slone_rd ='1' then
report LF & " User logic reads 2 bytes from the 16-bit stand-alone bus"& LF;
elsif launch_slone_wr ='1' then
report LF & " User logic writes 2 bytes on the 16-bit stand-alone bus"& LF;
elsif launch_wb_rd ='1' then
if launch_wb_rd ='1' then
if transfer_offst = 0 then
report LF & " User logic reads " & integer'image(transfer_lgth) &
" bytes of user data plus the length byte and the PDU type byte" &
......
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