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MasterFIP - Gateware
Commit b6f02ae3 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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cleanup

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Showing with 66 additions and 31 deletions
general-cores @ 49afba43
Subproject commit 9a40120ba4af4a7551f9fd8cbbe61f1d434f30bf
Subproject commit 49afba4313ecab5b99d32858b82fdff171a404dc
syn/spec/spec_masterfip_mt.xise
View file @ b6f02ae3
......@@ -399,7 +399,7 @@
</file>
<file xil_pn:name="../../ip_cores/nanofip/src/wf_rx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="147"/>
<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/cpu/wrn_cpu_iram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
......@@ -435,7 +435,7 @@
</file>
<file xil_pn:name="../../ip_cores/nanofip/src/wf_tx_serializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="145"/>
<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
</file>
<file xil_pn:name="../../rtl/wf_package.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="92"/>
......@@ -451,7 +451,7 @@
</file>
<file xil_pn:name="../../ip_cores/nanofip/src/wf_tx_osc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="146"/>
<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/mqueue/wrn_mqueue_irq_unit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
......@@ -471,7 +471,7 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="131"/>
<association xil_pn:name="Implementation" xil_pn:seqID="129"/>
<association xil_pn:name="Implementation" xil_pn:seqID="130"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
......@@ -539,7 +539,7 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="133"/>
<association xil_pn:name="Implementation" xil_pn:seqID="131"/>
<association xil_pn:name="Implementation" xil_pn:seqID="132"/>
</file>
<file xil_pn:name="../../rtl/decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="179"/>
......@@ -595,7 +595,7 @@
</file>
<file xil_pn:name="../../ip_cores/nanofip/src/wf_rx_deserializer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="148"/>
<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
......@@ -663,7 +663,7 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="134"/>
<association xil_pn:name="Implementation" xil_pn:seqID="132"/>
<association xil_pn:name="Implementation" xil_pn:seqID="133"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
......@@ -691,7 +691,7 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="132"/>
<association xil_pn:name="Implementation" xil_pn:seqID="130"/>
<association xil_pn:name="Implementation" xil_pn:seqID="131"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
......@@ -707,7 +707,7 @@
</file>
<file xil_pn:name="../../ip_cores/nanofip/src/wf_rx_deglitcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="149"/>
<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
......@@ -787,7 +787,7 @@
</file>
<file xil_pn:name="../../rtl/masterFIP_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="141"/>
<association xil_pn:name="Implementation" xil_pn:seqID="134"/>
<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
......@@ -831,7 +831,7 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="135"/>
<association xil_pn:name="Implementation" xil_pn:seqID="133"/>
<association xil_pn:name="Implementation" xil_pn:seqID="134"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
......@@ -879,7 +879,7 @@
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/rtl/wrnc/wr_node_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="142"/>
<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
<association xil_pn:name="Implementation" xil_pn:seqID="136"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
......@@ -1275,17 +1275,13 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<library xil_pn:name="nanoFIP"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="189"/>
<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="159"/>
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="130"/>
<association xil_pn:name="Implementation" xil_pn:seqID="128"/>
<association xil_pn:name="Implementation" xil_pn:seqID="129"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="158"/>
......@@ -1305,7 +1301,7 @@
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="150"/>
<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="186"/>
......@@ -1313,7 +1309,7 @@
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="129"/>
<association xil_pn:name="Implementation" xil_pn:seqID="127"/>
<association xil_pn:name="Implementation" xil_pn:seqID="128"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
......@@ -1325,23 +1321,23 @@
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="152"/>
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="151"/>
<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="128"/>
<association xil_pn:name="Implementation" xil_pn:seqID="126"/>
<association xil_pn:name="Implementation" xil_pn:seqID="127"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="127"/>
<association xil_pn:name="Implementation" xil_pn:seqID="125"/>
<association xil_pn:name="Implementation" xil_pn:seqID="126"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="126"/>
<association xil_pn:name="Implementation" xil_pn:seqID="124"/>
<association xil_pn:name="Implementation" xil_pn:seqID="125"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
......@@ -1409,7 +1405,7 @@
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="143"/>
<association xil_pn:name="Implementation" xil_pn:seqID="136"/>
<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_dacs/spec_serial_dac_arb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="184"/>
......@@ -1589,10 +1585,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
......@@ -1707,7 +1699,7 @@
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wr_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="144"/>
<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
</file>
<file xil_pn:name="../../ip_cores/wr-cores/modules/wrc_core/wrc_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
......@@ -1729,6 +1721,49 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="102"/>
<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dyn_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="343"/>
<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="346"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="347"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_64x512.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_64x512.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="356"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_64x512.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="357"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="365"/>
<association xil_pn:name="Implementation" xil_pn:seqID="124"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/l2p_fifo.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="366"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_64x512.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<bindings>
......
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