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MasterFIP - Gateware
Commit bc4cc976 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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added counter of ext_sync_p

parent aae395c5
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Showing with 443 additions and 393 deletions
rtl/fmc_masterFIP_core.vhd
View file @ bc4cc976
...@@ -123,7 +123,9 @@ architecture rtl of fmc_masterFIP_core is ...@@ -123,7 +123,9 @@ architecture rtl of fmc_masterFIP_core is
-- config -- config
signal speed : std_logic_vector(1 downto 0); signal speed : std_logic_vector(1 downto 0);
-- ext pulse -- ext pulse
signal ext_sync_p : std_logic; signal ext_sync_p, ext_sync_oe : std_logic;
signal ext_sync_p_cnt_rst, ext_sync_p_cnt_host_rst : std_logic;
signal ext_sync_p_cnt : std_logic_vector(31 downto 0);
-- counters -- counters
signal macrocyc_load_p, turnar_load_p, silen_load_p : std_logic; signal macrocyc_load_p, turnar_load_p, silen_load_p : std_logic;
signal macrocyc_lgth, turnar_lgth, silen_lgth : std_logic_vector(30 downto 0); signal macrocyc_lgth, turnar_lgth, silen_lgth : std_logic_vector(30 downto 0);
...@@ -146,6 +148,8 @@ architecture rtl of fmc_masterFIP_core is ...@@ -146,6 +148,8 @@ architecture rtl of fmc_masterFIP_core is
signal rx_frame : rx_frame_t; signal rx_frame : rx_frame_t;
signal rx_ctrl_byte, rx_byte : std_logic_vector(7 downto 0); signal rx_ctrl_byte, rx_byte : std_logic_vector(7 downto 0);
signal rx_byte_index, rx_bytes_num : std_logic_vector(8 downto 0); -- up to 263 bytes signal rx_byte_index, rx_bytes_num : std_logic_vector(8 downto 0); -- up to 263 bytes
-- LEDs
signal sync_led, out_of_sync_led : std_logic;
-- chipscope -- chipscope
-- component chipscope_ila -- component chipscope_ila
...@@ -177,207 +181,207 @@ begin ...@@ -177,207 +181,207 @@ begin
-- REGISTERS -- -- REGISTERS --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
cmp_masterfip_csr: fmc_masterfip_csr cmp_masterfip_csr: fmc_masterfip_csr
port map( port map
-- wishbone -- wishbone
rst_n_i => rst_n, (rst_n_i => rst_n,
clk_sys_i => clk_i, clk_sys_i => clk_i,
wb_adr_i => wb_adr_i(9 downto 2), wb_adr_i => wb_adr_i(9 downto 2),
wb_dat_i => wb_dat_i, wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o, wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i, wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i, wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i, wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i, wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o, wb_ack_o => wb_ack_o,
wb_stall_o => wb_stall_o, wb_stall_o => wb_stall_o,
-- resets -- resets
mf_rstn_core_o => core_rstn_tmp, -- reset has to be confirmed with lock word mf_rstn_lock_o mf_rstn_core_o => core_rstn_tmp, -- reset has to be confirmed with lock word mf_rstn_lock_o
mf_rstn_fd_o => fd_rstn_tmp, -- reset has to be confirmed with lock word mf_rstn_lock_o mf_rstn_fd_o => fd_rstn_tmp, -- reset has to be confirmed with lock word mf_rstn_lock_o
mf_rstn_lock_o => rstn_lock, mf_rstn_lock_o => rstn_lock,
mf_rstn_lock_wr_o => rstn_lock_wr, mf_rstn_lock_wr_o => rstn_lock_wr,
-- adc supplies -- adc supplies
mf_adc_1v8_shdn_n_o => adc_1v8_shdn_n_o, mf_adc_1v8_shdn_n_o => adc_1v8_shdn_n_o,
mf_adc_m5v_shdn_n_o => adc_m5v_shdn_n_o, mf_adc_m5v_shdn_n_o => adc_m5v_shdn_n_o,
mf_adc_5v_en_n_o => adc_5v_en_n_o, mf_adc_5v_en_n_o => adc_5v_en_n_o,
-- external sync pulse -- external sync pulse
mf_ext_sync_term_en_o => ext_sync_term_en_o, mf_ext_sync_term_en_o => ext_sync_term_en_o,
mf_ext_sync_dir_o => ext_sync_dir_o, mf_ext_sync_dir_o => ext_sync_dir_o,
mf_ext_sync_oe_o => ext_sync_oe_o, mf_ext_sync_oe_o => ext_sync_oe,
mf_ext_sync_tst_n_o => ext_sync_tst_n_o, mf_ext_sync_tst_n_o => ext_sync_tst_n_o,
mf_ext_sync_tstamp_i => "00000000000000000000000000000000", -- external sync tstamp mf_ext_sync_p_cnt_rst_o => ext_sync_p_cnt_host_rst,
-- bus termination mf_ext_sync_p_cnt_i => ext_sync_p_cnt,
mf_bus_term_en_n_o => bus_term_en_n_o, -- bus termination
-- bus speed mf_bus_term_en_n_o => bus_term_en_n_o,
mf_speed_i(1) => speed_b1_i, -- bus speed
mf_speed_i(0) => speed_b0_i, mf_speed_i(1) => speed_b1_i,
-- counters outputs mf_speed_i(0) => speed_b0_i,
mf_macrocyc_lgth_o => macrocyc_lgth, -- counters outputs
mf_turnar_lgth_o => turnar_lgth, mf_macrocyc_lgth_o => macrocyc_lgth,
mf_silen_lgth_o => silen_lgth, mf_turnar_lgth_o => turnar_lgth,
mf_macrocyc_start_o => macrocyc_host_load, -- optional counters loading through the host mf_silen_lgth_o => silen_lgth,
mf_turnar_start_o => turnar_host_load, mf_macrocyc_start_o => macrocyc_host_load, -- optional counters loading through the host
mf_silen_start_o => silen_host_load, mf_turnar_start_o => turnar_host_load,
-- counters inputs mf_silen_start_o => silen_host_load,
mf_macrocyc_time_cnt_i => macrocyc_cnt, -- counters inputs
mf_turnar_time_cnt_i => turnar_cnt, mf_macrocyc_time_cnt_i => macrocyc_cnt,
mf_silen_time_cnt_i => silen_cnt, mf_turnar_time_cnt_i => turnar_cnt,
-- tx control mf_silen_time_cnt_i => silen_cnt,
mf_tx_ctrl_rst_o => tx_host_rst, -- tx rst; then converted to 1-tick-long pulse -- tx control
mf_tx_ctrl_start_o => tx_start, -- tx start serializing a frame; then converted to 1-tick-long pulse mf_tx_ctrl_rst_o => tx_host_rst, -- tx rst; then converted to 1-tick-long pulse
mf_tx_ctrl_bytes_num_o => tx_bytes_num, -- number of bytes to serialize; sampled upon tx_start mf_tx_ctrl_start_o => tx_start, -- tx start serializing a frame; then converted to 1-tick-long pulse
-- tx status mf_tx_ctrl_bytes_num_o => tx_bytes_num, -- number of bytes to serialize; sampled upon tx_start
mf_tx_stat_stop_i => tx_completed, -- 16x25ns long pulse upon the end of delivery of a frame -- tx status
mf_tx_stat_byte_index_i => tx_byte_index, -- index of current byte being serialized mf_tx_stat_stop_i => tx_completed, -- 16x25ns long pulse upon the end of delivery of a frame
mf_tx_stat_ena_i => fd_txena, -- FIELDRIVE txena, signal generated by the tx_serializer mf_tx_stat_byte_index_i => tx_byte_index, -- index of current byte being serialized
mf_fd_wdgn_i => fd_wdgn_i, -- FIELDRIVE watchdog, signal comes from the FIELDRIVE mf_tx_stat_ena_i => fd_txena, -- FIELDRIVE txena, signal generated by the tx_serializer
mf_fd_txer_i => fd_txer_i, -- FIELDRIVE txerr, signal comes from the FIELDRIVE mf_fd_wdgn_i => fd_wdgn_i, -- FIELDRIVE watchdog, signal comes from the FIELDRIVE
-- rx control/status mf_fd_txer_i => fd_txer_i, -- FIELDRIVE txerr, signal comes from the FIELDRIVE
mf_rx_ctrl_rst_o => rx_host_rst, -- note: this is not a pulse -- rx control/status
-- rx status mf_rx_ctrl_rst_o => rx_host_rst, -- note: this is not a pulse
mf_rx_stat_pream_ok_i => rx_fss_received, -- rx status
mf_rx_stat_frame_ok_i => rx_frame_ok, mf_rx_stat_pream_ok_i => rx_fss_received,
mf_rx_stat_frame_err_i => rx_crc_wrong, mf_rx_stat_frame_ok_i => rx_frame_ok,
mf_rx_stat_frame_err_code_i => "000", mf_rx_stat_frame_err_i => rx_crc_wrong,
mf_rx_stat_bytes_num_i => rx_bytes_num, mf_rx_stat_frame_err_code_i => "000",
-- rx data mf_rx_stat_bytes_num_i => rx_bytes_num,
mf_rx_data_ctrl_i => rx_ctrl_byte, -- rx data
mf_rx_data_reg1_i => rx_frame(0), mf_rx_data_ctrl_i => rx_ctrl_byte,
mf_rx_data_reg2_i => rx_frame(1), mf_rx_data_reg1_i => rx_frame(0),
mf_rx_data_reg3_i => rx_frame(2), mf_rx_data_reg2_i => rx_frame(1),
mf_rx_data_reg4_i => rx_frame(3), mf_rx_data_reg3_i => rx_frame(2),
mf_rx_data_reg5_i => rx_frame(4), mf_rx_data_reg4_i => rx_frame(3),
mf_rx_data_reg6_i => rx_frame(5), mf_rx_data_reg5_i => rx_frame(4),
mf_rx_data_reg7_i => rx_frame(6), mf_rx_data_reg6_i => rx_frame(5),
mf_rx_data_reg8_i => rx_frame(7), mf_rx_data_reg7_i => rx_frame(6),
mf_rx_data_reg9_i => rx_frame(8), mf_rx_data_reg8_i => rx_frame(7),
mf_rx_data_reg10_i => rx_frame(9), mf_rx_data_reg9_i => rx_frame(8),
mf_rx_data_reg11_i => rx_frame(10), mf_rx_data_reg10_i => rx_frame(9),
mf_rx_data_reg12_i => rx_frame(11), mf_rx_data_reg11_i => rx_frame(10),
mf_rx_data_reg13_i => rx_frame(12), mf_rx_data_reg12_i => rx_frame(11),
mf_rx_data_reg14_i => rx_frame(13), mf_rx_data_reg13_i => rx_frame(12),
mf_rx_data_reg15_i => rx_frame(14), mf_rx_data_reg14_i => rx_frame(13),
mf_rx_data_reg16_i => rx_frame(15), mf_rx_data_reg15_i => rx_frame(14),
mf_rx_data_reg17_i => rx_frame(16), mf_rx_data_reg16_i => rx_frame(15),
mf_rx_data_reg18_i => rx_frame(17), mf_rx_data_reg17_i => rx_frame(16),
mf_rx_data_reg19_i => rx_frame(18), mf_rx_data_reg18_i => rx_frame(17),
mf_rx_data_reg20_i => rx_frame(19), mf_rx_data_reg19_i => rx_frame(18),
mf_rx_data_reg21_i => rx_frame(20), mf_rx_data_reg20_i => rx_frame(19),
mf_rx_data_reg22_i => rx_frame(21), mf_rx_data_reg21_i => rx_frame(20),
mf_rx_data_reg23_i => rx_frame(22), mf_rx_data_reg22_i => rx_frame(21),
mf_rx_data_reg24_i => rx_frame(23), mf_rx_data_reg23_i => rx_frame(22),
mf_rx_data_reg25_i => rx_frame(24), mf_rx_data_reg24_i => rx_frame(23),
mf_rx_data_reg26_i => rx_frame(25), mf_rx_data_reg25_i => rx_frame(24),
mf_rx_data_reg27_i => rx_frame(26), mf_rx_data_reg26_i => rx_frame(25),
mf_rx_data_reg28_i => rx_frame(27), mf_rx_data_reg27_i => rx_frame(26),
mf_rx_data_reg29_i => rx_frame(28), mf_rx_data_reg28_i => rx_frame(27),
mf_rx_data_reg30_i => rx_frame(29), mf_rx_data_reg29_i => rx_frame(28),
mf_rx_data_reg31_i => rx_frame(30), mf_rx_data_reg30_i => rx_frame(29),
mf_rx_data_reg32_i => rx_frame(31), mf_rx_data_reg31_i => rx_frame(30),
mf_rx_data_reg33_i => rx_frame(32), mf_rx_data_reg32_i => rx_frame(31),
mf_rx_data_reg34_i => rx_frame(33), mf_rx_data_reg33_i => rx_frame(32),
mf_rx_data_reg35_i => rx_frame(34), mf_rx_data_reg34_i => rx_frame(33),
mf_rx_data_reg36_i => rx_frame(35), mf_rx_data_reg35_i => rx_frame(34),
mf_rx_data_reg37_i => rx_frame(36), mf_rx_data_reg36_i => rx_frame(35),
mf_rx_data_reg38_i => rx_frame(37), mf_rx_data_reg37_i => rx_frame(36),
mf_rx_data_reg39_i => rx_frame(38), mf_rx_data_reg38_i => rx_frame(37),
mf_rx_data_reg40_i => rx_frame(39), mf_rx_data_reg39_i => rx_frame(38),
mf_rx_data_reg41_i => rx_frame(40), mf_rx_data_reg40_i => rx_frame(39),
mf_rx_data_reg42_i => rx_frame(41), mf_rx_data_reg41_i => rx_frame(40),
mf_rx_data_reg43_i => rx_frame(42), mf_rx_data_reg42_i => rx_frame(41),
mf_rx_data_reg44_i => rx_frame(43), mf_rx_data_reg43_i => rx_frame(42),
mf_rx_data_reg45_i => rx_frame(44), mf_rx_data_reg44_i => rx_frame(43),
mf_rx_data_reg46_i => rx_frame(45), mf_rx_data_reg45_i => rx_frame(44),
mf_rx_data_reg47_i => rx_frame(46), mf_rx_data_reg46_i => rx_frame(45),
mf_rx_data_reg48_i => rx_frame(47), mf_rx_data_reg47_i => rx_frame(46),
mf_rx_data_reg49_i => rx_frame(48), mf_rx_data_reg48_i => rx_frame(47),
mf_rx_data_reg50_i => rx_frame(49), mf_rx_data_reg49_i => rx_frame(48),
mf_rx_data_reg51_i => rx_frame(50), mf_rx_data_reg50_i => rx_frame(49),
mf_rx_data_reg52_i => rx_frame(51), mf_rx_data_reg51_i => rx_frame(50),
mf_rx_data_reg53_i => rx_frame(52), mf_rx_data_reg52_i => rx_frame(51),
mf_rx_data_reg54_i => rx_frame(53), mf_rx_data_reg53_i => rx_frame(52),
mf_rx_data_reg55_i => rx_frame(54), mf_rx_data_reg54_i => rx_frame(53),
mf_rx_data_reg56_i => rx_frame(55), mf_rx_data_reg55_i => rx_frame(54),
mf_rx_data_reg57_i => rx_frame(56), mf_rx_data_reg56_i => rx_frame(55),
mf_rx_data_reg58_i => rx_frame(57), mf_rx_data_reg57_i => rx_frame(56),
mf_rx_data_reg59_i => rx_frame(58), mf_rx_data_reg58_i => rx_frame(57),
mf_rx_data_reg60_i => rx_frame(59), mf_rx_data_reg59_i => rx_frame(58),
mf_rx_data_reg61_i => rx_frame(60), mf_rx_data_reg60_i => rx_frame(59),
mf_rx_data_reg62_i => rx_frame(61), mf_rx_data_reg61_i => rx_frame(60),
mf_rx_data_reg63_i => rx_frame(62), mf_rx_data_reg62_i => rx_frame(61),
mf_rx_data_reg64_i => rx_frame(63), mf_rx_data_reg63_i => rx_frame(62),
mf_rx_data_reg65_i => rx_frame(64), mf_rx_data_reg64_i => rx_frame(63),
mf_rx_data_reg66_i => rx_frame(65), mf_rx_data_reg65_i => rx_frame(64),
-- tx data mf_rx_data_reg66_i => rx_frame(65),
mf_tx_data_ctrl_o => tx_ctrl_byte, -- tx data
mf_tx_data_reg1_o => tx_frame(0), mf_tx_data_ctrl_o => tx_ctrl_byte,
mf_tx_data_reg2_o => tx_frame(1), mf_tx_data_reg1_o => tx_frame(0),
mf_tx_data_reg3_o => tx_frame(2), mf_tx_data_reg2_o => tx_frame(1),
mf_tx_data_reg4_o => tx_frame(3), mf_tx_data_reg3_o => tx_frame(2),
mf_tx_data_reg5_o => tx_frame(4), mf_tx_data_reg4_o => tx_frame(3),
mf_tx_data_reg6_o => tx_frame(5), mf_tx_data_reg5_o => tx_frame(4),
mf_tx_data_reg7_o => tx_frame(6), mf_tx_data_reg6_o => tx_frame(5),
mf_tx_data_reg8_o => tx_frame(7), mf_tx_data_reg7_o => tx_frame(6),
mf_tx_data_reg9_o => tx_frame(8), mf_tx_data_reg8_o => tx_frame(7),
mf_tx_data_reg10_o => tx_frame(9), mf_tx_data_reg9_o => tx_frame(8),
mf_tx_data_reg11_o => tx_frame(10), mf_tx_data_reg10_o => tx_frame(9),
mf_tx_data_reg12_o => tx_frame(11), mf_tx_data_reg11_o => tx_frame(10),
mf_tx_data_reg13_o => tx_frame(12), mf_tx_data_reg12_o => tx_frame(11),
mf_tx_data_reg14_o => tx_frame(13), mf_tx_data_reg13_o => tx_frame(12),
mf_tx_data_reg15_o => tx_frame(14), mf_tx_data_reg14_o => tx_frame(13),
mf_tx_data_reg16_o => tx_frame(15), mf_tx_data_reg15_o => tx_frame(14),
mf_tx_data_reg17_o => tx_frame(16), mf_tx_data_reg16_o => tx_frame(15),
mf_tx_data_reg18_o => tx_frame(17), mf_tx_data_reg17_o => tx_frame(16),
mf_tx_data_reg19_o => tx_frame(18), mf_tx_data_reg18_o => tx_frame(17),
mf_tx_data_reg20_o => tx_frame(19), mf_tx_data_reg19_o => tx_frame(18),
mf_tx_data_reg21_o => tx_frame(20), mf_tx_data_reg20_o => tx_frame(19),
mf_tx_data_reg22_o => tx_frame(21), mf_tx_data_reg21_o => tx_frame(20),
mf_tx_data_reg23_o => tx_frame(22), mf_tx_data_reg22_o => tx_frame(21),
mf_tx_data_reg24_o => tx_frame(23), mf_tx_data_reg23_o => tx_frame(22),
mf_tx_data_reg25_o => tx_frame(24), mf_tx_data_reg24_o => tx_frame(23),
mf_tx_data_reg26_o => tx_frame(25), mf_tx_data_reg25_o => tx_frame(24),
mf_tx_data_reg27_o => tx_frame(26), mf_tx_data_reg26_o => tx_frame(25),
mf_tx_data_reg28_o => tx_frame(27), mf_tx_data_reg27_o => tx_frame(26),
mf_tx_data_reg29_o => tx_frame(28), mf_tx_data_reg28_o => tx_frame(27),
mf_tx_data_reg30_o => tx_frame(29), mf_tx_data_reg29_o => tx_frame(28),
mf_tx_data_reg31_o => tx_frame(30), mf_tx_data_reg30_o => tx_frame(29),
mf_tx_data_reg32_o => tx_frame(31), mf_tx_data_reg31_o => tx_frame(30),
mf_tx_data_reg33_o => tx_frame(32), mf_tx_data_reg32_o => tx_frame(31),
mf_tx_data_reg34_o => tx_frame(33), mf_tx_data_reg33_o => tx_frame(32),
mf_tx_data_reg35_o => tx_frame(34), mf_tx_data_reg34_o => tx_frame(33),
mf_tx_data_reg36_o => tx_frame(35), mf_tx_data_reg35_o => tx_frame(34),
mf_tx_data_reg37_o => tx_frame(36), mf_tx_data_reg36_o => tx_frame(35),
mf_tx_data_reg38_o => tx_frame(37), mf_tx_data_reg37_o => tx_frame(36),
mf_tx_data_reg39_o => tx_frame(38), mf_tx_data_reg38_o => tx_frame(37),
mf_tx_data_reg40_o => tx_frame(39), mf_tx_data_reg39_o => tx_frame(38),
mf_tx_data_reg41_o => tx_frame(40), mf_tx_data_reg40_o => tx_frame(39),
mf_tx_data_reg42_o => tx_frame(41), mf_tx_data_reg41_o => tx_frame(40),
mf_tx_data_reg43_o => tx_frame(42), mf_tx_data_reg42_o => tx_frame(41),
mf_tx_data_reg44_o => tx_frame(43), mf_tx_data_reg43_o => tx_frame(42),
mf_tx_data_reg45_o => tx_frame(44), mf_tx_data_reg44_o => tx_frame(43),
mf_tx_data_reg46_o => tx_frame(45), mf_tx_data_reg45_o => tx_frame(44),
mf_tx_data_reg47_o => tx_frame(46), mf_tx_data_reg46_o => tx_frame(45),
mf_tx_data_reg48_o => tx_frame(47), mf_tx_data_reg47_o => tx_frame(46),
mf_tx_data_reg49_o => tx_frame(48), mf_tx_data_reg48_o => tx_frame(47),
mf_tx_data_reg50_o => tx_frame(49), mf_tx_data_reg49_o => tx_frame(48),
mf_tx_data_reg51_o => tx_frame(50), mf_tx_data_reg50_o => tx_frame(49),
mf_tx_data_reg52_o => tx_frame(51), mf_tx_data_reg51_o => tx_frame(50),
mf_tx_data_reg53_o => tx_frame(52), mf_tx_data_reg52_o => tx_frame(51),
mf_tx_data_reg54_o => tx_frame(53), mf_tx_data_reg53_o => tx_frame(52),
mf_tx_data_reg55_o => tx_frame(54), mf_tx_data_reg54_o => tx_frame(53),
mf_tx_data_reg56_o => tx_frame(55), mf_tx_data_reg55_o => tx_frame(54),
mf_tx_data_reg57_o => tx_frame(56), mf_tx_data_reg56_o => tx_frame(55),
mf_tx_data_reg58_o => tx_frame(57), mf_tx_data_reg57_o => tx_frame(56),
mf_tx_data_reg59_o => tx_frame(58), mf_tx_data_reg58_o => tx_frame(57),
mf_tx_data_reg60_o => tx_frame(59), mf_tx_data_reg59_o => tx_frame(58),
mf_tx_data_reg61_o => tx_frame(60), mf_tx_data_reg60_o => tx_frame(59),
mf_tx_data_reg62_o => tx_frame(61), mf_tx_data_reg61_o => tx_frame(60),
mf_tx_data_reg63_o => tx_frame(62), mf_tx_data_reg62_o => tx_frame(61),
mf_tx_data_reg64_o => tx_frame(63), mf_tx_data_reg63_o => tx_frame(62),
mf_tx_data_reg65_o => tx_frame(64), mf_tx_data_reg64_o => tx_frame(63),
mf_tx_data_reg66_o => tx_frame(65)); mf_tx_data_reg65_o => tx_frame(64),
mf_tx_data_reg66_o => tx_frame(65));
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- resets -- -- resets --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -411,143 +415,155 @@ begin ...@@ -411,143 +415,155 @@ begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- external sync -- -- external sync --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- synchronizer and edge detection
cmp_ext_sync_p_detect: gc_sync_ffs cmp_ext_sync_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive") generic map(g_sync_edge => "positive")
port map( port map
clk_i => clk_i, (clk_i => clk_i,
rst_n_i => core_rst_n, rst_n_i => core_rst_n,
data_i => ext_sync_i, data_i => ext_sync_i,
ppulse_o => ext_sync_p); ppulse_o => ext_sync_p);
-- pulses counter
cmp_ext_sync_p_cnt:incr_counter
generic map(g_counter_lgth => 32)
port map
(clk_i => clk_i,
counter_incr_i => ext_sync_p,
counter_reinit_i => ext_sync_p_cnt_rst,
counter_o => ext_sync_p_cnt);
-- -- -- -- -- -- -- -- -- -- --
ext_sync_p_cnt_rst <= ext_sync_p_cnt_host_rst or core_rst;
--
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- macrocycle counter -- -- macrocycle counter --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- macrocycle counter
cmp_macrocycle_cnt: decr_counter cmp_macrocycle_cnt: decr_counter
generic map(width => 31) generic map(width => 31)
port map( port map
clk_i => clk_i, (clk_i => clk_i,
rst_i => core_rst, rst_i => core_rst,
counter_load_i => macrocyc_load_p, counter_load_i => macrocyc_load_p,
counter_top_i => macrocyc_lgth, counter_top_i => macrocyc_lgth,
counter_o => macrocyc_cnt, counter_o => macrocyc_cnt,
counter_is_zero_o => macrocyc_cnt_zero_p); counter_is_zero_o => macrocyc_cnt_zero_p);
-- -- -- -- -- -- -- -- -- -- --
macrocyc_load_p <= macrocyc_cnt_zero_p or macrocyc_host_load_p or ext_sync_p; macrocyc_load_p <= macrocyc_cnt_zero_p or macrocyc_host_load_p or ext_sync_p;
-- edge detection of the macrocyc_host_load signal
cmp_macrocyc_host_load_p_detect: gc_sync_ffs cmp_macrocyc_host_load_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive") generic map(g_sync_edge => "positive")
port map( port map
clk_i => clk_i, (clk_i => clk_i,
rst_n_i => core_rst_n, rst_n_i => core_rst_n,
data_i => macrocyc_host_load, data_i => macrocyc_host_load,
ppulse_o => macrocyc_host_load_p); ppulse_o => macrocyc_host_load_p);
-- in an application where an external synchronization pulse is expected for every macrocyle,
-- the macrocyc_lgth is set slightly larger than the external synchronization period; therefore
-- th macrocycle counter should not be reaching zero; if it reaches zero, it means that the
-- external synchronization pulse did not arrive in time
cmp_out_of_sync_led: gc_extend_pulse
generic map
(g_width => 1000000)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => macrocyc_cnt_zero_p,
extended_o => out_of_sync_led);
cmp_sync_led: gc_extend_pulse
generic map
(g_width => 1000000)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => ext_sync_p,
extended_o => sync_led);
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- turnaround counter -- -- turnaround counter --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- turnaround counter
cmp_turnaround_cnt: decr_counter cmp_turnaround_cnt: decr_counter
generic map(width => 31) generic map(width => 31)
port map( port map
clk_i => clk_i, (clk_i => clk_i,
rst_i => core_rst, rst_i => core_rst,
counter_load_i => turnar_load_p, counter_load_i => turnar_load_p,
counter_top_i => turnar_lgth, counter_top_i => turnar_lgth,
counter_o => turnar_cnt, counter_o => turnar_cnt,
counter_is_zero_o => open); counter_is_zero_o => open);
-- -- -- -- -- -- -- -- -- -- --
turnar_load_p <= tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or turnar_host_load_p; turnar_load_p <= tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or turnar_host_load_p;
turnar_host_load_p_detect: gc_sync_ffs -- edge detection of the turnar_host_load signal
cmp_turnar_host_load_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive") generic map(g_sync_edge => "positive")
port map( port map
clk_i => clk_i, (clk_i => clk_i,
rst_n_i => core_rst_n, rst_n_i => core_rst_n,
data_i => turnar_host_load, data_i => turnar_host_load,
ppulse_o => turnar_host_load_p); ppulse_o => turnar_host_load_p);
-------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------
-- silence counter -- -- silence counter --
-------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------
-- silence time: maximum amount of time that the masterFIP waits for a response frame. -- silence time: maximum amount of time that the masterFIP waits for a response frame.
-- the counting starts after an ID_DAT sent by the master (therefore loaded upon tx_completed_p) -- the counting starts after an ID_DAT sent by the master (therefore loaded upon tx_completed_p)
-- or by the FES of an RP_DAT_MSG as a RP_FIN is expected afterwards -- or by the FES of an RP_DAT_MSG as a RP_FIN is expected afterwards
cmp_silence_cnt: decr_counter cmp_silence_cnt: decr_counter
generic map(width => 31) generic map(width => 31)
port map( port map
clk_i => clk_i, (clk_i => clk_i,
rst_i => core_rst, rst_i => core_rst,
counter_load_i => silen_load_p, counter_load_i => silen_load_p,
counter_top_i => silen_lgth, counter_top_i => silen_lgth,
counter_o => silen_cnt, counter_o => silen_cnt,
counter_is_zero_o => open); counter_is_zero_o => open);
-- -- -- -- -- -- -- -- -- -- --
silen_load_p <= tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or silen_host_load_p; silen_load_p <= tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or silen_host_load_p;
-- edge detection of the silen_host_load signal
cmp_silen_host_load_p_detect: gc_sync_ffs cmp_silen_host_load_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive") generic map(g_sync_edge => "positive")
port map( port map
clk_i => clk_i, (clk_i => clk_i,
rst_n_i => core_rst_n, rst_n_i => core_rst_n,
data_i => silen_host_load, data_i => silen_host_load,
ppulse_o => silen_host_load_p); ppulse_o => silen_host_load_p);
-------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------
-- signals for tx -- -- signals for tx --
-------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------
-- edge detection on the tx_start signal -- edge detection on the tx_start signal
cmp_tx_start_p_detect: gc_sync_ffs cmp_tx_start_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive") generic map(g_sync_edge => "positive")
port map( port map
clk_i => clk_i, (clk_i => clk_i,
rst_n_i => core_rst_n, rst_n_i => core_rst_n,
data_i => tx_start, data_i => tx_start,
ppulse_o => tx_start_p); ppulse_o => tx_start_p);
-------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------
-- signals for rx -- -- signals for rx --
-------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------
-- extension of the rx_fss_received_p so as to ensure capturing by the wrnc -- edge detection on the rx_host_rst signal
-- cmp_rx_extend_p : gc_extend_pulse cmp_rx_host_rst_p_detect: gc_sync_ffs
-- generic map (
-- g_width => 32)
-- port map (
-- clk_i => clk_i,
-- rst_n_i => core_rst_n,
-- pulse_i => rx_fss_received_p,
-- extended_o => rx_fss_received);
-- extension of the rx_frame_ok_p so as to ensure capturing by the wrnc
-- cmp_rx_frame_ok_extend_p : gc_extend_pulse
-- generic map (
-- g_width => 32)
-- port map (
-- clk_i => clk_i,
-- rst_n_i => core_rst_n,
-- pulse_i => rx_frame_ok_p_d1,
-- extended_o => rx_frame_ok);
-- extension of the rx_crc_wrong_p so as to ensure capturing by the wrnc
-- cmp_rx_crc_wrong_extend_p : gc_extend_pulse
-- generic map (
-- g_width => 32)
-- port map (
-- clk_i => clk_i,
-- rst_n_i => core_rst_n,
-- pulse_i => rx_crc_wrong_p,
-- extended_o => rx_crc_wrong);
cmp_rx_host_rst_pulse_detect: gc_sync_ffs
generic map(g_sync_edge => "positive") generic map(g_sync_edge => "positive")
port map( port map(
clk_i => clk_i, clk_i => clk_i,
rst_n_i => rst_n, rst_n_i => rst_n,
data_i => rx_host_rst, data_i => rx_host_rst,
ppulse_o => rx_host_rst_p); ppulse_o => rx_host_rst_p);
-- -- -- -- -- -- -- -- -- -- --
rx_rst <= rx_host_rst_p or fd_txena; rx_rst <= rx_host_rst_p or fd_txena;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
...@@ -568,7 +584,7 @@ begin ...@@ -568,7 +584,7 @@ begin
end process; end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- registering the number of received bytes -- extending the rx_fss_received_p until a core_rst or rx_rst is received
p_rx_fss_received_extend : process(clk_i) p_rx_fss_received_extend : process(clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
...@@ -583,7 +599,7 @@ begin ...@@ -583,7 +599,7 @@ begin
end process; end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- registering the number of received bytes -- extending the rx_crc_wrong_p until a core_rst or rx_rst is received
p_rx_crc_wrong_extend : process(clk_i) p_rx_crc_wrong_extend : process(clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
...@@ -601,44 +617,47 @@ begin ...@@ -601,44 +617,47 @@ begin
-- rx -- -- rx --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
cmp_masterfip_rx: masterfip_rx cmp_masterfip_rx: masterfip_rx
port map( port map
clk_40m_i => clk_i, (clk_40m_i => clk_i,
rst_i => core_rst, rst_i => core_rst,
speed_i => speed, speed_i => speed,
fd_rxd_a_i => fd_rxd_i, fd_rxd_a_i => fd_rxd_i,
rx_rst_i => rx_rst, -- reset from the WRNC or reset while transmitting rx_rst_i => rx_rst, -- reset from the WRNC or reset while transmitting
------------------------------------------------------------- -------------------------------------------------------------
rx_byte_index_o => rx_byte_index, -- current amount of bytes (counting starts after the fss; rx_byte_index_o => rx_byte_index, -- current amount of bytes (counting starts after the fss;
-- includes ctrl, data, crc, fes fields) -- includes ctrl, data, crc, fes fields)
rx_ctrl_byte_o => rx_ctrl_byte, rx_ctrl_byte_o => rx_ctrl_byte,
rx_frame_o => rx_frame, rx_frame_o => rx_frame,
rx_byte_o => rx_byte, rx_byte_o => rx_byte,
rx_byte_ready_p_o => rx_byte_ready_p, rx_byte_ready_p_o => rx_byte_ready_p,
rx_fss_crc_fes_ok_p_o => rx_frame_ok_p, rx_fss_crc_fes_ok_p_o => rx_frame_ok_p,
rx_fss_received_p_o => rx_fss_received_p, rx_fss_received_p_o => rx_fss_received_p,
rx_crc_wrong_p_o => rx_crc_wrong_p); rx_crc_wrong_p_o => rx_crc_wrong_p);
------------------------------------------------------------- -------------------------------------------------------------
speed <= speed_b1_i & speed_b0_i; speed <= speed_b1_i & speed_b0_i;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- tx -- -- tx --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
cmp_masterfip_tx: masterfip_tx cmp_masterfip_tx: masterfip_tx
port map( port map
clk_40m_i => clk_i, (clk_40m_i => clk_i,
rst_i => tx_rst, rst_i => tx_rst,
speed_i => speed, speed_i => speed,
tx_bytes_num_i => tx_bytes_num, tx_bytes_num_i => tx_bytes_num,
tx_start_p_i => tx_start_p, tx_start_p_i => tx_start_p,
tx_frame_i => tx_frame, tx_frame_i => tx_frame,
tx_ctrl_byte_i => tx_ctrl_byte, tx_ctrl_byte_i => tx_ctrl_byte,
------------------------------------------------------------- -------------------------------------------------------------
tx_byte_index_o => tx_byte_index, tx_byte_index_o => tx_byte_index,
tx_end_p_o => tx_completed_p, tx_end_p_o => tx_completed_p,
tx_data_o => fd_txd, tx_data_o => fd_txd,
tx_enable_o => fd_txena, tx_enable_o => fd_txena,
tx_clk_o => fd_txck); tx_clk_o => fd_txck);
------------------------------------------------------------- -------------------------------------------------------------
tx_rst <= core_rst or tx_host_rst_p; tx_rst <= core_rst or tx_host_rst_p;
...@@ -650,40 +669,38 @@ begin ...@@ -650,40 +669,38 @@ begin
-------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------
-- signals for tx -- -- signals for tx --
-------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------
-- edge detection on the tx_host_rst signal
-- create 1-clk-tick long pulse upon tx_host_rst
cmp_tx_host_rst_pulse_detect: gc_sync_ffs cmp_tx_host_rst_pulse_detect: gc_sync_ffs
generic map(g_sync_edge => "positive") generic map(g_sync_edge => "positive")
port map( port map
clk_i => clk_i, (clk_i => clk_i,
rst_n_i => rst_n, rst_n_i => rst_n,
data_i => tx_host_rst, data_i => tx_host_rst,
ppulse_o => tx_host_rst_p); ppulse_o => tx_host_rst_p);
-- extension of the tx_completed_p so as to ensure capturing by the wrnc -- extension of the tx_completed_p so as to ensure capturing by the wrnc
cmp_tx_extend_p : gc_extend_pulse cmp_tx_extend_p : gc_extend_pulse
generic map ( generic map (g_width => 32)
g_width => 32) port map
port map ( (clk_i => clk_i,
clk_i => clk_i, rst_n_i => core_rst_n,
rst_n_i => core_rst_n, pulse_i => tx_completed_p,
pulse_i => tx_completed_p, extended_o => tx_completed);
extended_o => tx_completed);
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- aux -- -- aux --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
aux_o(7) <= rx_fss_received_p; aux_o(7) <= out_of_sync_led;
aux_o(6) <= rx_fss_received; aux_o(6) <= macrocyc_host_load_p;
aux_o(5) <= rx_frame_ok; aux_o(5) <= macrocyc_load_p;
aux_o(4) <= rx_byte_ready_p; aux_o(4) <= rx_byte_ready_p;
aux_o(3) <= tx_host_rst; aux_o(3) <= macrocyc_cnt_zero_p;
aux_o(2) <= tx_completed_p; aux_o(2) <= ext_sync_p;--tx_completed;
aux_o(1) <= tx_start; aux_o(1) <= tx_start;
aux_o(0) <= rx_frame_ok_p; aux_o(0) <= sync_led;
ext_sync_oe_o <= ext_sync_oe;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- CHIPSCOPE -- -- CHIPSCOPE --
......
rtl/fmc_masterfip_csr.vhd
View file @ bc4cc976
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : fmc_masterfip_csr.vhd -- File : fmc_masterfip_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb -- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
-- Created : 10/21/15 17:14:44 -- Created : 10/27/15 14:50:00
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
...@@ -48,6 +48,10 @@ entity fmc_masterfip_csr is ...@@ -48,6 +48,10 @@ entity fmc_masterfip_csr is
mf_ext_sync_oe_o : out std_logic; mf_ext_sync_oe_o : out std_logic;
-- Port for BIT field: 'test pulse' in reg: 'ext sync' -- Port for BIT field: 'test pulse' in reg: 'ext sync'
mf_ext_sync_tst_n_o : out std_logic; mf_ext_sync_tst_n_o : out std_logic;
-- Port for BIT field: 'pulses counter reset' in reg: 'ext sync'
mf_ext_sync_p_cnt_rst_o : out std_logic;
-- Port for std_logic_vector field: 'ext_sync_p_cnt' in reg: 'ext sync pulses cnt'
mf_ext_sync_p_cnt_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: '150ohms terination of the bus' in reg: '150ohms bus termination' -- Port for BIT field: '150ohms terination of the bus' in reg: '150ohms bus termination'
mf_bus_term_en_n_o : out std_logic; mf_bus_term_en_n_o : out std_logic;
-- Port for std_logic_vector field: 'speed' in reg: 'speed' -- Port for std_logic_vector field: 'speed' in reg: 'speed'
...@@ -70,8 +74,6 @@ entity fmc_masterfip_csr is ...@@ -70,8 +74,6 @@ entity fmc_masterfip_csr is
mf_turnar_time_cnt_i : in std_logic_vector(30 downto 0); mf_turnar_time_cnt_i : in std_logic_vector(30 downto 0);
-- Port for std_logic_vector field: 'silence time counter' in reg: 'silence time cnt' -- Port for std_logic_vector field: 'silence time counter' in reg: 'silence time cnt'
mf_silen_time_cnt_i : in std_logic_vector(30 downto 0); mf_silen_time_cnt_i : in std_logic_vector(30 downto 0);
-- Port for std_logic_vector field: 'ext_sync_tstamp' in reg: 'ext sync tstamp'
mf_ext_sync_tstamp_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: 'tx rst' in reg: 'tx ctrl' -- Port for BIT field: 'tx rst' in reg: 'tx ctrl'
mf_tx_ctrl_rst_o : out std_logic; mf_tx_ctrl_rst_o : out std_logic;
-- Port for BIT field: 'tx strt' in reg: 'tx ctrl' -- Port for BIT field: 'tx strt' in reg: 'tx ctrl'
...@@ -382,6 +384,7 @@ signal mf_ext_sync_term_en_int : std_logic ; ...@@ -382,6 +384,7 @@ signal mf_ext_sync_term_en_int : std_logic ;
signal mf_ext_sync_dir_int : std_logic ; signal mf_ext_sync_dir_int : std_logic ;
signal mf_ext_sync_oe_int : std_logic ; signal mf_ext_sync_oe_int : std_logic ;
signal mf_ext_sync_tst_n_int : std_logic ; signal mf_ext_sync_tst_n_int : std_logic ;
signal mf_ext_sync_p_cnt_rst_int : std_logic ;
signal mf_bus_term_en_n_int : std_logic ; signal mf_bus_term_en_n_int : std_logic ;
signal mf_macrocyc_lgth_int : std_logic_vector(30 downto 0); signal mf_macrocyc_lgth_int : std_logic_vector(30 downto 0);
signal mf_macrocyc_start_int : std_logic ; signal mf_macrocyc_start_int : std_logic ;
...@@ -497,6 +500,7 @@ begin ...@@ -497,6 +500,7 @@ begin
mf_ext_sync_dir_int <= '0'; mf_ext_sync_dir_int <= '0';
mf_ext_sync_oe_int <= '0'; mf_ext_sync_oe_int <= '0';
mf_ext_sync_tst_n_int <= '0'; mf_ext_sync_tst_n_int <= '0';
mf_ext_sync_p_cnt_rst_int <= '0';
mf_bus_term_en_n_int <= '0'; mf_bus_term_en_n_int <= '0';
mf_macrocyc_lgth_int <= "0000000000000000000000000000000"; mf_macrocyc_lgth_int <= "0000000000000000000000000000000";
mf_macrocyc_start_int <= '0'; mf_macrocyc_start_int <= '0';
...@@ -681,16 +685,17 @@ begin ...@@ -681,16 +685,17 @@ begin
mf_ext_sync_dir_int <= wrdata_reg(1); mf_ext_sync_dir_int <= wrdata_reg(1);
mf_ext_sync_oe_int <= wrdata_reg(2); mf_ext_sync_oe_int <= wrdata_reg(2);
mf_ext_sync_tst_n_int <= wrdata_reg(3); mf_ext_sync_tst_n_int <= wrdata_reg(3);
mf_ext_sync_p_cnt_rst_int <= wrdata_reg(8);
end if; end if;
rddata_reg(0) <= mf_ext_sync_term_en_int; rddata_reg(0) <= mf_ext_sync_term_en_int;
rddata_reg(1) <= mf_ext_sync_dir_int; rddata_reg(1) <= mf_ext_sync_dir_int;
rddata_reg(2) <= mf_ext_sync_oe_int; rddata_reg(2) <= mf_ext_sync_oe_int;
rddata_reg(3) <= mf_ext_sync_tst_n_int; rddata_reg(3) <= mf_ext_sync_tst_n_int;
rddata_reg(8) <= mf_ext_sync_p_cnt_rst_int;
rddata_reg(4) <= 'X'; rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X'; rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X'; rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X'; rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X'; rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X'; rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X'; rddata_reg(11) <= 'X';
...@@ -717,6 +722,12 @@ begin ...@@ -717,6 +722,12 @@ begin
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00000100" => when "00000100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_ext_sync_p_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000101" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
mf_bus_term_en_n_int <= wrdata_reg(0); mf_bus_term_en_n_int <= wrdata_reg(0);
end if; end if;
...@@ -754,7 +765,7 @@ begin ...@@ -754,7 +765,7 @@ begin
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00000101" => when "00000110" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
rddata_reg(1 downto 0) <= mf_speed_i; rddata_reg(1 downto 0) <= mf_speed_i;
...@@ -790,7 +801,7 @@ begin ...@@ -790,7 +801,7 @@ begin
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00000110" => when "00000111" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
mf_macrocyc_lgth_int <= wrdata_reg(30 downto 0); mf_macrocyc_lgth_int <= wrdata_reg(30 downto 0);
mf_macrocyc_start_int <= wrdata_reg(31); mf_macrocyc_start_int <= wrdata_reg(31);
...@@ -799,7 +810,7 @@ begin ...@@ -799,7 +810,7 @@ begin
rddata_reg(31) <= mf_macrocyc_start_int; rddata_reg(31) <= mf_macrocyc_start_int;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00000111" => when "00001000" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
mf_turnar_lgth_int <= wrdata_reg(30 downto 0); mf_turnar_lgth_int <= wrdata_reg(30 downto 0);
mf_turnar_start_int <= wrdata_reg(31); mf_turnar_start_int <= wrdata_reg(31);
...@@ -808,7 +819,7 @@ begin ...@@ -808,7 +819,7 @@ begin
rddata_reg(31) <= mf_turnar_start_int; rddata_reg(31) <= mf_turnar_start_int;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00001000" => when "00001001" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
mf_silen_lgth_int <= wrdata_reg(30 downto 0); mf_silen_lgth_int <= wrdata_reg(30 downto 0);
mf_silen_start_int <= wrdata_reg(31); mf_silen_start_int <= wrdata_reg(31);
...@@ -817,33 +828,27 @@ begin ...@@ -817,33 +828,27 @@ begin
rddata_reg(31) <= mf_silen_start_int; rddata_reg(31) <= mf_silen_start_int;
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00001001" => when "00001010" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
rddata_reg(30 downto 0) <= mf_macrocyc_time_cnt_i; rddata_reg(30 downto 0) <= mf_macrocyc_time_cnt_i;
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00001010" => when "00001011" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
rddata_reg(30 downto 0) <= mf_turnar_time_cnt_i; rddata_reg(30 downto 0) <= mf_turnar_time_cnt_i;
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00001011" => when "00001100" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
end if; end if;
rddata_reg(30 downto 0) <= mf_silen_time_cnt_i; rddata_reg(30 downto 0) <= mf_silen_time_cnt_i;
rddata_reg(31) <= 'X'; rddata_reg(31) <= 'X';
ack_sreg(0) <= '1'; ack_sreg(0) <= '1';
ack_in_progress <= '1'; ack_in_progress <= '1';
when "00001100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_ext_sync_tstamp_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001101" => when "00001101" =>
if (wb_we_i = '1') then if (wb_we_i = '1') then
mf_tx_ctrl_rst_int <= wrdata_reg(0); mf_tx_ctrl_rst_int <= wrdata_reg(0);
...@@ -1960,6 +1965,9 @@ begin ...@@ -1960,6 +1965,9 @@ begin
mf_ext_sync_oe_o <= mf_ext_sync_oe_int; mf_ext_sync_oe_o <= mf_ext_sync_oe_int;
-- test pulse -- test pulse
mf_ext_sync_tst_n_o <= mf_ext_sync_tst_n_int; mf_ext_sync_tst_n_o <= mf_ext_sync_tst_n_int;
-- pulses counter reset
mf_ext_sync_p_cnt_rst_o <= mf_ext_sync_p_cnt_rst_int;
-- ext_sync_p_cnt
-- 150ohms terination of the bus -- 150ohms terination of the bus
mf_bus_term_en_n_o <= mf_bus_term_en_n_int; mf_bus_term_en_n_o <= mf_bus_term_en_n_int;
-- speed -- speed
...@@ -1978,7 +1986,6 @@ begin ...@@ -1978,7 +1986,6 @@ begin
-- macrocycle time counter -- macrocycle time counter
-- turnaround time counter -- turnaround time counter
-- silence time counter -- silence time counter
-- ext_sync_tstamp
-- tx rst -- tx rst
mf_tx_ctrl_rst_o <= mf_tx_ctrl_rst_int; mf_tx_ctrl_rst_o <= mf_tx_ctrl_rst_int;
-- tx strt -- tx strt
......
rtl/masterFIP_pkg.vhd
View file @ bc4cc976
...@@ -202,7 +202,8 @@ package masterFIP_pkg is ...@@ -202,7 +202,8 @@ package masterFIP_pkg is
mf_ext_sync_dir_o : out std_logic; mf_ext_sync_dir_o : out std_logic;
mf_ext_sync_oe_o : out std_logic; mf_ext_sync_oe_o : out std_logic;
mf_ext_sync_tst_n_o : out std_logic; mf_ext_sync_tst_n_o : out std_logic;
mf_ext_sync_tstamp_i : in std_logic_vector(31 downto 0); mf_ext_sync_p_cnt_rst_o : out std_logic;
mf_ext_sync_p_cnt_i : in std_logic_vector(31 downto 0);
mf_bus_term_en_n_o : out std_logic; mf_bus_term_en_n_o : out std_logic;
mf_speed_i : in std_logic_vector(1 downto 0); mf_speed_i : in std_logic_vector(1 downto 0);
...@@ -498,19 +499,34 @@ package masterFIP_pkg is ...@@ -498,19 +499,34 @@ package masterFIP_pkg is
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
component decr_counter component decr_counter
generic generic
(width : integer := 32); (width : integer := 32);
port port
(clk_i : in std_logic; (clk_i : in std_logic;
rst_i : in std_logic; rst_i : in std_logic;
counter_load_i : in std_logic; counter_load_i : in std_logic;
counter_top_i : in std_logic_vector(width-1 downto 0); counter_top_i : in std_logic_vector(width-1 downto 0);
------------------------------------------------------------- -------------------------------------------------------------
counter_is_zero_o : out std_logic; counter_is_zero_o : out std_logic;
counter_o : out std_logic_vector(width-1 downto 0)); counter_o : out std_logic_vector(width-1 downto 0));
------------------------------------------------------------- -------------------------------------------------------------
end component; end component;
---------------------------------------------------------------------------------------------------
component incr_counter is
generic
(g_counter_lgth : natural := 4);
port
(clk_i : in std_logic;
counter_incr_i : in std_logic;
counter_reinit_i : in std_logic;
-------------------------------------------------------------
counter_o : out std_logic_vector (g_counter_lgth-1 downto 0);
counter_is_full_o : out std_logic);
end component incr_counter;
-------------------------------------------------------------
end masterFIP_pkg; end masterFIP_pkg;
--================================================================================================= --=================================================================================================
......
rtl/masterfip_rx.vhd
View file @ bc4cc976
...@@ -153,7 +153,7 @@ architecture struc of masterfip_rx is ...@@ -153,7 +153,7 @@ architecture struc of masterfip_rx is
-- retreived bytes into 32-bit regs -- retreived bytes into 32-bit regs
signal byte0, byte1, byte2, byte3 : std_logic_vector(7 downto 0) := (others => '0'); signal byte0, byte1, byte2, byte3 : std_logic_vector(7 downto 0) := (others => '0');
signal word32 : std_logic_vector(31 downto 0); signal word32 : std_logic_vector(31 downto 0);
signal word32_num : integer range 0 to 31; signal word32_num : integer range 0 to 65;
-- bytes counter -- bytes counter
signal rx_byte_index, rx_byte_index_d1 : unsigned(8 downto 0) := (others => '0'); signal rx_byte_index, rx_byte_index_d1 : unsigned(8 downto 0) := (others => '0');
signal bytes_c_rst : std_logic; signal bytes_c_rst : std_logic;
......
rtl/masterfip_tx.vhd
View file @ bc4cc976
...@@ -137,7 +137,7 @@ architecture struc of masterfip_tx is ...@@ -137,7 +137,7 @@ architecture struc of masterfip_tx is
signal prod_bytes_c : unsigned(8 downto 0); signal prod_bytes_c : unsigned(8 downto 0);
signal ctrl_byte, tx_byte : std_logic_vector(7 downto 0); signal ctrl_byte, tx_byte : std_logic_vector(7 downto 0);
signal prod_frame : tx_frame_t; signal prod_frame : tx_frame_t;
signal word32_num : integer range 0 to 31; signal word32_num : integer range 0 to 65;
signal word32 : std_logic_vector(31 downto 0); signal word32 : std_logic_vector(31 downto 0);
-- bytes counter -- bytes counter
signal bytes_num : std_logic_vector(8 downto 0); signal bytes_num : std_logic_vector(8 downto 0);
......
rtl/wbgen/fmc_masterfip_csr.wb
View file @ bc4cc976
...@@ -146,9 +146,33 @@ peripheral { ...@@ -146,9 +146,33 @@ peripheral {
type = BIT; type = BIT;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
field {
name = "pulses counter reset";
prefix = "p_cnt_rst";
description = "resets the pulses counter";
type = BIT;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
}; };
reg {
name = "ext sync pulses cnt";
prefix = "ext_sync_p_cnt";
field {
name = "ext_sync_p_cnt";
description = "number of ext sync pulses";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- bus termination -- -- bus termination --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -301,21 +325,7 @@ peripheral { ...@@ -301,21 +325,7 @@ peripheral {
}; };
}; };
reg {
name = "ext sync tstamp";
prefix = "ext_sync_tstamp";
field {
name = "ext_sync_tstamp";
description = "timestamp of the last external sync pulse received";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- serializer ctrl -- -- serializer ctrl --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
......
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