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MasterFIP - Gateware
Commit bc4cc976 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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added counter of ext_sync_p

parent aae395c5
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rtl/fmc_masterFIP_core.vhd
View file @ bc4cc976
......@@ -123,7 +123,9 @@ architecture rtl of fmc_masterFIP_core is
-- config
signal speed : std_logic_vector(1 downto 0);
-- ext pulse
signal ext_sync_p : std_logic;
signal ext_sync_p, ext_sync_oe : std_logic;
signal ext_sync_p_cnt_rst, ext_sync_p_cnt_host_rst : std_logic;
signal ext_sync_p_cnt : std_logic_vector(31 downto 0);
-- counters
signal macrocyc_load_p, turnar_load_p, silen_load_p : std_logic;
signal macrocyc_lgth, turnar_lgth, silen_lgth : std_logic_vector(30 downto 0);
......@@ -146,6 +148,8 @@ architecture rtl of fmc_masterFIP_core is
signal rx_frame : rx_frame_t;
signal rx_ctrl_byte, rx_byte : std_logic_vector(7 downto 0);
signal rx_byte_index, rx_bytes_num : std_logic_vector(8 downto 0); -- up to 263 bytes
-- LEDs
signal sync_led, out_of_sync_led : std_logic;
-- chipscope
-- component chipscope_ila
......@@ -177,9 +181,9 @@ begin
-- REGISTERS --
---------------------------------------------------------------------------------------------------
cmp_masterfip_csr: fmc_masterfip_csr
port map(
port map
-- wishbone
rst_n_i => rst_n,
(rst_n_i => rst_n,
clk_sys_i => clk_i,
wb_adr_i => wb_adr_i(9 downto 2),
wb_dat_i => wb_dat_i,
......@@ -202,9 +206,10 @@ begin
-- external sync pulse
mf_ext_sync_term_en_o => ext_sync_term_en_o,
mf_ext_sync_dir_o => ext_sync_dir_o,
mf_ext_sync_oe_o => ext_sync_oe_o,
mf_ext_sync_oe_o => ext_sync_oe,
mf_ext_sync_tst_n_o => ext_sync_tst_n_o,
mf_ext_sync_tstamp_i => "00000000000000000000000000000000", -- external sync tstamp
mf_ext_sync_p_cnt_rst_o => ext_sync_p_cnt_host_rst,
mf_ext_sync_p_cnt_i => ext_sync_p_cnt,
-- bus termination
mf_bus_term_en_n_o => bus_term_en_n_o,
-- bus speed
......@@ -377,7 +382,6 @@ begin
mf_tx_data_reg66_o => tx_frame(65));
---------------------------------------------------------------------------------------------------
-- resets --
---------------------------------------------------------------------------------------------------
......@@ -411,84 +415,125 @@ begin
---------------------------------------------------------------------------------------------------
-- external sync --
---------------------------------------------------------------------------------------------------
-- synchronizer and edge detection
cmp_ext_sync_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => ext_sync_i,
ppulse_o => ext_sync_p);
-- pulses counter
cmp_ext_sync_p_cnt:incr_counter
generic map(g_counter_lgth => 32)
port map
(clk_i => clk_i,
counter_incr_i => ext_sync_p,
counter_reinit_i => ext_sync_p_cnt_rst,
counter_o => ext_sync_p_cnt);
-- -- -- -- -- -- -- -- -- -- --
ext_sync_p_cnt_rst <= ext_sync_p_cnt_host_rst or core_rst;
--
---------------------------------------------------------------------------------------------------
-- macrocycle counter --
---------------------------------------------------------------------------------------------------
-- macrocycle counter
cmp_macrocycle_cnt: decr_counter
generic map(width => 31)
port map(
clk_i => clk_i,
port map
(clk_i => clk_i,
rst_i => core_rst,
counter_load_i => macrocyc_load_p,
counter_top_i => macrocyc_lgth,
counter_o => macrocyc_cnt,
counter_is_zero_o => macrocyc_cnt_zero_p);
-- -- -- -- -- -- -- -- -- -- --
macrocyc_load_p <= macrocyc_cnt_zero_p or macrocyc_host_load_p or ext_sync_p;
-- edge detection of the macrocyc_host_load signal
cmp_macrocyc_host_load_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => macrocyc_host_load,
ppulse_o => macrocyc_host_load_p);
-- in an application where an external synchronization pulse is expected for every macrocyle,
-- the macrocyc_lgth is set slightly larger than the external synchronization period; therefore
-- th macrocycle counter should not be reaching zero; if it reaches zero, it means that the
-- external synchronization pulse did not arrive in time
cmp_out_of_sync_led: gc_extend_pulse
generic map
(g_width => 1000000)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => macrocyc_cnt_zero_p,
extended_o => out_of_sync_led);
cmp_sync_led: gc_extend_pulse
generic map
(g_width => 1000000)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => ext_sync_p,
extended_o => sync_led);
---------------------------------------------------------------------------------------------------
-- turnaround counter --
---------------------------------------------------------------------------------------------------
-- turnaround counter
cmp_turnaround_cnt: decr_counter
generic map(width => 31)
port map(
clk_i => clk_i,
port map
(clk_i => clk_i,
rst_i => core_rst,
counter_load_i => turnar_load_p,
counter_top_i => turnar_lgth,
counter_o => turnar_cnt,
counter_is_zero_o => open);
-- -- -- -- -- -- -- -- -- -- --
turnar_load_p <= tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or turnar_host_load_p;
turnar_host_load_p_detect: gc_sync_ffs
-- edge detection of the turnar_host_load signal
cmp_turnar_host_load_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => turnar_host_load,
ppulse_o => turnar_host_load_p);
--------------------------------------------------------------------------------------------------
-- silence counter --
--------------------------------------------------------------------------------------------------
-- silence time: maximum amount of time that the masterFIP waits for a response frame.
-- the counting starts after an ID_DAT sent by the master (therefore loaded upon tx_completed_p)
-- or by the FES of an RP_DAT_MSG as a RP_FIN is expected afterwards
-- silence time: maximum amount of time that the masterFIP waits for a response frame.
-- the counting starts after an ID_DAT sent by the master (therefore loaded upon tx_completed_p)
-- or by the FES of an RP_DAT_MSG as a RP_FIN is expected afterwards
cmp_silence_cnt: decr_counter
generic map(width => 31)
port map(
clk_i => clk_i,
port map
(clk_i => clk_i,
rst_i => core_rst,
counter_load_i => silen_load_p,
counter_top_i => silen_lgth,
counter_o => silen_cnt,
counter_is_zero_o => open);
-- -- -- -- -- -- -- -- -- -- --
silen_load_p <= tx_completed_p or rx_frame_ok_p or rx_crc_wrong_p or silen_host_load_p;
-- edge detection of the silen_host_load signal
cmp_silen_host_load_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => silen_host_load,
ppulse_o => silen_host_load_p);
......@@ -497,11 +542,11 @@ begin
--------------------------------------------------------------------------------------------------
-- signals for tx --
--------------------------------------------------------------------------------------------------
-- edge detection on the tx_start signal
-- edge detection on the tx_start signal
cmp_tx_start_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => tx_start,
ppulse_o => tx_start_p);
......@@ -510,44 +555,15 @@ begin
--------------------------------------------------------------------------------------------------
-- signals for rx --
--------------------------------------------------------------------------------------------------
-- extension of the rx_fss_received_p so as to ensure capturing by the wrnc
-- cmp_rx_extend_p : gc_extend_pulse
-- generic map (
-- g_width => 32)
-- port map (
-- clk_i => clk_i,
-- rst_n_i => core_rst_n,
-- pulse_i => rx_fss_received_p,
-- extended_o => rx_fss_received);
-- extension of the rx_frame_ok_p so as to ensure capturing by the wrnc
-- cmp_rx_frame_ok_extend_p : gc_extend_pulse
-- generic map (
-- g_width => 32)
-- port map (
-- clk_i => clk_i,
-- rst_n_i => core_rst_n,
-- pulse_i => rx_frame_ok_p_d1,
-- extended_o => rx_frame_ok);
-- extension of the rx_crc_wrong_p so as to ensure capturing by the wrnc
-- cmp_rx_crc_wrong_extend_p : gc_extend_pulse
-- generic map (
-- g_width => 32)
-- port map (
-- clk_i => clk_i,
-- rst_n_i => core_rst_n,
-- pulse_i => rx_crc_wrong_p,
-- extended_o => rx_crc_wrong);
cmp_rx_host_rst_pulse_detect: gc_sync_ffs
-- edge detection on the rx_host_rst signal
cmp_rx_host_rst_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
rst_n_i => rst_n,
data_i => rx_host_rst,
ppulse_o => rx_host_rst_p);
-- -- -- -- -- -- -- -- -- -- --
rx_rst <= rx_host_rst_p or fd_txena;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
......@@ -568,7 +584,7 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- registering the number of received bytes
-- extending the rx_fss_received_p until a core_rst or rx_rst is received
p_rx_fss_received_extend : process(clk_i)
begin
if rising_edge(clk_i) then
......@@ -583,7 +599,7 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- registering the number of received bytes
-- extending the rx_crc_wrong_p until a core_rst or rx_rst is received
p_rx_crc_wrong_extend : process(clk_i)
begin
if rising_edge(clk_i) then
......@@ -601,8 +617,8 @@ begin
-- rx --
---------------------------------------------------------------------------------------------------
cmp_masterfip_rx: masterfip_rx
port map(
clk_40m_i => clk_i,
port map
(clk_40m_i => clk_i,
rst_i => core_rst,
speed_i => speed,
fd_rxd_a_i => fd_rxd_i,
......@@ -620,13 +636,16 @@ begin
-------------------------------------------------------------
speed <= speed_b1_i & speed_b0_i;
---------------------------------------------------------------------------------------------------
-- tx --
---------------------------------------------------------------------------------------------------
cmp_masterfip_tx: masterfip_tx
port map(
clk_40m_i => clk_i,
port map
(clk_40m_i => clk_i,
rst_i => tx_rst,
speed_i => speed,
tx_bytes_num_i => tx_bytes_num,
......@@ -650,22 +669,20 @@ begin
--------------------------------------------------------------------------------------------------
-- signals for tx --
--------------------------------------------------------------------------------------------------
-- create 1-clk-tick long pulse upon tx_host_rst
-- edge detection on the tx_host_rst signal
cmp_tx_host_rst_pulse_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map(
clk_i => clk_i,
port map
(clk_i => clk_i,
rst_n_i => rst_n,
data_i => tx_host_rst,
ppulse_o => tx_host_rst_p);
-- extension of the tx_completed_p so as to ensure capturing by the wrnc
-- extension of the tx_completed_p so as to ensure capturing by the wrnc
cmp_tx_extend_p : gc_extend_pulse
generic map (
g_width => 32)
port map (
clk_i => clk_i,
generic map (g_width => 32)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
pulse_i => tx_completed_p,
extended_o => tx_completed);
......@@ -674,16 +691,16 @@ begin
---------------------------------------------------------------------------------------------------
-- aux --
---------------------------------------------------------------------------------------------------
aux_o(7) <= rx_fss_received_p;
aux_o(6) <= rx_fss_received;
aux_o(5) <= rx_frame_ok;
aux_o(7) <= out_of_sync_led;
aux_o(6) <= macrocyc_host_load_p;
aux_o(5) <= macrocyc_load_p;
aux_o(4) <= rx_byte_ready_p;
aux_o(3) <= tx_host_rst;
aux_o(2) <= tx_completed_p;
aux_o(3) <= macrocyc_cnt_zero_p;
aux_o(2) <= ext_sync_p;--tx_completed;
aux_o(1) <= tx_start;
aux_o(0) <= rx_frame_ok_p;
aux_o(0) <= sync_led;
ext_sync_oe_o <= ext_sync_oe;
---------------------------------------------------------------------------------------------------
-- CHIPSCOPE --
......
rtl/fmc_masterfip_csr.vhd
View file @ bc4cc976
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fmc_masterfip_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_masterfip_csr.wb
-- Created : 10/21/15 17:14:44
-- Created : 10/27/15 14:50:00
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
......@@ -48,6 +48,10 @@ entity fmc_masterfip_csr is
mf_ext_sync_oe_o : out std_logic;
-- Port for BIT field: 'test pulse' in reg: 'ext sync'
mf_ext_sync_tst_n_o : out std_logic;
-- Port for BIT field: 'pulses counter reset' in reg: 'ext sync'
mf_ext_sync_p_cnt_rst_o : out std_logic;
-- Port for std_logic_vector field: 'ext_sync_p_cnt' in reg: 'ext sync pulses cnt'
mf_ext_sync_p_cnt_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: '150ohms terination of the bus' in reg: '150ohms bus termination'
mf_bus_term_en_n_o : out std_logic;
-- Port for std_logic_vector field: 'speed' in reg: 'speed'
......@@ -70,8 +74,6 @@ entity fmc_masterfip_csr is
mf_turnar_time_cnt_i : in std_logic_vector(30 downto 0);
-- Port for std_logic_vector field: 'silence time counter' in reg: 'silence time cnt'
mf_silen_time_cnt_i : in std_logic_vector(30 downto 0);
-- Port for std_logic_vector field: 'ext_sync_tstamp' in reg: 'ext sync tstamp'
mf_ext_sync_tstamp_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: 'tx rst' in reg: 'tx ctrl'
mf_tx_ctrl_rst_o : out std_logic;
-- Port for BIT field: 'tx strt' in reg: 'tx ctrl'
......@@ -382,6 +384,7 @@ signal mf_ext_sync_term_en_int : std_logic ;
signal mf_ext_sync_dir_int : std_logic ;
signal mf_ext_sync_oe_int : std_logic ;
signal mf_ext_sync_tst_n_int : std_logic ;
signal mf_ext_sync_p_cnt_rst_int : std_logic ;
signal mf_bus_term_en_n_int : std_logic ;
signal mf_macrocyc_lgth_int : std_logic_vector(30 downto 0);
signal mf_macrocyc_start_int : std_logic ;
......@@ -497,6 +500,7 @@ begin
mf_ext_sync_dir_int <= '0';
mf_ext_sync_oe_int <= '0';
mf_ext_sync_tst_n_int <= '0';
mf_ext_sync_p_cnt_rst_int <= '0';
mf_bus_term_en_n_int <= '0';
mf_macrocyc_lgth_int <= "0000000000000000000000000000000";
mf_macrocyc_start_int <= '0';
......@@ -681,16 +685,17 @@ begin
mf_ext_sync_dir_int <= wrdata_reg(1);
mf_ext_sync_oe_int <= wrdata_reg(2);
mf_ext_sync_tst_n_int <= wrdata_reg(3);
mf_ext_sync_p_cnt_rst_int <= wrdata_reg(8);
end if;
rddata_reg(0) <= mf_ext_sync_term_en_int;
rddata_reg(1) <= mf_ext_sync_dir_int;
rddata_reg(2) <= mf_ext_sync_oe_int;
rddata_reg(3) <= mf_ext_sync_tst_n_int;
rddata_reg(8) <= mf_ext_sync_p_cnt_rst_int;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
......@@ -717,6 +722,12 @@ begin
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_ext_sync_p_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000101" =>
if (wb_we_i = '1') then
mf_bus_term_en_n_int <= wrdata_reg(0);
end if;
......@@ -754,7 +765,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000101" =>
when "00000110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(1 downto 0) <= mf_speed_i;
......@@ -790,7 +801,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000110" =>
when "00000111" =>
if (wb_we_i = '1') then
mf_macrocyc_lgth_int <= wrdata_reg(30 downto 0);
mf_macrocyc_start_int <= wrdata_reg(31);
......@@ -799,7 +810,7 @@ begin
rddata_reg(31) <= mf_macrocyc_start_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000111" =>
when "00001000" =>
if (wb_we_i = '1') then
mf_turnar_lgth_int <= wrdata_reg(30 downto 0);
mf_turnar_start_int <= wrdata_reg(31);
......@@ -808,7 +819,7 @@ begin
rddata_reg(31) <= mf_turnar_start_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001000" =>
when "00001001" =>
if (wb_we_i = '1') then
mf_silen_lgth_int <= wrdata_reg(30 downto 0);
mf_silen_start_int <= wrdata_reg(31);
......@@ -817,33 +828,27 @@ begin
rddata_reg(31) <= mf_silen_start_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001001" =>
when "00001010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(30 downto 0) <= mf_macrocyc_time_cnt_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001010" =>
when "00001011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(30 downto 0) <= mf_turnar_time_cnt_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001011" =>
when "00001100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(30 downto 0) <= mf_silen_time_cnt_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mf_ext_sync_tstamp_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001101" =>
if (wb_we_i = '1') then
mf_tx_ctrl_rst_int <= wrdata_reg(0);
......@@ -1960,6 +1965,9 @@ begin
mf_ext_sync_oe_o <= mf_ext_sync_oe_int;
-- test pulse
mf_ext_sync_tst_n_o <= mf_ext_sync_tst_n_int;
-- pulses counter reset
mf_ext_sync_p_cnt_rst_o <= mf_ext_sync_p_cnt_rst_int;
-- ext_sync_p_cnt
-- 150ohms terination of the bus
mf_bus_term_en_n_o <= mf_bus_term_en_n_int;
-- speed
......@@ -1978,7 +1986,6 @@ begin
-- macrocycle time counter
-- turnaround time counter
-- silence time counter
-- ext_sync_tstamp
-- tx rst
mf_tx_ctrl_rst_o <= mf_tx_ctrl_rst_int;
-- tx strt
......
rtl/masterFIP_pkg.vhd
View file @ bc4cc976
......@@ -202,7 +202,8 @@ package masterFIP_pkg is
mf_ext_sync_dir_o : out std_logic;
mf_ext_sync_oe_o : out std_logic;
mf_ext_sync_tst_n_o : out std_logic;
mf_ext_sync_tstamp_i : in std_logic_vector(31 downto 0);
mf_ext_sync_p_cnt_rst_o : out std_logic;
mf_ext_sync_p_cnt_i : in std_logic_vector(31 downto 0);
mf_bus_term_en_n_o : out std_logic;
mf_speed_i : in std_logic_vector(1 downto 0);
......@@ -511,6 +512,21 @@ package masterFIP_pkg is
-------------------------------------------------------------
end component;
---------------------------------------------------------------------------------------------------
component incr_counter is
generic
(g_counter_lgth : natural := 4);
port
(clk_i : in std_logic;
counter_incr_i : in std_logic;
counter_reinit_i : in std_logic;
-------------------------------------------------------------
counter_o : out std_logic_vector (g_counter_lgth-1 downto 0);
counter_is_full_o : out std_logic);
end component incr_counter;
-------------------------------------------------------------
end masterFIP_pkg;
--=================================================================================================
......
rtl/masterfip_rx.vhd
View file @ bc4cc976
......@@ -153,7 +153,7 @@ architecture struc of masterfip_rx is
-- retreived bytes into 32-bit regs
signal byte0, byte1, byte2, byte3 : std_logic_vector(7 downto 0) := (others => '0');
signal word32 : std_logic_vector(31 downto 0);
signal word32_num : integer range 0 to 31;
signal word32_num : integer range 0 to 65;
-- bytes counter
signal rx_byte_index, rx_byte_index_d1 : unsigned(8 downto 0) := (others => '0');
signal bytes_c_rst : std_logic;
......
rtl/masterfip_tx.vhd
View file @ bc4cc976
......@@ -137,7 +137,7 @@ architecture struc of masterfip_tx is
signal prod_bytes_c : unsigned(8 downto 0);
signal ctrl_byte, tx_byte : std_logic_vector(7 downto 0);
signal prod_frame : tx_frame_t;
signal word32_num : integer range 0 to 31;
signal word32_num : integer range 0 to 65;
signal word32 : std_logic_vector(31 downto 0);
-- bytes counter
signal bytes_num : std_logic_vector(8 downto 0);
......
rtl/wbgen/fmc_masterfip_csr.wb
View file @ bc4cc976
......@@ -147,6 +147,30 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "pulses counter reset";
prefix = "p_cnt_rst";
description = "resets the pulses counter";
type = BIT;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "ext sync pulses cnt";
prefix = "ext_sync_p_cnt";
field {
name = "ext_sync_p_cnt";
description = "number of ext sync pulses";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
-------------------------------------------------------------------------------
......@@ -301,20 +325,6 @@ peripheral {
};
};
reg {
name = "ext sync tstamp";
prefix = "ext_sync_tstamp";
field {
name = "ext_sync_tstamp";
description = "timestamp of the last external sync pulse received";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
-------------------------------------------------------------------------------
-- serializer ctrl --
......
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