Skip to content

M
MasterFIP - Gateware
Commit c1d5c166 authored by Evangelia Gousiou's avatar Evangelia Gousiou
Browse files
Options

used wbgen2 files with versioning regs; resynthesised

parent 3fd8eb85
Hide whitespace changes
Inline Side-by-side
Showing with 3832 additions and 3511 deletions
rtl/masterfip_tx.vhd
View file @ c1d5c166
......@@ -105,9 +105,8 @@ use work.wf_package.all;
entity masterfip_tx is
generic
(g_span : integer := 32; -- address span in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
(g_span : integer := 32; -- address span in bus interfaces
g_width : integer := 32; -- data width in bus interfaces
g_simul : boolean := FALSE); -- set to TRUE when instantiated in a test-bench
......
rtl/masterfip_wbgen2_csr.vhd
View file @ c1d5c166
......@@ -3,7 +3,8 @@
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_csr.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 04/21/17 11:57:29
-- Created : 06/30/17 10:03:28
-- Version : 0x00000001
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
......@@ -37,6 +38,7 @@ end masterfip_wbgen2_csr;
architecture syn of masterfip_wbgen2_csr is
signal masterfip_ver_id_int : std_logic_vector(31 downto 0);
signal masterfip_rst_core_dly0 : std_logic ;
signal masterfip_rst_core_int : std_logic ;
signal masterfip_rst_fd_dly0 : std_logic ;
......@@ -141,22 +143,12 @@ signal masterfip_tx_payld_reg67_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(7 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
-- Some internal signals assignments
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
......@@ -165,6 +157,7 @@ begin
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
masterfip_ver_id_int <= "00000000000000000000000000000001";
masterfip_rst_core_int <= '0';
masterfip_rst_fd_int <= '0';
masterfip_led_rx_act_int <= '0';
......@@ -279,6 +272,13 @@ begin
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(7 downto 0) is
when "00000000" =>
if (wb_we_i = '1') then
masterfip_ver_id_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_ver_id_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000001" =>
if (wb_we_i = '1') then
masterfip_rst_core_int <= wrdata_reg(0);
masterfip_rst_fd_int <= wrdata_reg(1);
......@@ -319,13 +319,13 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "00000001" =>
when "00000010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= "11000000000000001111111111101110";
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000010" =>
when "00000011" =>
if (wb_we_i = '1') then
masterfip_led_rx_act_int <= wrdata_reg(0);
masterfip_led_rx_err_int <= wrdata_reg(1);
......@@ -346,7 +346,7 @@ begin
rddata_reg(7) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000011" =>
when "00000100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= regs_i.ds1820_temper_i;
......@@ -368,19 +368,19 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000100" =>
when "00000101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.ds1820_id_lsb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000101" =>
when "00000110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.ds1820_id_msb_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000110" =>
when "00000111" =>
if (wb_we_i = '1') then
masterfip_ext_sync_ctrl_term_en_int <= wrdata_reg(0);
masterfip_ext_sync_ctrl_dir_int <= wrdata_reg(1);
......@@ -423,13 +423,13 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00000111" =>
when "00001000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.ext_sync_p_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001000" =>
when "00001001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(1 downto 0) <= regs_i.speed_i;
......@@ -465,7 +465,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001001" =>
when "00001010" =>
if (wb_we_i = '1') then
masterfip_macrocyc_lgth_int <= wrdata_reg(30 downto 0);
masterfip_macrocyc_start_int <= wrdata_reg(31);
......@@ -474,20 +474,20 @@ begin
rddata_reg(31) <= '0';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "00001010" =>
when "00001011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(30 downto 0) <= regs_i.macrocyc_time_cnt_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001011" =>
when "00001100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.macrocyc_num_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001100" =>
when "00001101" =>
if (wb_we_i = '1') then
masterfip_turnar_lgth_int <= wrdata_reg(30 downto 0);
masterfip_turnar_start_int <= wrdata_reg(31);
......@@ -496,14 +496,14 @@ begin
rddata_reg(31) <= '0';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "00001101" =>
when "00001110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(30 downto 0) <= regs_i.turnar_time_cnt_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001110" =>
when "00001111" =>
if (wb_we_i = '1') then
masterfip_silen_lgth_int <= wrdata_reg(30 downto 0);
masterfip_silen_start_int <= wrdata_reg(31);
......@@ -512,14 +512,14 @@ begin
rddata_reg(31) <= '0';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "00001111" =>
when "00010000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(30 downto 0) <= regs_i.silen_time_cnt_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010000" =>
when "00010001" =>
if (wb_we_i = '1') then
masterfip_tx_ctrl_rst_int <= wrdata_reg(0);
masterfip_tx_ctrl_start_int <= wrdata_reg(1);
......@@ -544,7 +544,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "00010001" =>
when "00010010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= regs_i.tx_stat_stop_i;
......@@ -566,7 +566,7 @@ begin
rddata_reg(15) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010010" =>
when "00010011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= regs_i.fd_wdg_i;
......@@ -603,25 +603,25 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010011" =>
when "00010100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.fd_wdg_tstamp_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010100" =>
when "00010101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.fd_txer_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010101" =>
when "00010110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.fd_txer_tstamp_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010110" =>
when "00010111" =>
if (wb_we_i = '1') then
masterfip_rx_ctrl_rst_int <= wrdata_reg(0);
end if;
......@@ -659,7 +659,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "00010111" =>
when "00011000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= regs_i.rx_stat_pream_ok_i;
......@@ -681,7 +681,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011000" =>
when "00011001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= regs_i.rx_stat_curr_word_indx_i;
......@@ -711,13 +711,13 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011001" =>
when "00011010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_stat_crc_err_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011010" =>
when "00011011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(7 downto 0) <= regs_i.rx_payld_ctrl_i;
......@@ -747,409 +747,409 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011011" =>
when "00011100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg1_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011100" =>
when "00011101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg2_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011101" =>
when "00011110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg3_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011110" =>
when "00011111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg4_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011111" =>
when "00100000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg5_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100000" =>
when "00100001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg6_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100001" =>
when "00100010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg7_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100010" =>
when "00100011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg8_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100011" =>
when "00100100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg9_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100100" =>
when "00100101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg10_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100101" =>
when "00100110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg11_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100110" =>
when "00100111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg12_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100111" =>
when "00101000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg13_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101000" =>
when "00101001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg14_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101001" =>
when "00101010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg15_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101010" =>
when "00101011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg16_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101011" =>
when "00101100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg17_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101100" =>
when "00101101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg18_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101101" =>
when "00101110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg19_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101110" =>
when "00101111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg20_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101111" =>
when "00110000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg21_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110000" =>
when "00110001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg22_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110001" =>
when "00110010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg23_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110010" =>
when "00110011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg24_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110011" =>
when "00110100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg25_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110100" =>
when "00110101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg26_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110101" =>
when "00110110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg27_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110110" =>
when "00110111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg28_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110111" =>
when "00111000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg29_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111000" =>
when "00111001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg30_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111001" =>
when "00111010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg31_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111010" =>
when "00111011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg32_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111011" =>
when "00111100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg33_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111100" =>
when "00111101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg34_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111101" =>
when "00111110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg35_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111110" =>
when "00111111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg36_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111111" =>
when "01000000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg37_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000000" =>
when "01000001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg38_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000001" =>
when "01000010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg39_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000010" =>
when "01000011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg40_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000011" =>
when "01000100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg41_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000100" =>
when "01000101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg42_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000101" =>
when "01000110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg43_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000110" =>
when "01000111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg44_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000111" =>
when "01001000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg45_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001000" =>
when "01001001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg46_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001001" =>
when "01001010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg47_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001010" =>
when "01001011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg48_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001011" =>
when "01001100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg49_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001100" =>
when "01001101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg50_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001101" =>
when "01001110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg51_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001110" =>
when "01001111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg52_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001111" =>
when "01010000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg53_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010000" =>
when "01010001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg54_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010001" =>
when "01010010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg55_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010010" =>
when "01010011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg56_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010011" =>
when "01010100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg57_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010100" =>
when "01010101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg58_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010101" =>
when "01010110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg59_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010110" =>
when "01010111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg60_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010111" =>
when "01011000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg61_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011000" =>
when "01011001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg62_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011001" =>
when "01011010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg63_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011010" =>
when "01011011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg64_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011011" =>
when "01011100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg65_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011100" =>
when "01011101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg66_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011101" =>
when "01011110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.rx_payld_reg67_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011110" =>
when "01011111" =>
if (wb_we_i = '1') then
masterfip_tx_payld_ctrl_int <= wrdata_reg(7 downto 0);
end if;
......@@ -1180,469 +1180,469 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011111" =>
when "01100000" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg1_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg1_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100000" =>
when "01100001" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg2_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg2_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100001" =>
when "01100010" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg3_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg3_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100010" =>
when "01100011" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg4_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg4_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100011" =>
when "01100100" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg5_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg5_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100100" =>
when "01100101" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg6_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg6_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100101" =>
when "01100110" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg7_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg7_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100110" =>
when "01100111" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg8_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg8_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100111" =>
when "01101000" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg9_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg9_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101000" =>
when "01101001" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg10_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg10_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101001" =>
when "01101010" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg11_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg11_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101010" =>
when "01101011" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg12_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg12_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101011" =>
when "01101100" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg13_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg13_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101100" =>
when "01101101" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg14_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg14_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101101" =>
when "01101110" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg15_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg15_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101110" =>
when "01101111" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg16_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg16_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101111" =>
when "01110000" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg17_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg17_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110000" =>
when "01110001" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg18_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg18_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110001" =>
when "01110010" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg19_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg19_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110010" =>
when "01110011" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg20_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg20_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110011" =>
when "01110100" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg21_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg21_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110100" =>
when "01110101" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg22_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg22_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110101" =>
when "01110110" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg23_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg23_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110110" =>
when "01110111" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg24_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg24_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110111" =>
when "01111000" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg25_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg25_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111000" =>
when "01111001" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg26_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg26_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111001" =>
when "01111010" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg27_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg27_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111010" =>
when "01111011" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg28_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg28_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111011" =>
when "01111100" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg29_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg29_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111100" =>
when "01111101" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg30_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg30_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111101" =>
when "01111110" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg31_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg31_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111110" =>
when "01111111" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg32_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg32_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111111" =>
when "10000000" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg33_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg33_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000000" =>
when "10000001" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg34_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg34_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000001" =>
when "10000010" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg35_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg35_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000010" =>
when "10000011" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg36_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg36_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000011" =>
when "10000100" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg37_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg37_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000100" =>
when "10000101" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg38_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg38_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000101" =>
when "10000110" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg39_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg39_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000110" =>
when "10000111" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg40_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg40_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000111" =>
when "10001000" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg41_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg41_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001000" =>
when "10001001" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg42_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg42_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001001" =>
when "10001010" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg43_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg43_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001010" =>
when "10001011" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg44_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg44_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001011" =>
when "10001100" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg45_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg45_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001100" =>
when "10001101" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg46_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg46_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001101" =>
when "10001110" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg47_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg47_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001110" =>
when "10001111" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg48_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg48_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001111" =>
when "10010000" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg49_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg49_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010000" =>
when "10010001" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg50_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg50_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010001" =>
when "10010010" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg51_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg51_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010010" =>
when "10010011" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg52_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg52_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010011" =>
when "10010100" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg53_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg53_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010100" =>
when "10010101" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg54_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg54_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010101" =>
when "10010110" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg55_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg55_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010110" =>
when "10010111" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg56_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg56_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010111" =>
when "10011000" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg57_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg57_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011000" =>
when "10011001" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg58_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg58_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011001" =>
when "10011010" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg59_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg59_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011010" =>
when "10011011" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg60_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg60_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011011" =>
when "10011100" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg61_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg61_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011100" =>
when "10011101" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg62_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg62_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011101" =>
when "10011110" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg63_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg63_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011110" =>
when "10011111" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg64_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg64_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10011111" =>
when "10100000" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg65_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg65_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10100000" =>
when "10100001" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg66_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= masterfip_tx_payld_reg66_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10100001" =>
when "10100010" =>
if (wb_we_i = '1') then
masterfip_tx_payld_reg67_int <= wrdata_reg(31 downto 0);
end if;
......@@ -1662,6 +1662,8 @@ begin
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Version identifier
regs_o.ver_id_o <= masterfip_ver_id_int;
-- reset of the masterFIP core
process (clk_sys_i, rst_n_i)
begin
......
rtl/masterfip_wbgen2_pkg.vhd
View file @ c1d5c166
......@@ -3,7 +3,8 @@
---------------------------------------------------------------------------------------
-- File : masterfip_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from masterfip_csr.wb
-- Created : 04/21/17 11:57:29
-- Created : 06/30/17 10:03:28
-- Version : 0x00000001
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
......@@ -210,6 +211,7 @@ package masterfip_wbgen2_pkg is
-- Output registers (WB slave -> user design)
type t_masterfip_out_registers is record
ver_id_o : std_logic_vector(31 downto 0);
rst_core_o : std_logic;
rst_fd_o : std_logic;
led_rx_act_o : std_logic;
......@@ -306,6 +308,7 @@ package masterfip_wbgen2_pkg is
end record;
constant c_masterfip_out_registers_init_value: t_masterfip_out_registers := (
ver_id_o => (others => '0'),
rst_core_o => '0',
rst_fd_o => '0',
led_rx_act_o => '0',
......
rtl/wbgen/masterfip_csr.wb
View file @ c1d5c166
......@@ -2,8 +2,8 @@ peripheral {
name = "FMC masterFIP core registers";
description = "Wishbone slave for FMC masterFIP core";
hdl_entity = "masterfip_wbgen2_csr";
prefix = "masterfip";
version = 1;
-- Note that for html readability, some of the lines are longer than 100 characters.
......@@ -18,7 +18,8 @@ peripheral {
field {
name = "reset of the masterFIP core";
description = "write 1: generates a 1-clk-tick-long (10ns) masterFIP core reset;\
note: there is no need to clear the bit before writing another '1'";
note: there is no need to clear the bit before writing another '1';\
it s also not meaningful to read back this register";
type = MONOSTABLE;
prefix = "core";
};
......@@ -27,7 +28,8 @@ peripheral {
name = "reset of the FielDrive chip";
description = "write 1: to generate a FielDrive reset;\
upon writing, the fmc_masterFIP_core generates a 1-WorldFIP-clk-tick-long FD RSTN;\
note: there is no need to clear the bit before writing another '1'";
note: there is no need to clear the bit before writing another '1';\
it s also not meaningful to read back this register";
type = MONOSTABLE;
prefix = "fd";
};
......
rtl/wbgen/masterfip_wbgen2_csr.h
View file @ c1d5c166
......@@ -3,7 +3,8 @@
* File : masterfip_wbgen2_csr.h
* Author : auto-generated by wbgen2 from masterfip_csr.wb
* Created : 04/21/17 11:57:29
* Created : 06/30/17 10:03:28
* Version : 0x00000001
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE masterfip_csr.wb
......@@ -14,7 +15,11 @@
#ifndef __WBGEN2_REGDEFS_MASTERFIP_CSR_WB
#define __WBGEN2_REGDEFS_MASTERFIP_CSR_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......@@ -30,6 +35,17 @@
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* version definition */
#define WBGEN2_MASTERFIP_VERSION 0x00000001
/* definitions for register: Version register */
/* definitions for field: Version identifier in reg: Version register */
#define MASTERFIP_VER_ID_MASK WBGEN2_GEN_MASK(0, 32)
#define MASTERFIP_VER_ID_SHIFT 0
#define MASTERFIP_VER_ID_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define MASTERFIP_VER_ID_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: rst */
......@@ -477,328 +493,330 @@
/* definitions for register: tx payload reg66 */
/* definitions for register: tx payload reg67 */
/* [0x0]: REG rst */
#define MASTERFIP_REG_RST 0x00000000
/* [0x4]: REG core id */
#define MASTERFIP_REG_ID 0x00000004
/* [0x8]: REG leds and debug */
#define MASTERFIP_REG_LED 0x00000008
/* [0xc]: REG fmc temperature */
#define MASTERFIP_REG_DS1820_TEMPER 0x0000000c
/* [0x10]: REG fmc unique id lsb */
#define MASTERFIP_REG_DS1820_ID_LSB 0x00000010
/* [0x14]: REG fmc unique id msb */
#define MASTERFIP_REG_DS1820_ID_MSB 0x00000014
/* [0x18]: REG ext sync ctrl */
#define MASTERFIP_REG_EXT_SYNC_CTRL 0x00000018
/* [0x1c]: REG ext sync pulses cnt */
#define MASTERFIP_REG_EXT_SYNC_P_CNT 0x0000001c
/* [0x20]: REG bus speed */
#define MASTERFIP_REG_SPEED 0x00000020
/* [0x24]: REG macrocycle lgth */
#define MASTERFIP_REG_MACROCYC 0x00000024
/* [0x28]: REG macrocycle time cnt */
#define MASTERFIP_REG_MACROCYC_TIME_CNT 0x00000028
/* [0x2c]: REG macrocycles number cnt */
#define MASTERFIP_REG_MACROCYC_NUM_CNT 0x0000002c
/* [0x30]: REG turnaround lgth */
#define MASTERFIP_REG_TURNAR 0x00000030
/* [0x34]: REG turnaround time cnt */
#define MASTERFIP_REG_TURNAR_TIME_CNT 0x00000034
/* [0x38]: REG silence lgth */
#define MASTERFIP_REG_SILEN 0x00000038
/* [0x3c]: REG silence time cnt */
#define MASTERFIP_REG_SILEN_TIME_CNT 0x0000003c
/* [0x40]: REG tx ctrl */
#define MASTERFIP_REG_TX_CTRL 0x00000040
/* [0x44]: REG tx status */
#define MASTERFIP_REG_TX_STAT 0x00000044
/* [0x48]: REG FielDrive wdgn, cdn */
#define MASTERFIP_REG_FD 0x00000048
/* [0x4c]: REG FielDrive wdg timestamp */
#define MASTERFIP_REG_FD_WDG_TSTAMP 0x0000004c
/* [0x50]: REG FielDrive txer cnt */
#define MASTERFIP_REG_FD_TXER_CNT 0x00000050
/* [0x54]: REG FielDrive txer tstamp */
#define MASTERFIP_REG_FD_TXER_TSTAMP 0x00000054
/* [0x58]: REG rx ctrl */
#define MASTERFIP_REG_RX_CTRL 0x00000058
/* [0x5c]: REG rx status */
#define MASTERFIP_REG_RX_STAT 0x0000005c
/* [0x60]: REG rx current word index */
#define MASTERFIP_REG_RX_STAT_CURR_WORD_INDX 0x00000060
/* [0x64]: REG rx num of frames with CRC error */
#define MASTERFIP_REG_RX_STAT_CRC_ERR_CNT 0x00000064
/* [0x68]: REG rx payload ctrl byte */
#define MASTERFIP_REG_RX_PAYLD_CTRL 0x00000068
/* [0x6c]: REG rx payload reg1 */
#define MASTERFIP_REG_RX_PAYLD_REG1 0x0000006c
/* [0x70]: REG rx payload reg2 */
#define MASTERFIP_REG_RX_PAYLD_REG2 0x00000070
/* [0x74]: REG rx payload reg3 */
#define MASTERFIP_REG_RX_PAYLD_REG3 0x00000074
/* [0x78]: REG rx payload reg4 */
#define MASTERFIP_REG_RX_PAYLD_REG4 0x00000078
/* [0x7c]: REG rx payload reg5 */
#define MASTERFIP_REG_RX_PAYLD_REG5 0x0000007c
/* [0x80]: REG rx payload reg6 */
#define MASTERFIP_REG_RX_PAYLD_REG6 0x00000080
/* [0x84]: REG rx payload reg7 */
#define MASTERFIP_REG_RX_PAYLD_REG7 0x00000084
/* [0x88]: REG rx payload reg8 */
#define MASTERFIP_REG_RX_PAYLD_REG8 0x00000088
/* [0x8c]: REG rx payload reg9 */
#define MASTERFIP_REG_RX_PAYLD_REG9 0x0000008c
/* [0x90]: REG rx payload reg10 */
#define MASTERFIP_REG_RX_PAYLD_REG10 0x00000090
/* [0x94]: REG rx payload reg11 */
#define MASTERFIP_REG_RX_PAYLD_REG11 0x00000094
/* [0x98]: REG rx payload reg12 */
#define MASTERFIP_REG_RX_PAYLD_REG12 0x00000098
/* [0x9c]: REG rx payload reg13 */
#define MASTERFIP_REG_RX_PAYLD_REG13 0x0000009c
/* [0xa0]: REG rx payload reg14 */
#define MASTERFIP_REG_RX_PAYLD_REG14 0x000000a0
/* [0xa4]: REG rx payload reg15 */
#define MASTERFIP_REG_RX_PAYLD_REG15 0x000000a4
/* [0xa8]: REG rx payload reg16 */
#define MASTERFIP_REG_RX_PAYLD_REG16 0x000000a8
/* [0xac]: REG rx payload reg17 */
#define MASTERFIP_REG_RX_PAYLD_REG17 0x000000ac
/* [0xb0]: REG rx payload reg18 */
#define MASTERFIP_REG_RX_PAYLD_REG18 0x000000b0
/* [0xb4]: REG rx payload reg19 */
#define MASTERFIP_REG_RX_PAYLD_REG19 0x000000b4
/* [0xb8]: REG rx payload reg20 */
#define MASTERFIP_REG_RX_PAYLD_REG20 0x000000b8
/* [0xbc]: REG rx payload reg21 */
#define MASTERFIP_REG_RX_PAYLD_REG21 0x000000bc
/* [0xc0]: REG rx payload reg22 */
#define MASTERFIP_REG_RX_PAYLD_REG22 0x000000c0
/* [0xc4]: REG rx payload reg23 */
#define MASTERFIP_REG_RX_PAYLD_REG23 0x000000c4
/* [0xc8]: REG rx payload reg24 */
#define MASTERFIP_REG_RX_PAYLD_REG24 0x000000c8
/* [0xcc]: REG rx payload reg25 */
#define MASTERFIP_REG_RX_PAYLD_REG25 0x000000cc
/* [0xd0]: REG rx payload reg26 */
#define MASTERFIP_REG_RX_PAYLD_REG26 0x000000d0
/* [0xd4]: REG rx payload reg27 */
#define MASTERFIP_REG_RX_PAYLD_REG27 0x000000d4
/* [0xd8]: REG rx payload reg28 */
#define MASTERFIP_REG_RX_PAYLD_REG28 0x000000d8
/* [0xdc]: REG rx payload reg29 */
#define MASTERFIP_REG_RX_PAYLD_REG29 0x000000dc
/* [0xe0]: REG rx payload reg30 */
#define MASTERFIP_REG_RX_PAYLD_REG30 0x000000e0
/* [0xe4]: REG rx payload reg31 */
#define MASTERFIP_REG_RX_PAYLD_REG31 0x000000e4
/* [0xe8]: REG rx payload reg32 */
#define MASTERFIP_REG_RX_PAYLD_REG32 0x000000e8
/* [0xec]: REG rx payload reg33 */
#define MASTERFIP_REG_RX_PAYLD_REG33 0x000000ec
/* [0xf0]: REG rx payload reg34 */
#define MASTERFIP_REG_RX_PAYLD_REG34 0x000000f0
/* [0xf4]: REG rx payload reg35 */
#define MASTERFIP_REG_RX_PAYLD_REG35 0x000000f4
/* [0xf8]: REG rx payload reg36 */
#define MASTERFIP_REG_RX_PAYLD_REG36 0x000000f8
/* [0xfc]: REG rx payload reg37 */
#define MASTERFIP_REG_RX_PAYLD_REG37 0x000000fc
/* [0x100]: REG rx payload reg38 */
#define MASTERFIP_REG_RX_PAYLD_REG38 0x00000100
/* [0x104]: REG rx payload reg39 */
#define MASTERFIP_REG_RX_PAYLD_REG39 0x00000104
/* [0x108]: REG rx payload reg40 */
#define MASTERFIP_REG_RX_PAYLD_REG40 0x00000108
/* [0x10c]: REG rx payload reg41 */
#define MASTERFIP_REG_RX_PAYLD_REG41 0x0000010c
/* [0x110]: REG rx payload reg42 */
#define MASTERFIP_REG_RX_PAYLD_REG42 0x00000110
/* [0x114]: REG rx payload reg43 */
#define MASTERFIP_REG_RX_PAYLD_REG43 0x00000114
/* [0x118]: REG rx payload reg44 */
#define MASTERFIP_REG_RX_PAYLD_REG44 0x00000118
/* [0x11c]: REG rx payload reg45 */
#define MASTERFIP_REG_RX_PAYLD_REG45 0x0000011c
/* [0x120]: REG rx payload reg46 */
#define MASTERFIP_REG_RX_PAYLD_REG46 0x00000120
/* [0x124]: REG rx payload reg47 */
#define MASTERFIP_REG_RX_PAYLD_REG47 0x00000124
/* [0x128]: REG rx payload reg48 */
#define MASTERFIP_REG_RX_PAYLD_REG48 0x00000128
/* [0x12c]: REG rx payload reg49 */
#define MASTERFIP_REG_RX_PAYLD_REG49 0x0000012c
/* [0x130]: REG rx payload reg50 */
#define MASTERFIP_REG_RX_PAYLD_REG50 0x00000130
/* [0x134]: REG rx payload reg51 */
#define MASTERFIP_REG_RX_PAYLD_REG51 0x00000134
/* [0x138]: REG rx payload reg52 */
#define MASTERFIP_REG_RX_PAYLD_REG52 0x00000138
/* [0x13c]: REG rx payload reg53 */
#define MASTERFIP_REG_RX_PAYLD_REG53 0x0000013c
/* [0x140]: REG rx payload reg54 */
#define MASTERFIP_REG_RX_PAYLD_REG54 0x00000140
/* [0x144]: REG rx payload reg55 */
#define MASTERFIP_REG_RX_PAYLD_REG55 0x00000144
/* [0x148]: REG rx payload reg56 */
#define MASTERFIP_REG_RX_PAYLD_REG56 0x00000148
/* [0x14c]: REG rx payload reg57 */
#define MASTERFIP_REG_RX_PAYLD_REG57 0x0000014c
/* [0x150]: REG rx payload reg58 */
#define MASTERFIP_REG_RX_PAYLD_REG58 0x00000150
/* [0x154]: REG rx payload reg59 */
#define MASTERFIP_REG_RX_PAYLD_REG59 0x00000154
/* [0x158]: REG rx payload reg60 */
#define MASTERFIP_REG_RX_PAYLD_REG60 0x00000158
/* [0x15c]: REG rx payload reg61 */
#define MASTERFIP_REG_RX_PAYLD_REG61 0x0000015c
/* [0x160]: REG rx payload reg62 */
#define MASTERFIP_REG_RX_PAYLD_REG62 0x00000160
/* [0x164]: REG rx payload reg63 */
#define MASTERFIP_REG_RX_PAYLD_REG63 0x00000164
/* [0x168]: REG rx payload reg64 */
#define MASTERFIP_REG_RX_PAYLD_REG64 0x00000168
/* [0x16c]: REG rx payload reg65 */
#define MASTERFIP_REG_RX_PAYLD_REG65 0x0000016c
/* [0x170]: REG rx payload reg66 */
#define MASTERFIP_REG_RX_PAYLD_REG66 0x00000170
/* [0x174]: REG rx payload reg67 */
#define MASTERFIP_REG_RX_PAYLD_REG67 0x00000174
/* [0x178]: REG tx ctrl byte */
#define MASTERFIP_REG_TX_PAYLD_CTRL 0x00000178
/* [0x17c]: REG tx payload reg1 */
#define MASTERFIP_REG_TX_PAYLD_REG1 0x0000017c
/* [0x180]: REG tx payload reg2 */
#define MASTERFIP_REG_TX_PAYLD_REG2 0x00000180
/* [0x184]: REG tx payload reg3 */
#define MASTERFIP_REG_TX_PAYLD_REG3 0x00000184
/* [0x188]: REG tx payload reg4 */
#define MASTERFIP_REG_TX_PAYLD_REG4 0x00000188
/* [0x18c]: REG tx payload reg5 */
#define MASTERFIP_REG_TX_PAYLD_REG5 0x0000018c
/* [0x190]: REG tx payload reg6 */
#define MASTERFIP_REG_TX_PAYLD_REG6 0x00000190
/* [0x194]: REG tx payload reg7 */
#define MASTERFIP_REG_TX_PAYLD_REG7 0x00000194
/* [0x198]: REG tx payload reg8 */
#define MASTERFIP_REG_TX_PAYLD_REG8 0x00000198
/* [0x19c]: REG tx payload reg9 */
#define MASTERFIP_REG_TX_PAYLD_REG9 0x0000019c
/* [0x1a0]: REG tx payload reg10 */
#define MASTERFIP_REG_TX_PAYLD_REG10 0x000001a0
/* [0x1a4]: REG tx payload reg11 */
#define MASTERFIP_REG_TX_PAYLD_REG11 0x000001a4
/* [0x1a8]: REG tx payload reg12 */
#define MASTERFIP_REG_TX_PAYLD_REG12 0x000001a8
/* [0x1ac]: REG tx payload reg13 */
#define MASTERFIP_REG_TX_PAYLD_REG13 0x000001ac
/* [0x1b0]: REG tx payload reg14 */
#define MASTERFIP_REG_TX_PAYLD_REG14 0x000001b0
/* [0x1b4]: REG tx payload reg15 */
#define MASTERFIP_REG_TX_PAYLD_REG15 0x000001b4
/* [0x1b8]: REG tx payload reg16 */
#define MASTERFIP_REG_TX_PAYLD_REG16 0x000001b8
/* [0x1bc]: REG tx payload reg17 */
#define MASTERFIP_REG_TX_PAYLD_REG17 0x000001bc
/* [0x1c0]: REG tx payload reg18 */
#define MASTERFIP_REG_TX_PAYLD_REG18 0x000001c0
/* [0x1c4]: REG tx payload reg19 */
#define MASTERFIP_REG_TX_PAYLD_REG19 0x000001c4
/* [0x1c8]: REG tx payload reg20 */
#define MASTERFIP_REG_TX_PAYLD_REG20 0x000001c8
/* [0x1cc]: REG tx payload reg21 */
#define MASTERFIP_REG_TX_PAYLD_REG21 0x000001cc
/* [0x1d0]: REG tx payload reg22 */
#define MASTERFIP_REG_TX_PAYLD_REG22 0x000001d0
/* [0x1d4]: REG tx payload reg23 */
#define MASTERFIP_REG_TX_PAYLD_REG23 0x000001d4
/* [0x1d8]: REG tx payload reg24 */
#define MASTERFIP_REG_TX_PAYLD_REG24 0x000001d8
/* [0x1dc]: REG tx payload reg25 */
#define MASTERFIP_REG_TX_PAYLD_REG25 0x000001dc
/* [0x1e0]: REG tx payload reg26 */
#define MASTERFIP_REG_TX_PAYLD_REG26 0x000001e0
/* [0x1e4]: REG tx payload reg27 */
#define MASTERFIP_REG_TX_PAYLD_REG27 0x000001e4
/* [0x1e8]: REG tx payload reg28 */
#define MASTERFIP_REG_TX_PAYLD_REG28 0x000001e8
/* [0x1ec]: REG tx payload reg29 */
#define MASTERFIP_REG_TX_PAYLD_REG29 0x000001ec
/* [0x1f0]: REG tx payload reg30 */
#define MASTERFIP_REG_TX_PAYLD_REG30 0x000001f0
/* [0x1f4]: REG tx payload reg31 */
#define MASTERFIP_REG_TX_PAYLD_REG31 0x000001f4
/* [0x1f8]: REG tx payload reg32 */
#define MASTERFIP_REG_TX_PAYLD_REG32 0x000001f8
/* [0x1fc]: REG tx payload reg33 */
#define MASTERFIP_REG_TX_PAYLD_REG33 0x000001fc
/* [0x200]: REG tx payload reg34 */
#define MASTERFIP_REG_TX_PAYLD_REG34 0x00000200
/* [0x204]: REG tx payload reg35 */
#define MASTERFIP_REG_TX_PAYLD_REG35 0x00000204
/* [0x208]: REG tx payload reg36 */
#define MASTERFIP_REG_TX_PAYLD_REG36 0x00000208
/* [0x20c]: REG tx payload reg37 */
#define MASTERFIP_REG_TX_PAYLD_REG37 0x0000020c
/* [0x210]: REG tx payload reg38 */
#define MASTERFIP_REG_TX_PAYLD_REG38 0x00000210
/* [0x214]: REG tx payload reg39 */
#define MASTERFIP_REG_TX_PAYLD_REG39 0x00000214
/* [0x218]: REG tx payload reg40 */
#define MASTERFIP_REG_TX_PAYLD_REG40 0x00000218
/* [0x21c]: REG tx payload reg41 */
#define MASTERFIP_REG_TX_PAYLD_REG41 0x0000021c
/* [0x220]: REG tx payload reg42 */
#define MASTERFIP_REG_TX_PAYLD_REG42 0x00000220
/* [0x224]: REG tx payload reg43 */
#define MASTERFIP_REG_TX_PAYLD_REG43 0x00000224
/* [0x228]: REG tx payload reg44 */
#define MASTERFIP_REG_TX_PAYLD_REG44 0x00000228
/* [0x22c]: REG tx payload reg45 */
#define MASTERFIP_REG_TX_PAYLD_REG45 0x0000022c
/* [0x230]: REG tx payload reg46 */
#define MASTERFIP_REG_TX_PAYLD_REG46 0x00000230
/* [0x234]: REG tx payload reg47 */
#define MASTERFIP_REG_TX_PAYLD_REG47 0x00000234
/* [0x238]: REG tx payload reg48 */
#define MASTERFIP_REG_TX_PAYLD_REG48 0x00000238
/* [0x23c]: REG tx payload reg49 */
#define MASTERFIP_REG_TX_PAYLD_REG49 0x0000023c
/* [0x240]: REG tx payload reg50 */
#define MASTERFIP_REG_TX_PAYLD_REG50 0x00000240
/* [0x244]: REG tx payload reg51 */
#define MASTERFIP_REG_TX_PAYLD_REG51 0x00000244
/* [0x248]: REG tx payload reg52 */
#define MASTERFIP_REG_TX_PAYLD_REG52 0x00000248
/* [0x24c]: REG tx payload reg53 */
#define MASTERFIP_REG_TX_PAYLD_REG53 0x0000024c
/* [0x250]: REG tx payload reg54 */
#define MASTERFIP_REG_TX_PAYLD_REG54 0x00000250
/* [0x254]: REG tx payload reg55 */
#define MASTERFIP_REG_TX_PAYLD_REG55 0x00000254
/* [0x258]: REG tx payload reg56 */
#define MASTERFIP_REG_TX_PAYLD_REG56 0x00000258
/* [0x25c]: REG tx payload reg57 */
#define MASTERFIP_REG_TX_PAYLD_REG57 0x0000025c
/* [0x260]: REG tx payload reg58 */
#define MASTERFIP_REG_TX_PAYLD_REG58 0x00000260
/* [0x264]: REG tx payload reg59 */
#define MASTERFIP_REG_TX_PAYLD_REG59 0x00000264
/* [0x268]: REG tx payload reg60 */
#define MASTERFIP_REG_TX_PAYLD_REG60 0x00000268
/* [0x26c]: REG tx payload reg61 */
#define MASTERFIP_REG_TX_PAYLD_REG61 0x0000026c
/* [0x270]: REG tx payload reg62 */
#define MASTERFIP_REG_TX_PAYLD_REG62 0x00000270
/* [0x274]: REG tx payload reg63 */
#define MASTERFIP_REG_TX_PAYLD_REG63 0x00000274
/* [0x278]: REG tx payload reg64 */
#define MASTERFIP_REG_TX_PAYLD_REG64 0x00000278
/* [0x27c]: REG tx payload reg65 */
#define MASTERFIP_REG_TX_PAYLD_REG65 0x0000027c
/* [0x280]: REG tx payload reg66 */
#define MASTERFIP_REG_TX_PAYLD_REG66 0x00000280
/* [0x284]: REG tx payload reg67 */
#define MASTERFIP_REG_TX_PAYLD_REG67 0x00000284
/* [0x0]: REG Version register */
#define MASTERFIP_REG_VER 0x00000000
/* [0x4]: REG rst */
#define MASTERFIP_REG_RST 0x00000004
/* [0x8]: REG core id */
#define MASTERFIP_REG_ID 0x00000008
/* [0xc]: REG leds and debug */
#define MASTERFIP_REG_LED 0x0000000c
/* [0x10]: REG fmc temperature */
#define MASTERFIP_REG_DS1820_TEMPER 0x00000010
/* [0x14]: REG fmc unique id lsb */
#define MASTERFIP_REG_DS1820_ID_LSB 0x00000014
/* [0x18]: REG fmc unique id msb */
#define MASTERFIP_REG_DS1820_ID_MSB 0x00000018
/* [0x1c]: REG ext sync ctrl */
#define MASTERFIP_REG_EXT_SYNC_CTRL 0x0000001c
/* [0x20]: REG ext sync pulses cnt */
#define MASTERFIP_REG_EXT_SYNC_P_CNT 0x00000020
/* [0x24]: REG bus speed */
#define MASTERFIP_REG_SPEED 0x00000024
/* [0x28]: REG macrocycle lgth */
#define MASTERFIP_REG_MACROCYC 0x00000028
/* [0x2c]: REG macrocycle time cnt */
#define MASTERFIP_REG_MACROCYC_TIME_CNT 0x0000002c
/* [0x30]: REG macrocycles number cnt */
#define MASTERFIP_REG_MACROCYC_NUM_CNT 0x00000030
/* [0x34]: REG turnaround lgth */
#define MASTERFIP_REG_TURNAR 0x00000034
/* [0x38]: REG turnaround time cnt */
#define MASTERFIP_REG_TURNAR_TIME_CNT 0x00000038
/* [0x3c]: REG silence lgth */
#define MASTERFIP_REG_SILEN 0x0000003c
/* [0x40]: REG silence time cnt */
#define MASTERFIP_REG_SILEN_TIME_CNT 0x00000040
/* [0x44]: REG tx ctrl */
#define MASTERFIP_REG_TX_CTRL 0x00000044
/* [0x48]: REG tx status */
#define MASTERFIP_REG_TX_STAT 0x00000048
/* [0x4c]: REG FielDrive wdgn, cdn */
#define MASTERFIP_REG_FD 0x0000004c
/* [0x50]: REG FielDrive wdg timestamp */
#define MASTERFIP_REG_FD_WDG_TSTAMP 0x00000050
/* [0x54]: REG FielDrive txer cnt */
#define MASTERFIP_REG_FD_TXER_CNT 0x00000054
/* [0x58]: REG FielDrive txer tstamp */
#define MASTERFIP_REG_FD_TXER_TSTAMP 0x00000058
/* [0x5c]: REG rx ctrl */
#define MASTERFIP_REG_RX_CTRL 0x0000005c
/* [0x60]: REG rx status */
#define MASTERFIP_REG_RX_STAT 0x00000060
/* [0x64]: REG rx current word index */
#define MASTERFIP_REG_RX_STAT_CURR_WORD_INDX 0x00000064
/* [0x68]: REG rx num of frames with CRC error */
#define MASTERFIP_REG_RX_STAT_CRC_ERR_CNT 0x00000068
/* [0x6c]: REG rx payload ctrl byte */
#define MASTERFIP_REG_RX_PAYLD_CTRL 0x0000006c
/* [0x70]: REG rx payload reg1 */
#define MASTERFIP_REG_RX_PAYLD_REG1 0x00000070
/* [0x74]: REG rx payload reg2 */
#define MASTERFIP_REG_RX_PAYLD_REG2 0x00000074
/* [0x78]: REG rx payload reg3 */
#define MASTERFIP_REG_RX_PAYLD_REG3 0x00000078
/* [0x7c]: REG rx payload reg4 */
#define MASTERFIP_REG_RX_PAYLD_REG4 0x0000007c
/* [0x80]: REG rx payload reg5 */
#define MASTERFIP_REG_RX_PAYLD_REG5 0x00000080
/* [0x84]: REG rx payload reg6 */
#define MASTERFIP_REG_RX_PAYLD_REG6 0x00000084
/* [0x88]: REG rx payload reg7 */
#define MASTERFIP_REG_RX_PAYLD_REG7 0x00000088
/* [0x8c]: REG rx payload reg8 */
#define MASTERFIP_REG_RX_PAYLD_REG8 0x0000008c
/* [0x90]: REG rx payload reg9 */
#define MASTERFIP_REG_RX_PAYLD_REG9 0x00000090
/* [0x94]: REG rx payload reg10 */
#define MASTERFIP_REG_RX_PAYLD_REG10 0x00000094
/* [0x98]: REG rx payload reg11 */
#define MASTERFIP_REG_RX_PAYLD_REG11 0x00000098
/* [0x9c]: REG rx payload reg12 */
#define MASTERFIP_REG_RX_PAYLD_REG12 0x0000009c
/* [0xa0]: REG rx payload reg13 */
#define MASTERFIP_REG_RX_PAYLD_REG13 0x000000a0
/* [0xa4]: REG rx payload reg14 */
#define MASTERFIP_REG_RX_PAYLD_REG14 0x000000a4
/* [0xa8]: REG rx payload reg15 */
#define MASTERFIP_REG_RX_PAYLD_REG15 0x000000a8
/* [0xac]: REG rx payload reg16 */
#define MASTERFIP_REG_RX_PAYLD_REG16 0x000000ac
/* [0xb0]: REG rx payload reg17 */
#define MASTERFIP_REG_RX_PAYLD_REG17 0x000000b0
/* [0xb4]: REG rx payload reg18 */
#define MASTERFIP_REG_RX_PAYLD_REG18 0x000000b4
/* [0xb8]: REG rx payload reg19 */
#define MASTERFIP_REG_RX_PAYLD_REG19 0x000000b8
/* [0xbc]: REG rx payload reg20 */
#define MASTERFIP_REG_RX_PAYLD_REG20 0x000000bc
/* [0xc0]: REG rx payload reg21 */
#define MASTERFIP_REG_RX_PAYLD_REG21 0x000000c0
/* [0xc4]: REG rx payload reg22 */
#define MASTERFIP_REG_RX_PAYLD_REG22 0x000000c4
/* [0xc8]: REG rx payload reg23 */
#define MASTERFIP_REG_RX_PAYLD_REG23 0x000000c8
/* [0xcc]: REG rx payload reg24 */
#define MASTERFIP_REG_RX_PAYLD_REG24 0x000000cc
/* [0xd0]: REG rx payload reg25 */
#define MASTERFIP_REG_RX_PAYLD_REG25 0x000000d0
/* [0xd4]: REG rx payload reg26 */
#define MASTERFIP_REG_RX_PAYLD_REG26 0x000000d4
/* [0xd8]: REG rx payload reg27 */
#define MASTERFIP_REG_RX_PAYLD_REG27 0x000000d8
/* [0xdc]: REG rx payload reg28 */
#define MASTERFIP_REG_RX_PAYLD_REG28 0x000000dc
/* [0xe0]: REG rx payload reg29 */
#define MASTERFIP_REG_RX_PAYLD_REG29 0x000000e0
/* [0xe4]: REG rx payload reg30 */
#define MASTERFIP_REG_RX_PAYLD_REG30 0x000000e4
/* [0xe8]: REG rx payload reg31 */
#define MASTERFIP_REG_RX_PAYLD_REG31 0x000000e8
/* [0xec]: REG rx payload reg32 */
#define MASTERFIP_REG_RX_PAYLD_REG32 0x000000ec
/* [0xf0]: REG rx payload reg33 */
#define MASTERFIP_REG_RX_PAYLD_REG33 0x000000f0
/* [0xf4]: REG rx payload reg34 */
#define MASTERFIP_REG_RX_PAYLD_REG34 0x000000f4
/* [0xf8]: REG rx payload reg35 */
#define MASTERFIP_REG_RX_PAYLD_REG35 0x000000f8
/* [0xfc]: REG rx payload reg36 */
#define MASTERFIP_REG_RX_PAYLD_REG36 0x000000fc
/* [0x100]: REG rx payload reg37 */
#define MASTERFIP_REG_RX_PAYLD_REG37 0x00000100
/* [0x104]: REG rx payload reg38 */
#define MASTERFIP_REG_RX_PAYLD_REG38 0x00000104
/* [0x108]: REG rx payload reg39 */
#define MASTERFIP_REG_RX_PAYLD_REG39 0x00000108
/* [0x10c]: REG rx payload reg40 */
#define MASTERFIP_REG_RX_PAYLD_REG40 0x0000010c
/* [0x110]: REG rx payload reg41 */
#define MASTERFIP_REG_RX_PAYLD_REG41 0x00000110
/* [0x114]: REG rx payload reg42 */
#define MASTERFIP_REG_RX_PAYLD_REG42 0x00000114
/* [0x118]: REG rx payload reg43 */
#define MASTERFIP_REG_RX_PAYLD_REG43 0x00000118
/* [0x11c]: REG rx payload reg44 */
#define MASTERFIP_REG_RX_PAYLD_REG44 0x0000011c
/* [0x120]: REG rx payload reg45 */
#define MASTERFIP_REG_RX_PAYLD_REG45 0x00000120
/* [0x124]: REG rx payload reg46 */
#define MASTERFIP_REG_RX_PAYLD_REG46 0x00000124
/* [0x128]: REG rx payload reg47 */
#define MASTERFIP_REG_RX_PAYLD_REG47 0x00000128
/* [0x12c]: REG rx payload reg48 */
#define MASTERFIP_REG_RX_PAYLD_REG48 0x0000012c
/* [0x130]: REG rx payload reg49 */
#define MASTERFIP_REG_RX_PAYLD_REG49 0x00000130
/* [0x134]: REG rx payload reg50 */
#define MASTERFIP_REG_RX_PAYLD_REG50 0x00000134
/* [0x138]: REG rx payload reg51 */
#define MASTERFIP_REG_RX_PAYLD_REG51 0x00000138
/* [0x13c]: REG rx payload reg52 */
#define MASTERFIP_REG_RX_PAYLD_REG52 0x0000013c
/* [0x140]: REG rx payload reg53 */
#define MASTERFIP_REG_RX_PAYLD_REG53 0x00000140
/* [0x144]: REG rx payload reg54 */
#define MASTERFIP_REG_RX_PAYLD_REG54 0x00000144
/* [0x148]: REG rx payload reg55 */
#define MASTERFIP_REG_RX_PAYLD_REG55 0x00000148
/* [0x14c]: REG rx payload reg56 */
#define MASTERFIP_REG_RX_PAYLD_REG56 0x0000014c
/* [0x150]: REG rx payload reg57 */
#define MASTERFIP_REG_RX_PAYLD_REG57 0x00000150
/* [0x154]: REG rx payload reg58 */
#define MASTERFIP_REG_RX_PAYLD_REG58 0x00000154
/* [0x158]: REG rx payload reg59 */
#define MASTERFIP_REG_RX_PAYLD_REG59 0x00000158
/* [0x15c]: REG rx payload reg60 */
#define MASTERFIP_REG_RX_PAYLD_REG60 0x0000015c
/* [0x160]: REG rx payload reg61 */
#define MASTERFIP_REG_RX_PAYLD_REG61 0x00000160
/* [0x164]: REG rx payload reg62 */
#define MASTERFIP_REG_RX_PAYLD_REG62 0x00000164
/* [0x168]: REG rx payload reg63 */
#define MASTERFIP_REG_RX_PAYLD_REG63 0x00000168
/* [0x16c]: REG rx payload reg64 */
#define MASTERFIP_REG_RX_PAYLD_REG64 0x0000016c
/* [0x170]: REG rx payload reg65 */
#define MASTERFIP_REG_RX_PAYLD_REG65 0x00000170
/* [0x174]: REG rx payload reg66 */
#define MASTERFIP_REG_RX_PAYLD_REG66 0x00000174
/* [0x178]: REG rx payload reg67 */
#define MASTERFIP_REG_RX_PAYLD_REG67 0x00000178
/* [0x17c]: REG tx ctrl byte */
#define MASTERFIP_REG_TX_PAYLD_CTRL 0x0000017c
/* [0x180]: REG tx payload reg1 */
#define MASTERFIP_REG_TX_PAYLD_REG1 0x00000180
/* [0x184]: REG tx payload reg2 */
#define MASTERFIP_REG_TX_PAYLD_REG2 0x00000184
/* [0x188]: REG tx payload reg3 */
#define MASTERFIP_REG_TX_PAYLD_REG3 0x00000188
/* [0x18c]: REG tx payload reg4 */
#define MASTERFIP_REG_TX_PAYLD_REG4 0x0000018c
/* [0x190]: REG tx payload reg5 */
#define MASTERFIP_REG_TX_PAYLD_REG5 0x00000190
/* [0x194]: REG tx payload reg6 */
#define MASTERFIP_REG_TX_PAYLD_REG6 0x00000194
/* [0x198]: REG tx payload reg7 */
#define MASTERFIP_REG_TX_PAYLD_REG7 0x00000198
/* [0x19c]: REG tx payload reg8 */
#define MASTERFIP_REG_TX_PAYLD_REG8 0x0000019c
/* [0x1a0]: REG tx payload reg9 */
#define MASTERFIP_REG_TX_PAYLD_REG9 0x000001a0
/* [0x1a4]: REG tx payload reg10 */
#define MASTERFIP_REG_TX_PAYLD_REG10 0x000001a4
/* [0x1a8]: REG tx payload reg11 */
#define MASTERFIP_REG_TX_PAYLD_REG11 0x000001a8
/* [0x1ac]: REG tx payload reg12 */
#define MASTERFIP_REG_TX_PAYLD_REG12 0x000001ac
/* [0x1b0]: REG tx payload reg13 */
#define MASTERFIP_REG_TX_PAYLD_REG13 0x000001b0
/* [0x1b4]: REG tx payload reg14 */
#define MASTERFIP_REG_TX_PAYLD_REG14 0x000001b4
/* [0x1b8]: REG tx payload reg15 */
#define MASTERFIP_REG_TX_PAYLD_REG15 0x000001b8
/* [0x1bc]: REG tx payload reg16 */
#define MASTERFIP_REG_TX_PAYLD_REG16 0x000001bc
/* [0x1c0]: REG tx payload reg17 */
#define MASTERFIP_REG_TX_PAYLD_REG17 0x000001c0
/* [0x1c4]: REG tx payload reg18 */
#define MASTERFIP_REG_TX_PAYLD_REG18 0x000001c4
/* [0x1c8]: REG tx payload reg19 */
#define MASTERFIP_REG_TX_PAYLD_REG19 0x000001c8
/* [0x1cc]: REG tx payload reg20 */
#define MASTERFIP_REG_TX_PAYLD_REG20 0x000001cc
/* [0x1d0]: REG tx payload reg21 */
#define MASTERFIP_REG_TX_PAYLD_REG21 0x000001d0
/* [0x1d4]: REG tx payload reg22 */
#define MASTERFIP_REG_TX_PAYLD_REG22 0x000001d4
/* [0x1d8]: REG tx payload reg23 */
#define MASTERFIP_REG_TX_PAYLD_REG23 0x000001d8
/* [0x1dc]: REG tx payload reg24 */
#define MASTERFIP_REG_TX_PAYLD_REG24 0x000001dc
/* [0x1e0]: REG tx payload reg25 */
#define MASTERFIP_REG_TX_PAYLD_REG25 0x000001e0
/* [0x1e4]: REG tx payload reg26 */
#define MASTERFIP_REG_TX_PAYLD_REG26 0x000001e4
/* [0x1e8]: REG tx payload reg27 */
#define MASTERFIP_REG_TX_PAYLD_REG27 0x000001e8
/* [0x1ec]: REG tx payload reg28 */
#define MASTERFIP_REG_TX_PAYLD_REG28 0x000001ec
/* [0x1f0]: REG tx payload reg29 */
#define MASTERFIP_REG_TX_PAYLD_REG29 0x000001f0
/* [0x1f4]: REG tx payload reg30 */
#define MASTERFIP_REG_TX_PAYLD_REG30 0x000001f4
/* [0x1f8]: REG tx payload reg31 */
#define MASTERFIP_REG_TX_PAYLD_REG31 0x000001f8
/* [0x1fc]: REG tx payload reg32 */
#define MASTERFIP_REG_TX_PAYLD_REG32 0x000001fc
/* [0x200]: REG tx payload reg33 */
#define MASTERFIP_REG_TX_PAYLD_REG33 0x00000200
/* [0x204]: REG tx payload reg34 */
#define MASTERFIP_REG_TX_PAYLD_REG34 0x00000204
/* [0x208]: REG tx payload reg35 */
#define MASTERFIP_REG_TX_PAYLD_REG35 0x00000208
/* [0x20c]: REG tx payload reg36 */
#define MASTERFIP_REG_TX_PAYLD_REG36 0x0000020c
/* [0x210]: REG tx payload reg37 */
#define MASTERFIP_REG_TX_PAYLD_REG37 0x00000210
/* [0x214]: REG tx payload reg38 */
#define MASTERFIP_REG_TX_PAYLD_REG38 0x00000214
/* [0x218]: REG tx payload reg39 */
#define MASTERFIP_REG_TX_PAYLD_REG39 0x00000218
/* [0x21c]: REG tx payload reg40 */
#define MASTERFIP_REG_TX_PAYLD_REG40 0x0000021c
/* [0x220]: REG tx payload reg41 */
#define MASTERFIP_REG_TX_PAYLD_REG41 0x00000220
/* [0x224]: REG tx payload reg42 */
#define MASTERFIP_REG_TX_PAYLD_REG42 0x00000224
/* [0x228]: REG tx payload reg43 */
#define MASTERFIP_REG_TX_PAYLD_REG43 0x00000228
/* [0x22c]: REG tx payload reg44 */
#define MASTERFIP_REG_TX_PAYLD_REG44 0x0000022c
/* [0x230]: REG tx payload reg45 */
#define MASTERFIP_REG_TX_PAYLD_REG45 0x00000230
/* [0x234]: REG tx payload reg46 */
#define MASTERFIP_REG_TX_PAYLD_REG46 0x00000234
/* [0x238]: REG tx payload reg47 */
#define MASTERFIP_REG_TX_PAYLD_REG47 0x00000238
/* [0x23c]: REG tx payload reg48 */
#define MASTERFIP_REG_TX_PAYLD_REG48 0x0000023c
/* [0x240]: REG tx payload reg49 */
#define MASTERFIP_REG_TX_PAYLD_REG49 0x00000240
/* [0x244]: REG tx payload reg50 */
#define MASTERFIP_REG_TX_PAYLD_REG50 0x00000244
/* [0x248]: REG tx payload reg51 */
#define MASTERFIP_REG_TX_PAYLD_REG51 0x00000248
/* [0x24c]: REG tx payload reg52 */
#define MASTERFIP_REG_TX_PAYLD_REG52 0x0000024c
/* [0x250]: REG tx payload reg53 */
#define MASTERFIP_REG_TX_PAYLD_REG53 0x00000250
/* [0x254]: REG tx payload reg54 */
#define MASTERFIP_REG_TX_PAYLD_REG54 0x00000254
/* [0x258]: REG tx payload reg55 */
#define MASTERFIP_REG_TX_PAYLD_REG55 0x00000258
/* [0x25c]: REG tx payload reg56 */
#define MASTERFIP_REG_TX_PAYLD_REG56 0x0000025c
/* [0x260]: REG tx payload reg57 */
#define MASTERFIP_REG_TX_PAYLD_REG57 0x00000260
/* [0x264]: REG tx payload reg58 */
#define MASTERFIP_REG_TX_PAYLD_REG58 0x00000264
/* [0x268]: REG tx payload reg59 */
#define MASTERFIP_REG_TX_PAYLD_REG59 0x00000268
/* [0x26c]: REG tx payload reg60 */
#define MASTERFIP_REG_TX_PAYLD_REG60 0x0000026c
/* [0x270]: REG tx payload reg61 */
#define MASTERFIP_REG_TX_PAYLD_REG61 0x00000270
/* [0x274]: REG tx payload reg62 */
#define MASTERFIP_REG_TX_PAYLD_REG62 0x00000274
/* [0x278]: REG tx payload reg63 */
#define MASTERFIP_REG_TX_PAYLD_REG63 0x00000278
/* [0x27c]: REG tx payload reg64 */
#define MASTERFIP_REG_TX_PAYLD_REG64 0x0000027c
/* [0x280]: REG tx payload reg65 */
#define MASTERFIP_REG_TX_PAYLD_REG65 0x00000280
/* [0x284]: REG tx payload reg66 */
#define MASTERFIP_REG_TX_PAYLD_REG66 0x00000284
/* [0x288]: REG tx payload reg67 */
#define MASTERFIP_REG_TX_PAYLD_REG67 0x00000288
#endif
rtl/wbgen/masterfip_wbgen2_csr.html
View file @ c1d5c166
This source diff could not be displayed because it is too large. You can view the blob instead.
syn/spec/spec_masterfip_mt.par
View file @ c1d5c166
Release 14.7 par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
PCBE13457:: Fri Apr 21 14:14:01 2017
PCBE13457:: Fri Jun 30 10:32:04 2017
par -w -intstyle ise -ol high -xe n -mt off spec_masterfip_mt_map.ncd
spec_masterfip_mt.ncd spec_masterfip_mt.pcf
......@@ -20,8 +20,8 @@ WARNING:Security:44 - Since no license file was found,
please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
WARNING:Security:42 - Your license support version '2017.04' for ISE expires in 9 days after which you will not qualify
for Xilinx software updates or new releases.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
......@@ -36,16 +36,16 @@ Device speed data version: "PRODUCTION 1.23 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 12,635 out of 54,576 23%
Number used as Flip Flops: 12,633
Number of Slice Registers: 12,670 out of 54,576 23%
Number used as Flip Flops: 12,668
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 2
Number of Slice LUTs: 15,507 out of 27,288 56%
Number used as logic: 12,326 out of 27,288 45%
Number using O6 output only: 10,102
Number of Slice LUTs: 14,862 out of 27,288 54%
Number used as logic: 11,526 out of 27,288 42%
Number using O6 output only: 8,548
Number using O5 output only: 392
Number using O5 and O6: 1,832
Number using O5 and O6: 2,586
Number used as ROM: 0
Number used as Memory: 2,828 out of 6,408 44%
Number used as Dual Port RAM: 2,828
......@@ -54,18 +54,18 @@ Slice Logic Utilization:
Number using O5 and O6: 32
Number used as Single Port RAM: 0
Number used as Shift Register: 0
Number used exclusively as route-thrus: 353
Number with same-slice register load: 324
Number used exclusively as route-thrus: 508
Number with same-slice register load: 479
Number with same-slice carry load: 29
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 5,478 out of 6,822 80%
Number of occupied Slices: 5,110 out of 6,822 74%
Number of MUXCYs used: 1,452 out of 13,644 10%
Number of LUT Flip Flop pairs used: 19,132
Number with an unused Flip Flop: 7,564 out of 19,132 39%
Number with an unused LUT: 3,625 out of 19,132 18%
Number of fully used LUT-FF pairs: 7,943 out of 19,132 41%
Number of LUT Flip Flop pairs used: 18,225
Number with an unused Flip Flop: 7,491 out of 18,225 41%
Number with an unused LUT: 3,363 out of 18,225 18%
Number of fully used LUT-FF pairs: 7,371 out of 18,225 40%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
......@@ -125,7 +125,7 @@ Router effort level (-rl): High
INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx
Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis. REAL time: 18 secs
Finished initial Timing Analysis. REAL time: 19 secs
Finished initial Timing Analysis. REAL time: 18 secs
WARNING:Par:288 - The signal vc_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal vc_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
......@@ -136,113 +136,95 @@ WARNING:Par:288 - The signal fmc_prsnt_m2c_n_i_IBUF has no load. PAR will not a
WARNING:Par:288 - The signal l2p_rdy_i_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal l_wr_rdy_i<0>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal l_wr_rdy_i<1>_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem32_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem24_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem30_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem31_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem26_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem25_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem23_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem15_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem11_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem12_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem5_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem21_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem9_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem16_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem14_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem22_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem18_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem31_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem17_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem28_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem14_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem27_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem13_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem24_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem4_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem7_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem3_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem8_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem6_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem4_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem19_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem13_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem2_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem21_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem20_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem10_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem21_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem20_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem44_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem2_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem29_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem22_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem7_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem17_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem8_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem30_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem3_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem32_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem4_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem29_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem19_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem26_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem9_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem43_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem10_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem44_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem11_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem23_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem18_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem20_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem17_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem19_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem1_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem17_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem7_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem18_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem8_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem6_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem22_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem15_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem13_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem16_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem12_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem19_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem14_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem21_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem10_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem6_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem9_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem16_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem3_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem43_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem5_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem6_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem4_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem5_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem1_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem1_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem5_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem3_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem20_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem25_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem28_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem2_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem34_RAMB_DPO
has no load. PAR will not attempt to route this signal.
......@@ -256,36 +238,54 @@ WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_w
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem33_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem18_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem10_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem9_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem7_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem15_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_fifo_to_wb/U_Inferred_FIFO/Mram_mem27_RAMD_O
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem16_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem12_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem13_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem11_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem8_RAMD_O
has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_wbmaster32/cmp_from_wb_fifo/U_Inferred_FIFO/Mram_mem14_RAMD_O
has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 110750 unrouted; REAL time: 20 secs
Phase 1 : 104698 unrouted; REAL time: 20 secs
Phase 2 : 101929 unrouted; REAL time: 23 secs
Phase 2 : 95389 unrouted; REAL time: 23 secs
Phase 3 : 53093 unrouted; REAL time: 1 mins 7 secs
Phase 3 : 47329 unrouted; REAL time: 59 secs
Phase 4 : 54969 unrouted; (Setup:23, Hold:1029, Component Switching Limit:0) REAL time: 1 mins 28 secs
Phase 4 : 48234 unrouted; (Setup:0, Hold:6082, Component Switching Limit:0) REAL time: 1 mins 8 secs
Updating file: spec_masterfip_mt.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:20, Hold:940, Component Switching Limit:0) REAL time: 10 mins 31 secs
Phase 5 : 0 unrouted; (Setup:38, Hold:5903, Component Switching Limit:0) REAL time: 8 mins 8 secs
Phase 6 : 0 unrouted; (Setup:20, Hold:940, Component Switching Limit:0) REAL time: 11 mins 12 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:5903, Component Switching Limit:0) REAL time: 12 mins 2 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:940, Component Switching Limit:0) REAL time: 16 mins 29 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:5903, Component Switching Limit:0) REAL time: 12 mins 2 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:940, Component Switching Limit:0) REAL time: 16 mins 29 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:5903, Component Switching Limit:0) REAL time: 12 mins 2 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 16 mins 31 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 12 mins 4 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 16 mins 36 secs
Total REAL time to Router completion: 16 mins 36 secs
Total CPU time to Router completion: 16 mins 56 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 12 mins 9 secs
Total REAL time to Router completion: 12 mins 9 secs
Total CPU time to Router completion: 12 mins 21 secs
Partition Implementation Status
-------------------------------
......@@ -304,11 +304,11 @@ Generating Clock Report
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/clk_ | | | | | |
| sys | BUFGMUX_X2Y3| No | 4492 | 0.548 | 1.759 |
| sys | BUFGMUX_X2Y3| No | 4191 | 0.548 | 1.759 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/gen_ | | | | | |
|with_gennum.U_GN4124 | | | | | |
| _Core/sys_clk | BUFGMUX_X3Y13| No | 227 | 0.491 | 1.704 |
| _Core/sys_clk | BUFGMUX_X3Y13| No | 220 | 0.493 | 1.704 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_mock_turtle/gen_ | | | | | |
|with_gennum.U_GN4124 | | | | | |
......@@ -334,18 +334,18 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_gen_with_gennum_U_GN41 | SETUP | 0.032ns| 4.968ns| 0| 0
24_Core_cmp_clk_in_rx_pllout_x1 = | HOLD | 0.072ns| | 0| 0
TS_cmp_mock_turtle_pllout_clk_sys_0 = PER | SETUP | 0.030ns| 9.970ns| 0| 0
IOD TIMEGRP "cmp_mock_turtle_pllo | HOLD | 0.344ns| | 0| 0
ut_clk_sys_0" TS_clk_125m_pllref_n_i / 0. | | | | |
8 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_gen_with_gennum_U_GN41 | SETUP | 0.044ns| 4.956ns| 0| 0
24_Core_cmp_clk_in_rx_pllout_x1 = | HOLD | 0.070ns| | 0| 0
PERIOD TIMEGRP "cmp_mock_turtle_ | | | | |
gen_with_gennum_U_GN4124_Core_cmp_clk_in_ | | | | |
rx_pllout_x1" TS_cmp_mock_turtle_ | | | | |
gen_with_gennum_U_GN4124_Core_cmp_clk_in_ | | | | |
buf_P_clk PHASE 1.25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_pllout_clk_sys_0 = PER | SETUP | 0.035ns| 9.965ns| 0| 0
IOD TIMEGRP "cmp_mock_turtle_pllo | HOLD | 0.300ns| | 0| 0
ut_clk_sys_0" TS_clk_125m_pllref_n_i / 0. | | | | |
8 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_mock_turtle_gen_with_gennum_U_GN41 | MINLOWPULSE | 2.200ns| 2.800ns| 0| 0
24_Core_cmp_clk_in_buf_P_clk = PERIOD | | | | |
......@@ -401,8 +401,8 @@ Derived Constraints for TS_clk_125m_pllref_n_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk_125m_pllref_n_i | 8.000ns| 3.334ns| 7.972ns| 0| 0| 0| 4827236|
| TS_cmp_mock_turtle_pllout_clk_| 10.000ns| 9.965ns| N/A| 0| 0| 4827236| 0|
|TS_clk_125m_pllref_n_i | 8.000ns| 3.334ns| 7.976ns| 0| 0| 0| 4840975|
| TS_cmp_mock_turtle_pllout_clk_| 10.000ns| 9.970ns| N/A| 0| 0| 4840975| 0|
| sys_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
......@@ -412,15 +412,15 @@ Derived Constraints for TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_U_Node_Template_U_GN4124_Cor| 5.000ns| 0.925ns| 4.968ns| 0| 0| 0| 4827|
|TS_U_Node_Template_U_GN4124_Cor| 5.000ns| 0.925ns| 4.956ns| 0| 0| 0| 4827|
|e_cmp_clk_in_P_clk | | | | | | | |
| TS_cmp_mock_turtle_gen_with_ge| 5.000ns| 2.800ns| 4.968ns| 0| 0| 0| 4827|
| TS_cmp_mock_turtle_gen_with_ge| 5.000ns| 2.800ns| 4.956ns| 0| 0| 0| 4827|
| nnum_U_GN4124_Core_cmp_clk_in_| | | | | | | |
| buf_P_clk | | | | | | | |
| TS_cmp_mock_turtle_gen_with_g| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| ennum_U_GN4124_Core_cmp_clk_i| | | | | | | |
| n_rx_pllout_xs_int | | | | | | | |
| TS_cmp_mock_turtle_gen_with_g| 5.000ns| 4.968ns| N/A| 0| 0| 4827| 0|
| TS_cmp_mock_turtle_gen_with_g| 5.000ns| 4.956ns| N/A| 0| 0| 4827| 0|
| ennum_U_GN4124_Core_cmp_clk_i| | | | | | | |
| n_rx_pllout_x1 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
......@@ -439,10 +439,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 71 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 16 mins 42 secs
Total CPU time to PAR completion: 17 mins 2 secs
Total REAL time to PAR completion: 12 mins 15 secs
Total CPU time to PAR completion: 12 mins 27 secs
Peak Memory Usage: 936 MB
Peak Memory Usage: 906 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
syn/spec/spec_masterfip_mt.syr
View file @ c1d5c166
This source diff could not be displayed because it is too large. You can view the blob instead.
syn/spec/spec_masterfip_mt.twr
View file @ c1d5c166
This source diff could not be displayed because it is too large. You can view the blob instead.
syn/spec/spec_masterfip_mt.xise
View file @ c1d5c166
......@@ -871,10 +871,6 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../rtl/carrier_info.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
......
syn/spec/spec_masterfip_mt_map.mrp
View file @ c1d5c166
This source diff could not be displayed because it is too large. You can view the blob instead.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment