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MasterFIP - Gateware
Commit ceb6ff76 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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WRNC and masterFIP_core running at 100MHz instead of 40MHz

parent 4055ba8d
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Showing with 14 additions and 14 deletions
rtl/fmc_masterFIP_core.vhd
View file @ ceb6ff76
......@@ -502,7 +502,7 @@ begin
-- extension of the rx_fss_received_p so as to ensure capturing by the wrnc
cmp_rx_extend_p : gc_extend_pulse
generic map (
g_width => 16)
g_width => 32)
port map (
clk_i => clk_i,
rst_n_i => core_rst_n,
......@@ -512,7 +512,7 @@ begin
-- extension of the rx_frame_ok_p so as to ensure capturing by the wrnc
cmp_rx_frame_ok_extend_p : gc_extend_pulse
generic map (
g_width => 16)
g_width => 32)
port map (
clk_i => clk_i,
rst_n_i => core_rst_n,
......@@ -522,7 +522,7 @@ begin
-- extension of the rx_crc_wrong_p so as to ensure capturing by the wrnc
cmp_rx_crc_wrong_extend_p : gc_extend_pulse
generic map (
g_width => 16)
g_width => 32)
port map (
clk_i => clk_i,
rst_n_i => core_rst_n,
......@@ -619,7 +619,7 @@ begin
-- extension of the tx_completed_p so as to ensure capturing by the wrnc
cmp_tx_extend_p : gc_extend_pulse
generic map (
g_width => 16)
g_width => 32)
port map (
clk_i => clk_i,
rst_n_i => core_rst_n,
......
rtl/from_nanofip/wf_package.vhd
View file @ ceb6ff76
......@@ -66,7 +66,7 @@ package wf_package is
-- Constant regarding the user clock --
---------------------------------------------------------------------------------------------------
constant c_QUARTZ_PERIOD : real := 25.0;
constant c_QUARTZ_PERIOD : real := 10.0; ----------***-----25
......@@ -267,7 +267,7 @@ package wf_package is
-- Calculation of the number of uclk ticks equivalent to the reception/ transmission period
constant c_PERIODS_COUNTER_LGTH : natural := 11; -- in the slowest bit rate (31.25kbps), the
constant c_PERIODS_COUNTER_LGTH : natural := 13; -- in the slowest bit rate (31.25kbps), the -------***---------- 11
-- period is 32000 ns and can be measured after
-- 1280 uclk ticks. Therefore a counter of 11
-- bits is the max needed for counting
......
sim/spec/data_vectors/masterFIP_test.vec
View file @ ceb6ff76
......@@ -116,7 +116,7 @@ wr 0000000000030154 F 00000003
wait %d20
-- data bytes varid = 1403 for agent to send identification
wr 0000000000030158 F 00000314
wr 0000000000030158 F 00000306
wait %d20
-- tx_start
......
sim/spec/testbench/tb_masterFIP.vhd
View file @ ceb6ff76
......@@ -240,7 +240,7 @@ constant pll_clk_period : time:= 8 ns;
constant g_width : integer:= 32;
constant g_span : integer:= 32;
constant spec_clk_period : time:= 50 ns;
signal nanoFIP_clk_period : time:= 25 ns;
signal nanoFIP_clk_period : time:= 10 ns; -------***-------- 25
constant start_retrig_period : time:= 512 ns;
-- Number of Models receiving commands
......@@ -446,7 +446,7 @@ begin
wclk_i => nanoFIP_clk,
adr_i => (others => '0'),
cyc_i => '0',
dat_i => (others => '0'),
dat_i => consu_data,
rst_i => '0',
stb_i => '0',
we_i => '0',
......
syn/spec/spec_masterFIP.xise
View file @ ceb6ff76
......@@ -1132,8 +1132,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_masterFIP" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.tb_masterFIP" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_masterFIP/dut" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.spec_masterFIP" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -1151,7 +1151,7 @@
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.tb_masterFIP" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.spec_masterFIP" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
......
top/spec/spec_masterFIP.vhd
View file @ ceb6ff76
......@@ -281,7 +281,7 @@ begin
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 25, -- 40 MHz
CLKOUT0_DIVIDE => 10, -- 40 MHz ----***---- 25
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8, -- 125 MHz, not used
......
top/spec_wrnode/spec_top.vhd
View file @ ceb6ff76
......@@ -241,7 +241,7 @@ begin
g_with_wr_phy => false,
g_with_white_rabbit => false,
g_double_wrnode_core_clock => false,
g_system_clock_freq => 40000000,
g_system_clock_freq => 100000000, -------***-------
g_wr_node_config => c_node_config)
port map (
rst_n_sys_o => rst_n_sys,
......
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