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MasterFIP - Gateware
Commit d30c6031 authored by Evangelia Gousiou's avatar Evangelia Gousiou
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- corrected relays control(0: relay ON; Z: relay OFF instead of 0: relay ON; 1: relay OFF) 

- general code cleanup
parent 6921cd9e
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Showing with 961 additions and 794 deletions
rtl/fmc_masterFIP_core.vhd
View file @ d30c6031
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rtl/fmc_masterfip_csr.vhd
View file @ d30c6031
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rtl/masterFIP_pkg.vhd
View file @ d30c6031
......@@ -13,21 +13,13 @@
-- File masterFIP_pkg.vhd |
-- |
-- Description Definitions of constants, types, entities, functions |
-- Author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 11/01/2011 |
-- Version v0.05 |
-- Author Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 30/09/2015 |
-- Version v0.01 |
-- |
---------------- |
-- Last changes |
-- 8/2010 v0.01 EG byte_array of all vars cleaned_up (ex: subs_i removed) |
-- 10/2010 v0.02 EG base_addr unsigned(8 downto 0) instead of |
-- std_logic_vector (9 downto 0) to simplify calculations; cleaning-up |
-- 1/2011 v0.03 EG turnaround times & broadcast var (91h) updated following new specs |
-- added DualClkRam |
-- 2/2011 v0.04 EG function for manch_encoder; cleaning up of constants+generics |
-- added CTRL bytes for RP_DAT_MSG and RP_DAT_RQ and RP_DAT_RQ_MSG |
-- 2/2011 v0.05 EG JTAG variables added |
-- 11/2011 v0.06 EG c_SESSION_TIMEOUT_C_LGTH, c_JTAG_TIMEOUT_C_LGTH added |
-- 09/2015 v0.01 EG First version |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -188,11 +180,13 @@ package masterFIP_pkg is
mf_rstn_lock_o : out std_logic_vector(15 downto 0);
mf_rstn_lock_wr_o : out std_logic;
mf_dbg_o : out std_logic_vector(31 downto 0);
mf_adc_1v8_shdn_n_o : out std_logic;
mf_adc_m5v_shdn_n_o : out std_logic;
mf_adc_5v_en_n_o : out std_logic;
mf_adc_prim_conn_n_o : out std_logic;
mf_adc_sec_conn_n_o : out std_logic;
mf_adc_prim_conn_n_o : out std_logic;
mf_adc_sec_conn_n_o : out std_logic;
mf_ext_sync_term_en_o : out std_logic;
mf_ext_sync_dir_o : out std_logic;
......@@ -206,6 +200,7 @@ package masterFIP_pkg is
mf_macrocyc_lgth_o : out std_logic_vector(30 downto 0);
mf_macrocyc_start_o : out std_logic;
mf_macrocyc_num_cnt_i : in std_logic_vector(31 downto 0);
mf_turnar_lgth_o : out std_logic_vector(30 downto 0);
mf_turnar_start_o : out std_logic;
mf_silen_lgth_o : out std_logic_vector(30 downto 0);
......@@ -457,7 +452,7 @@ package masterFIP_pkg is
---------------------------------------------------------------------------------------------------
component masterfip_rx is
port (
clk_40m_i : in std_logic;
clk_i : in std_logic;
speed_i : in std_logic_vector (1 downto 0);
fd_rxd_a_i : in std_logic;
rst_i : in std_logic;
......@@ -478,7 +473,7 @@ package masterFIP_pkg is
---------------------------------------------------------------------------------------------------
component masterfip_tx is
port (
clk_40m_i : in std_logic;
clk_i : in std_logic;
speed_i : in std_logic_vector (1 downto 0);
rst_i : in std_logic;
tx_start_p_i : in std_logic;
......
rtl/masterfip_rx.vhd
View file @ d30c6031
......@@ -23,9 +23,10 @@
-- |
-- o bytes_c : for the counting of the retrieved bytes |
-- |
-- o create_32bit_words: for the formation of 32-bit words to be provided to the WRNC|
-- o create_32bit_words: for the formation of 32-bit words to be provided to the |
-- processor (Mock Turtle for example) |
-- |
-- WRNC |
-- Mock Turtle |
-- ___________________________________________________________ |
-- | | |
-- | _________ _______________________ | |
......@@ -94,13 +95,13 @@ use work.wf_package.all;
--=================================================================================================
entity masterfip_rx is port(
-- INPUTS
clk_40m_i : in std_logic; -- 40 MHZ clock
clk_i : in std_logic; -- 100 MHZ clock
rst_i : in std_logic; -- core rst, synched with clk_40m_i
rst_i : in std_logic; -- core rst, synched with clk_i
rx_rst_i : in std_logic; -- rx reset during production or
-- reset pulse from the WRNC when during
-- reception a frame is rejected
-- reset pulse from the processor (eg. MT)
-- when during reception a frame is rejected
-- (ex: RP_DAT > 133 bytes, wrong CTRL byte)
speed_i : in std_logic_vector(1 downto 0); -- WorldFIP bit rate
......@@ -123,7 +124,7 @@ entity masterfip_rx is port(
-- structure with 66 words of 32-bit each
-- this represents the max length of a frame
-- upon the rx_fss_crc_fes_ok_p_o only
-- rx_byte_index_o bytes have to be read by the WRNC
-- rx_byte_index_o bytes have to be read by the processor
rx_fss_crc_fes_ok_p_o : out std_logic; -- indication of a frame with
-- correct FSS, FES & CRC; pulse upon FES detection
......@@ -170,7 +171,7 @@ begin
cmp_rx_deglitcher: wf_rx_deglitcher
port map(
uclk_i => clk_40m_i,
uclk_i => clk_i,
nfip_rst_i => rst_i,
fd_rxd_a_i => fd_rxd_a_i,
-----------------------------------------------------------------
......@@ -183,7 +184,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_rx_deserializer: wf_rx_deserializer
port map(
uclk_i => clk_40m_i,
uclk_i => clk_i,
nfip_rst_i => rst_i,
rx_rst_i => rx_rst_i,
fd_rxd_f_edge_p_i => s_fd_rxd_filt_f_edge_p,
......@@ -208,7 +209,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_rx_osc: wf_rx_osc
port map(
uclk_i => clk_40m_i,
uclk_i => clk_i,
rate_i => speed_i,
nfip_rst_i => rst_i,
fd_rxd_edge_p_i => s_rxd_filt_edge_p,
......@@ -227,7 +228,7 @@ begin
cmp_rx_bytes_cnt: wf_incr_counter
generic map(g_counter_lgth => 9)
port map(
uclk_i => clk_40m_i,
uclk_i => clk_i,
counter_reinit_i => bytes_c_rst,
counter_incr_i => rx_byte_ready_p,
counter_is_full_o => open,
......@@ -241,9 +242,9 @@ begin
---------------------------------------------------------------------------------------------------
-- combination of four retrieved bytes to a 32-bit word --
---------------------------------------------------------------------------------------------------
create_32bit_words: process (clk_40m_i)
create_32bit_words: process (clk_i)
begin
if rising_edge (clk_40m_i) then
if rising_edge (clk_i) then
if rst_i = '1' or rx_rst_i = '1' then
byte0 <= (others => '0');
byte1 <= (others => '0');
......@@ -272,9 +273,9 @@ begin
---------------------------------------------------------------------------------------------------
-- transfer 32bit words to the cons_frame registers
delay: process (clk_40m_i)
delay: process (clk_i)
begin
if rising_edge (clk_40m_i) then
if rising_edge (clk_i) then
if rst_i = '1' or rx_rst_i = '1' then
rx_byte_index_d1 <= (others =>'0'); -- needed for synching
else
......@@ -286,9 +287,9 @@ begin
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
data_transfer_to_regs: process (clk_40m_i)
data_transfer_to_regs: process (clk_i)
begin
if rising_edge (clk_40m_i) then
if rising_edge (clk_i) then
if rst_i = '1' or rx_rst_i = '1' then
word32_num <= 0;
rx_frame_o <= (others =>(others =>'0'));
......
rtl/masterfip_tx.vhd
View file @ d30c6031
......@@ -15,20 +15,21 @@
-- Description The unit groups the main actions that regard FIELDRIVE data transmission. |
-- It instantiates the units/processes: |
-- |
-- o wf_tx_serializer: that receives bytes from the WRNC trough the tx_frame , |
-- structure, encodes them (Manchester 2), adds the FSS, FCS, FES|
-- fields and puts one by one bits to the FIELDRIVE output FD_TXD|
-- following the synchronization signals from the wf_tx_osc unit.|
-- o wf_tx_serializer: that receives bytes from the processor (Mock Turtle for |
-- example) trough the tx_frame structure, encodes them |
-- (Manchester 2), adds the FSS, FCS, FES fields and puts one by |
-- one bits to the FIELDRIVE output FD_TXD following the |
-- synchronization signals from the wf_tx_osc unit. |
-- Also generates the output FD_TXENA. |
-- |
-- o wf_tx_osc : that generates the output FD_TXCK and the array of pulses |
-- tx_sched_p_buff, used for the synchronization of the |
-- wf_tx_serializer's actions. |
-- |
-- o data_retrieval : that copies the bytes provided by the WRNC upon the activation|
-- of the signal tx_start |
-- o data_retrieval : that copies the bytes provided by the processor upon the |
-- activation of the signal tx_start. |
-- |
-- WRNC |
-- Mock Turtle |
-- ___________________________________________________________ |
-- | _______________________________ | |
-- | | | | |
......@@ -96,9 +97,9 @@ use work.wf_package.all;
entity masterfip_tx is port(
-- INPUTS
clk_40m_i : in std_logic; -- 40 MHz clock
clk_i : in std_logic; -- 100 MHz clock
rst_i : in std_logic; -- core rst, synched with clk_40m_i
rst_i : in std_logic; -- core rst, synched with clk_i
speed_i : in std_logic_vector(1 downto 0); -- WorldFIP bit rate
......@@ -166,9 +167,9 @@ begin
-- All the frame bytes are copied to local registers; like this the frame data remain stable
-- until the next tx_start_p_i arrives.
data_retrieval: process (clk_40m_i)
data_retrieval: process (clk_i)
begin
if rising_edge (clk_40m_i) then
if rising_edge (clk_i) then
if rst_i = '1' then
prod_frame <= ((others => (others=>'0')));
ctrl_byte <= (others=>'0');
......@@ -188,9 +189,9 @@ begin
-- Mux to select the right byte --
---------------------------------------------------------------------------------------------------
-- The process retrieves sequentially one by one the byte to be sent to the serializer.
select_byte: process (clk_40m_i)
select_byte: process (clk_i)
begin
if rising_edge (clk_40m_i) then
if rising_edge (clk_i) then
if rst_i = '1' then
word32_num <= 0;
else
......@@ -207,7 +208,7 @@ begin
cmp_tx_bytes_cnt: wf_incr_counter
generic map(g_counter_lgth => 9)
port map(
uclk_i => clk_40m_i,
uclk_i => clk_i,
counter_reinit_i => tx_start_p_i,
counter_incr_i => tx_byte_request_p,
counter_is_full_o => open,
......@@ -231,7 +232,7 @@ begin
cmp_tx_serializer: wf_tx_serializer
port map(
uclk_i => clk_40m_i,
uclk_i => clk_i,
nfip_rst_i => rst_i,
byte_i => tx_byte,
tx_start_p_i => tx_start_p_i,
......@@ -249,7 +250,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
cmp_tx_osc: wf_tx_osc
port map(
uclk_i => clk_40m_i,
uclk_i => clk_i,
rate_i => speed_i,
nfip_rst_i => rst_i,
tx_osc_rst_p_i => s_tx_osc_rst_p,
......@@ -267,9 +268,9 @@ begin
prod_data_lgth_match <= '1' when prod_bytes_c = unsigned(bytes_num) else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
synch_signals: process (clk_40m_i)
synch_signals: process (clk_i)
begin
if rising_edge (clk_40m_i) then
if rising_edge (clk_i) then
if rst_i = '1' then
last_data_byte_p <= '0'; -- indication of the last data byte (CRC, FES not included)
last_data_byte_p_d <= '0';
......
rtl/wbgen/fmc_masterfip_csr.wb
View file @ d30c6031
......@@ -62,6 +62,23 @@ peripheral {
};
};
-------------------------------------------------------------------------------
-- debugging --
-------------------------------------------------------------------------------
reg {
name = "dbg";
description = "for debugging purpuses";
prefix = "dbg";
field {
name = "debugging";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-------------------------------------------------------------------------------
-- ADC power supplies --
......@@ -318,7 +335,21 @@ peripheral {
};
};
reg {
name = "macrocycles number cnt";
prefix = "macrocyc_num_cnt";
field {
name = "number of macrocycles";
description = "current amount of macrocycles";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "turnaround time cnt";
prefix = "turnar_time_cnt";
......
sim/spec/data_vectors/masterFIP_test.vec
View file @ d30c6031
......@@ -60,115 +60,115 @@ wait %d20
--------------- ID_DAT ---------------
-- tx_rst
wr 0000000000030034 F 00000001
wr 000000000003003C F 00000001
wait %d10
wr 0000000000030034 F 00000000
wr 000000000003003C F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000030154 F 00000003
wr 000000000003015C F 00000003
wait %d20
-- data bytes varid = 0503 for agent to consume
wr 0000000000030158 F 00000305
wr 0000000000030160 F 00000305
wait %d20
-- tx_start
wr 0000000000030034 F 00000202
wr 000000000003003C F 00000202
wait %d20000
--------------- RP_DAT ---------------
-- tx_rst
wr 0000000000030034 F 00000001
wr 000000000003003C F 00000001
wait %d10
wr 0000000000030034 F 00000000
wr 000000000003003C F 00000000
wait %d20
-- control byte of rp_dat
wr 0000000000030154 F 00000002
wr 000000000003015C F 00000002
wait %d20
-- data bytes
wr 0000000000030158 F BBAA0340 -- for 2 data bytes: BBAA0340 | for 8 data bytes: BBAA0940
wr 0000000000030160 F BBAA0340 -- for 2 data bytes: BBAA0340 | for 8 data bytes: BBAA0940
wait %d20
wr 000000000003015c F EEDDCC05 -- for 2 data bytes: EEDDCC05 | for 8 data bytes: FFEEDDCC
-- tx_start
wr 0000000000030034 F 00000502 -- for 2 data bytes: 00000502 | for 8 data bytes: 00000B02
wr 000000000003003C F 00000502 -- for 2 data bytes: 00000502 | for 8 data bytes: 00000B02
wait %d40000
--------------- ID_DAT ---------------
-- tx_rst
wr 0000000000030034 F 00000001
wr 000000000003003C F 00000001
wait %d10
wr 0000000000030034 F 00000000
wr 000000000003003C F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000030154 F 00000003
wr 000000000003015C F 00000003
wait %d20
-- data bytes varid = 1403 for agent to send identification
wr 0000000000030158 F 00000314
wr 0000000000030160 F 00000314
wait %d20
-- tx_start
wr 0000000000030034 F 00000202
wr 000000000003003C F 00000202
wait %d20
-- deactivate tx_start
wr 0000000000030034 F 00000000
wr 000000000003003C F 00000000
-- release rx_rst
wr 0000000000030040 F 00000000
wr 0000000000030048 F 00000000
wait %d40000
-- read received data
rd 0000000000030048 F 00000002
rd 0000000000030050 F 00000002
wait %d20
rd 000000000003004c F 03800550
wait %d40000
--------------- ID_DAT ---------------
tx_rst
wr 0000000000030034 F 00000001
wr 000000000003003C F 00000001
wait %d10
wr 0000000000030034 F 00000000
wr 000000000003003C F 00000000
wait %d20
-- control byte of id_dat
wr 0000000000030154 F 00000003
wr 000000000003015C F 00000003
wait %d20
-- data bytes varid = 0603 for agent to produce
wr 0000000000030158 F 00000306
wr 0000000000030160 F 00000306
wait %d20
-- tx_start
wr 0000000000030034 F 00000202
wr 000000000003003C F 00000202
wait %d20
-- deactivate tx_start
wr 0000000000030034 F 00000000
wr 000000000003003C F 00000000
-- release rx_rst
wr 0000000000030040 F 00000000
wr 0000000000030048 F 00000000
wait %d40000
-- read received data
rd 0000000000030048 F 00000000 FFFFFFFF -- XXXXXX02 FFFFFFFF
rd 0000000000030050 F 00000000 FFFFFFFF -- XXXXXX02 FFFFFFFF
wait %d20
rd 000000000003004c F 00000000 FFFFFFFF -- BC870940 FFFFFFFF
rd 0000000000030054 F 00000000 FFFFFFFF -- BC870940 FFFFFFFF
wait %d20
rd 0000000000030050 F 00000000 FFFFFFFF -- B07D75EF FFFFFFFF
rd 0000000000030058 F 00000000 FFFFFFFF -- B07D75EF FFFFFFFF
wait %d20
rd 0000000000030054 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 000000000003005C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030058 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000030060 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 000000000003005C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
rd 0000000000030064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
......@@ -236,13 +236,13 @@ wait %d40000
--------------- RP_FIN ---------------
-- control byte of rp_fin
wr 0000000000030154 F 00000040
wr 000000000003015C F 00000040
wait %d20
-- rx_rst
wr 0000000000030040 F 00000001
wr 0000000000030048 F 00000001
wait %d20
-- tx_start
wr 0000000000030034 F 00000002
wr 000000000003003C F 00000002
wait %d20000
\ No newline at end of file
syn/spec/spec_masterFIP.xise
View file @ d30c6031
This diff is collapsed.
syn/spec_wrnode/spec_masterfip_wrnode.xise
View file @ d30c6031
......@@ -863,9 +863,6 @@
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/etherbone-core/hdl/eb_master_core/eb_record_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="124"/>
</file>
<file xil_pn:name="../../top/spec_wrnode/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
......@@ -1313,6 +1310,10 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="389"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../top/spec_wrnode/synthesis_descriptor.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="391"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/wr-node-core/hdl/ip_cores/gn4124-core/hdl/spec/ip_cores/fifo_32x512.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
......
top/spec/spec_masterFIP.ucf
View file @ d30c6031
......@@ -20,10 +20,6 @@ TIMESPEC TS_p2l_clk_n_i = PERIOD "p2l_clk_n_i" 5 ns HIGH 50%;
#----------------------------------------
# FMC slot
#----------------------------------------
# <ucfgen_start>
# This section has bee generated automatically by ucfgen.py. Do not hand-modify if not really necessary.
# ucfgen pin assignments for mezzanine fmc-tdc-v3 slot 0
NET "fd_rstn_o" LOC = "Y18";
NET "fd_rstn_o" IOSTANDARD = "LVCMOS25";
......@@ -54,7 +50,6 @@ NET "speed_b0_i" IOSTANDARD = "LVCMOS25";
NET "speed_b1_i" LOC = AB5;
NET "speed_b1_i" IOSTANDARD = "LVCMOS25";
NET "led_tx_err_n_o" LOC = C19;
NET "led_tx_err_n_o" IOSTANDARD = "LVCMOS25";
......@@ -102,7 +97,6 @@ NET "adc_sec_conn_n_o" IOSTANDARD = "LVCMOS25";
#NET "mezz_onewire_b" LOC = "A19";
#NET "mezz_onewire_b" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
#NET "mezz_sys_scl_b" LOC = "F7";
#NET "mezz_sys_scl_b" IOSTANDARD = "LVCMOS25";
#NET "mezz_sys_sda_b" LOC = "F8";
......
top/spec/spec_masterFIP.vhd
View file @ d30c6031
This diff is collapsed.
top/spec/synthesis_descriptor.vhd
View file @ d30c6031
......@@ -42,16 +42,16 @@ package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "masterFIP_tdc ",
syn_module_name => "spec_masterFIP ",
syn_commit_id => "00000000000000000000000000000000",
syn_tool_name => "ISE ",
syn_tool_version => x"00000134",
syn_date => x"20140731",
syn_tool_version => x"00000147",
syn_date => x"20160128",
syn_username => "egousiou ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "http://svn.ohwr.org/masterFIP "
repo_url => "http://svn.ohwr.org/projects/masterFIP "
);
end package synthesis_descriptor;
top/spec_wrnode/spec_top.vhd
View file @ d30c6031
......@@ -376,14 +376,14 @@ begin
end if;
end process;
-- -- -- -- -- --
led_tx_err_n_o <= led_clk_40m_aux(0);
led_tx_act_n_o <= aux(3);
--led_tx_err_n_o <= aux(5);
led_rx_err_n_o <= aux(2);
led_rx_act_n_o <= aux(6);
led_out_of_sync_n_o <= aux(7);
led_sync_n_o <= aux(0);
-- led_tx_err_n_o <= led_clk_40m_aux(0);
led_tx_act_n_o <= aux(0); -- R5
led_tx_err_n_o <= aux(1); -- R8
led_rx_act_n_o <= aux(2); -- R6
led_rx_err_n_o <= aux(3); -- R9
led_out_of_sync_n_o <= aux(4); -- R7
led_sync_n_o <= aux(5); -- R2
......
top/spec_wrnode/synthesis_descriptor.vhd
View file @ d30c6031
-------------------------------------------------------------------------------
-- Title : Fine Delay FMC SVEC (Simple VME FMC Carrier) SDB descriptor
-- Project : Fine Delay FMC (fmc-delay-1ns-4cha)
-- Title : TDC FMC SPEC (Simple VME FMC Carrier) SDB descriptor
-- Project : TDC FMC (fmc-tdc-1ns-5cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Tomasz Wlostowski
-- Author : Evangelia Gousiou
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2014-03-18
-- Last update: 2013-04-16
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SVEC carrier.
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
......@@ -42,16 +42,16 @@ package synthesis_descriptor is
constant c_sdb_synthesis_info : t_sdb_synthesis :=
(
syn_module_name => "spec-wrnode-demo",
syn_module_name => "masterFIP_MT ",
syn_commit_id => "00000000000000000000000000000000",
syn_tool_name => "ISE ",
syn_tool_version => x"00000147",
syn_date => x"20150327",
syn_username => "twlostow ");
syn_date => x"20160128",
syn_username => "egousiou ");
constant c_sdb_repo_url : t_sdb_repo_url :=
(
repo_url => "git://ohwr.org/wr-node-core "
repo_url => "http://svn.ohwr.org/projects/masterFIP "
);
end package synthesis_descriptor;
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