corrected core_rst_n that was used instead of core_rst for the counting of the…

corrected core_rst_n that was used instead of core_rst for the counting of the number of macrocycles and the counting of crc errors

corrected core_rst_n that was used instead of core_rst for the counting of the…
corrected core_rst_n that was used instead of core_rst for the counting of the number of macrocycles and the counting of crc errors
dda9a212 · Evangelia Gousiou · 590336a8 · dda9a212 · dda9a212 · dda9a212
Commit dda9a212 authored Jul 25, 2017 by Evangelia Gousiou
6 changed files
--- a/rtl/fmc_masterFIP_core.vhd
+++ b/rtl/fmc_masterFIP_core.vhd
@@ -422,7 +422,7 @@ begin
  -- counter counting the number of macrocycles;
  -- being a 32-bit counter, for the fastest application of 20 ms macrocycle, the counter can
  -- keep counting for 2.7 years; when it fills up it would restart from 0.
-  cmp_macrocycles_cnt:incr_counter
+  cmp_macrocycles_cnt: incr_counter
  generic map(g_counter_lgth => g_width)
  port map
    (clk_i             => clk_i,
@@ -560,12 +560,12 @@ begin

  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  -
  -- counter of frames with crc errors since the startup or a core reset (not on every macrocycle)
-  cmp_rx_crc_err_cnt:incr_counter
+  cmp_rx_crc_err_cnt: incr_counter
  generic map(g_counter_lgth => 32)
  port map
    (clk_i            => clk_i,
     counter_incr_i   => rx_crc_wrong_p,
-     counter_reinit_i => core_rst_n,
+     counter_reinit_i => core_rst,
     counter_o        => reg_to_mt.rx_stat_crc_err_cnt_i);



--- a/syn/spec/spec_masterfip_mt.par
+++ b/syn/spec/spec_masterfip_mt.par
--- a/syn/spec/spec_masterfip_mt.syr
+++ b/syn/spec/spec_masterfip_mt.syr
--- a/syn/spec/spec_masterfip_mt.twr
+++ b/syn/spec/spec_masterfip_mt.twr
--- a/syn/spec/spec_masterfip_mt.xise
+++ b/syn/spec/spec_masterfip_mt.xise
@@ -20,8 +20,6 @@
    <!-- project is analyzed based on files automatically identified as       -->
    <!-- include files.                                                       -->
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" xil_pn:type="FILE_VERILOG"/>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" xil_pn:type=""/>
-    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" xil_pn:type=""/>
    <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_functions.v" xil_pn:type="FILE_VERILOG"/>
  </autoManagedFiles>


--- a/syn/spec/spec_masterfip_mt_map.mrp
+++ b/syn/spec/spec_masterfip_mt_map.mrp