masterFIP gateware
Overview
Following the evaluation of different implementation solutions, the technical choice for the design was the use of Mock Turtle (also referred to as White Rabbit Node Core).
Mock Turtle is a HDL core of a generic distributed control system node,
based on multiple deterministic CPU cores where the users can run
any sort of hard real time applications.
The applications can be written in bare metal C, using standard GNU
tool set, cross-compiled and loaded into the CPUs. The CPUs can
communicate between each other through
a dedicated Shared Memory and with the host through Host Message
Queues.The following figure illustrates the SPEC FPGA gateware
architecture,
spec_masterfip_mt.
Overview of the gateware architecture of the fmc-worldfip on a SPEC
carrier*
The top entity consists of two main blocks: the
spec_node_template*, which is the Mock Turtle top level for SPEC,
and the application-specific fmc-masterFIP_core.
The communication between the two modules is through wishbone.
On one side (red arrows) the fmc_masterfip_core is the interface to
the FMC hardware i.e. FielDrive chip, external pulse LEMO, 1-wire
DS18B20 chip, LEDs.
On the other side (blue line) it provides a set of
wbgen2 -generated
control and status registers, to interface through wishbone with the
Mock Turtle.
The fmc_masterfip_core core ignores the notion of the WorldFIP frame
type (ID_DAT/RT_DAT/..etc), or the macrocycle sequence and macrocycle
timing; the sw running on the
Mock Turtle CPUs is responsible for managing these aspects and for
providing to this core all the payload bytes (coming from the host) that
have to be serializedand or
for enabling the deserializer and then providing to the host the
deserialized bytes.
Supported carriers
- SPEC PCIe 1-FMC-slot carrier
SPEC FPGA XC6SLX45T resource utilization metrics
- Number of Slice LUTs: 57%
- Number of RAMB16BWERs: 75%
- Number of RAMB8BWERs: 9%
- Number of bonded IOBs: 31%
Folder structure
- rtl: FMC-masterFIP core
- ip_cores: general-cores
- sim: simulation testbench
- syn: Xilinx ISE project
- top/spec: SPEC carrier top level
Git sub-modules
- nanoFIP-core: hdl/ip_cores/nano-fip
- gn4124-core: hdl/ip_cores/gn4124-core
- wr-node-core: hdl/ip_cores/wr-cores
- general-cores: hdl/ip_cores/general-cores
- wr-cores: hdl/ip_cores/wr-cores
- etherbone-core: hdl/ip_cores/etherbone-core
Project info
- masterFIP functional specification
- masterFIP design guide:
- masterFIP core wbgen2 register map
- Mock Turtle project
Project Status
Date | Event |
12-2014 | HDL technical choice, pdf |
01-2015 | Start working on HDL specification |
07-2015 | One board tested that sent and received WorldFIP data. ADC not tested. |
07-2016 | Long runs with Cryo lab equipment run smoothly |
09-2016 | Successful migration of the RadMon application |
02-2017 | Stable gateware version |
03-2017 | Section-wide gateware review: review intro, review outcome |
Contacts
Eva Gousiou - CERN | Tomasz Wlostowski - CERN
Eva Gousiou - 28 Feb 2017