#  Register definitions for slave core: FMC masterFIP PTS registers
#
#  * File           : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_pts_csr.py
#  * Author         : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
#  * Created        : Mon Apr  3 13:15:24 2017
#
#    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
#    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
#

addr = {
    
    'rst' : [ 0x0, 0xffffffff, "w"],
    
    'ext_sync' : [ 0x1, 0xffffffff, "rw"],
        'ext_sync.term_en' : [ 0x1, 0x1, "rw"], 
        'ext_sync.dir' : [ 0x1, 0x2, "rw"], 
        'ext_sync.oe' : [ 0x1, 0x4, "rw"], 
        'ext_sync.output_value' : [ 0x1, 0x8, "rw"], 
        'ext_sync.fpga_io_dir' : [ 0x1, 0x10, "rw"], 
        'ext_sync.raw_input' : [ 0x1, 0x20, "rw"], 
    
    'tx_corrupt' : [ 0x2, 0xffffffff, "rw"],
    
    'fd' : [ 0x3, 0xffffffff, "r"],
        'fd.wdgn' : [ 0x3, 0x1, "r"], 
        'fd.wdgn_latch' : [ 0x3, 0x2, "r"], 
        'fd.cd_n' : [ 0x3, 0x4, "r"], 
        'fd.txer' : [ 0x3, 0x8, "r"], 
    
    'fd_rxcdn_cnt' : [ 0x4, 0xffffffff, "r"],
    
    'fd_txerr_cnt' : [ 0x5, 0xffffffff, "r"],
    '':[0,0]
}
