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-- Title          : Wishbone slave core for FMC masterFIP PTS registers
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-- File           : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.vhd
-- Author         : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
-- Created        : Mon Apr  3 13:15:24 2017
-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity masterfip_pts_csr is
    port (
        rst_n_i                                  : in     std_logic;
        clk_sys_i                                : in     std_logic;
        wb_adr_i                                 : in     std_logic_vector(2 downto 0);
        wb_dat_i                                 : in     std_logic_vector(31 downto 0);
        wb_dat_o                                 : out    std_logic_vector(31 downto 0);
        wb_cyc_i                                 : in     std_logic;
        wb_sel_i                                 : in     std_logic_vector(3 downto 0);
        wb_stb_i                                 : in     std_logic;
        wb_we_i                                  : in     std_logic;
        wb_ack_o                                 : out    std_logic;
        wb_stall_o                               : out    std_logic;
-- Port for MONOSTABLE field: 'reset of the masterFIP core' in reg: 'rst'
        mfpts_rst_core_o                         : out    std_logic;
-- Port for BIT field: 'termination enable' in reg: 'ext sync'
        mfpts_ext_sync_term_en_o                 : out    std_logic;
-- Port for BIT field: 'transceiver direction' in reg: 'ext sync'
        mfpts_ext_sync_dir_o                     : out    std_logic;
-- Port for BIT field: 'transceiver output enable' in reg: 'ext sync'
        mfpts_ext_sync_oe_o                      : out    std_logic;
-- Port for BIT field: 'External sync output value (when buffer is switched)' in reg: 'ext sync'
        mfpts_ext_sync_output_value_o            : out    std_logic;
-- Port for BIT field: 'FPGA IO direction' in reg: 'ext sync'
        mfpts_ext_sync_fpga_io_dir_o             : out    std_logic;
-- Port for BIT field: 'raw_input' in reg: 'ext sync'
        mfpts_ext_sync_raw_input_i               : in     std_logic;
-- Port for BIT field: 'enable' in reg: 'PTS options'
        mfpts_tx_corrupt_enable_o                : out    std_logic;
-- Port for BIT field: 'fd watchdog' in reg: 'fieldrive status'
        mfpts_fd_wdgn_i                          : in     std_logic;
-- Port for BIT field: 'fd watchdog latched' in reg: 'fieldrive status'
        mfpts_fd_wdgn_latch_i                    : in     std_logic;
-- Port for BIT field: 'fd carrier detect' in reg: 'fieldrive status'
        mfpts_fd_cd_n_i                          : in     std_logic;
-- Port for BIT field: 'fd transmitter error' in reg: 'fieldrive status'
        mfpts_fd_txer_i                          : in     std_logic;
-- Port for std_logic_vector field: 'fieldrive rx not carrier detect  counter' in reg: 'fieldrive rx not carrier detect  counter'
        mfpts_fd_rxcdn_cnt_i                     : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'fieldrive tx error counter' in reg: 'fieldrive tx error counter'
        mfpts_fd_txerr_cnt_i                     : in     std_logic_vector(31 downto 0)
    );
end masterfip_pts_csr;

architecture syn of masterfip_pts_csr is

signal mfpts_rst_core_dly0                      : std_logic      ;
signal mfpts_rst_core_int                       : std_logic      ;
signal mfpts_ext_sync_term_en_int               : std_logic      ;
signal mfpts_ext_sync_dir_int                   : std_logic      ;
signal mfpts_ext_sync_oe_int                    : std_logic      ;
signal mfpts_ext_sync_output_value_int          : std_logic      ;
signal mfpts_ext_sync_fpga_io_dir_int           : std_logic      ;
signal mfpts_tx_corrupt_enable_int              : std_logic      ;
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(2 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
    wrdata_reg <= wb_dat_i;
    bwsel_reg <= wb_sel_i;
    rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
    wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
    allones <= (others => '1');
    allzeros <= (others => '0');
-- 
-- Main register bank access process.
    process (clk_sys_i, rst_n_i)
    begin
        if (rst_n_i = '0') then 
            ack_sreg <= "0000000000";
            ack_in_progress <= '0';
            rddata_reg <= "00000000000000000000000000000000";
            mfpts_rst_core_int <= '0';
            mfpts_ext_sync_term_en_int <= '0';
            mfpts_ext_sync_dir_int <= '0';
            mfpts_ext_sync_oe_int <= '0';
            mfpts_ext_sync_output_value_int <= '0';
            mfpts_ext_sync_fpga_io_dir_int <= '0';
            mfpts_tx_corrupt_enable_int <= '0';
        elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
            ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
            ack_sreg(9) <= '0';
            if (ack_in_progress = '1') then
                if (ack_sreg(0) = '1') then
                    mfpts_rst_core_int <= '0';
                    ack_in_progress <= '0';
                else
                end if;
            else
                if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
                    case rwaddr_reg(2 downto 0) is
                    when "000" => 
                        if (wb_we_i = '1') then
                            mfpts_rst_core_int <= wrdata_reg(0);
                        end if;
                        rddata_reg(0) <= '0';
                        rddata_reg(0) <= 'X';
                        rddata_reg(1) <= 'X';
                        rddata_reg(2) <= 'X';
                        rddata_reg(3) <= 'X';
                        rddata_reg(4) <= 'X';
                        rddata_reg(5) <= 'X';
                        rddata_reg(6) <= 'X';
                        rddata_reg(7) <= 'X';
                        rddata_reg(8) <= 'X';
                        rddata_reg(9) <= 'X';
                        rddata_reg(10) <= 'X';
                        rddata_reg(11) <= 'X';
                        rddata_reg(12) <= 'X';
                        rddata_reg(13) <= 'X';
                        rddata_reg(14) <= 'X';
                        rddata_reg(15) <= 'X';
                        rddata_reg(16) <= 'X';
                        rddata_reg(17) <= 'X';
                        rddata_reg(18) <= 'X';
                        rddata_reg(19) <= 'X';
                        rddata_reg(20) <= 'X';
                        rddata_reg(21) <= 'X';
                        rddata_reg(22) <= 'X';
                        rddata_reg(23) <= 'X';
                        rddata_reg(24) <= 'X';
                        rddata_reg(25) <= 'X';
                        rddata_reg(26) <= 'X';
                        rddata_reg(27) <= 'X';
                        rddata_reg(28) <= 'X';
                        rddata_reg(29) <= 'X';
                        rddata_reg(30) <= 'X';
                        rddata_reg(31) <= 'X';
                        ack_sreg(2) <= '1';
                        ack_in_progress <= '1';
                    when "001" => 
                        if (wb_we_i = '1') then
                            mfpts_ext_sync_term_en_int <= wrdata_reg(0);
                            mfpts_ext_sync_dir_int <= wrdata_reg(1);
                            mfpts_ext_sync_oe_int <= wrdata_reg(2);
                            mfpts_ext_sync_output_value_int <= wrdata_reg(3);
                            mfpts_ext_sync_fpga_io_dir_int <= wrdata_reg(4);
                        end if;
                        rddata_reg(0) <= mfpts_ext_sync_term_en_int;
                        rddata_reg(1) <= mfpts_ext_sync_dir_int;
                        rddata_reg(2) <= mfpts_ext_sync_oe_int;
                        rddata_reg(3) <= mfpts_ext_sync_output_value_int;
                        rddata_reg(4) <= mfpts_ext_sync_fpga_io_dir_int;
                        rddata_reg(5) <= mfpts_ext_sync_raw_input_i;
                        rddata_reg(6) <= 'X';
                        rddata_reg(7) <= 'X';
                        rddata_reg(8) <= 'X';
                        rddata_reg(9) <= 'X';
                        rddata_reg(10) <= 'X';
                        rddata_reg(11) <= 'X';
                        rddata_reg(12) <= 'X';
                        rddata_reg(13) <= 'X';
                        rddata_reg(14) <= 'X';
                        rddata_reg(15) <= 'X';
                        rddata_reg(16) <= 'X';
                        rddata_reg(17) <= 'X';
                        rddata_reg(18) <= 'X';
                        rddata_reg(19) <= 'X';
                        rddata_reg(20) <= 'X';
                        rddata_reg(21) <= 'X';
                        rddata_reg(22) <= 'X';
                        rddata_reg(23) <= 'X';
                        rddata_reg(24) <= 'X';
                        rddata_reg(25) <= 'X';
                        rddata_reg(26) <= 'X';
                        rddata_reg(27) <= 'X';
                        rddata_reg(28) <= 'X';
                        rddata_reg(29) <= 'X';
                        rddata_reg(30) <= 'X';
                        rddata_reg(31) <= 'X';
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "010" => 
                        if (wb_we_i = '1') then
                            mfpts_tx_corrupt_enable_int <= wrdata_reg(0);
                        end if;
                        rddata_reg(0) <= mfpts_tx_corrupt_enable_int;
                        rddata_reg(1) <= 'X';
                        rddata_reg(2) <= 'X';
                        rddata_reg(3) <= 'X';
                        rddata_reg(4) <= 'X';
                        rddata_reg(5) <= 'X';
                        rddata_reg(6) <= 'X';
                        rddata_reg(7) <= 'X';
                        rddata_reg(8) <= 'X';
                        rddata_reg(9) <= 'X';
                        rddata_reg(10) <= 'X';
                        rddata_reg(11) <= 'X';
                        rddata_reg(12) <= 'X';
                        rddata_reg(13) <= 'X';
                        rddata_reg(14) <= 'X';
                        rddata_reg(15) <= 'X';
                        rddata_reg(16) <= 'X';
                        rddata_reg(17) <= 'X';
                        rddata_reg(18) <= 'X';
                        rddata_reg(19) <= 'X';
                        rddata_reg(20) <= 'X';
                        rddata_reg(21) <= 'X';
                        rddata_reg(22) <= 'X';
                        rddata_reg(23) <= 'X';
                        rddata_reg(24) <= 'X';
                        rddata_reg(25) <= 'X';
                        rddata_reg(26) <= 'X';
                        rddata_reg(27) <= 'X';
                        rddata_reg(28) <= 'X';
                        rddata_reg(29) <= 'X';
                        rddata_reg(30) <= 'X';
                        rddata_reg(31) <= 'X';
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "011" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(0) <= mfpts_fd_wdgn_i;
                        rddata_reg(1) <= mfpts_fd_wdgn_latch_i;
                        rddata_reg(2) <= mfpts_fd_cd_n_i;
                        rddata_reg(3) <= mfpts_fd_txer_i;
                        rddata_reg(4) <= 'X';
                        rddata_reg(5) <= 'X';
                        rddata_reg(6) <= 'X';
                        rddata_reg(7) <= 'X';
                        rddata_reg(8) <= 'X';
                        rddata_reg(9) <= 'X';
                        rddata_reg(10) <= 'X';
                        rddata_reg(11) <= 'X';
                        rddata_reg(12) <= 'X';
                        rddata_reg(13) <= 'X';
                        rddata_reg(14) <= 'X';
                        rddata_reg(15) <= 'X';
                        rddata_reg(16) <= 'X';
                        rddata_reg(17) <= 'X';
                        rddata_reg(18) <= 'X';
                        rddata_reg(19) <= 'X';
                        rddata_reg(20) <= 'X';
                        rddata_reg(21) <= 'X';
                        rddata_reg(22) <= 'X';
                        rddata_reg(23) <= 'X';
                        rddata_reg(24) <= 'X';
                        rddata_reg(25) <= 'X';
                        rddata_reg(26) <= 'X';
                        rddata_reg(27) <= 'X';
                        rddata_reg(28) <= 'X';
                        rddata_reg(29) <= 'X';
                        rddata_reg(30) <= 'X';
                        rddata_reg(31) <= 'X';
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "100" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= mfpts_fd_rxcdn_cnt_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when "101" => 
                        if (wb_we_i = '1') then
                        end if;
                        rddata_reg(31 downto 0) <= mfpts_fd_txerr_cnt_i;
                        ack_sreg(0) <= '1';
                        ack_in_progress <= '1';
                    when others =>
-- prevent the slave from hanging the bus on invalid address
                        ack_in_progress <= '1';
                        ack_sreg(0) <= '1';
                    end case;
                end if;
            end if;
        end if;
    end process;
    
    
-- Drive the data output bus
    wb_dat_o <= rddata_reg;
-- reset of the masterFIP core
    process (clk_sys_i, rst_n_i)
    begin
        if (rst_n_i = '0') then 
            mfpts_rst_core_dly0 <= '0';
            mfpts_rst_core_o <= '0';
        elsif rising_edge(clk_sys_i) then
            mfpts_rst_core_dly0 <= mfpts_rst_core_int;
            mfpts_rst_core_o <= mfpts_rst_core_int and (not mfpts_rst_core_dly0);
        end if;
    end process;
    
    
-- termination enable
    mfpts_ext_sync_term_en_o <= mfpts_ext_sync_term_en_int;
-- transceiver direction
    mfpts_ext_sync_dir_o <= mfpts_ext_sync_dir_int;
-- transceiver output enable
    mfpts_ext_sync_oe_o <= mfpts_ext_sync_oe_int;
-- External sync output value (when buffer is switched)
    mfpts_ext_sync_output_value_o <= mfpts_ext_sync_output_value_int;
-- FPGA IO direction
    mfpts_ext_sync_fpga_io_dir_o <= mfpts_ext_sync_fpga_io_dir_int;
-- raw_input
-- enable
    mfpts_tx_corrupt_enable_o <= mfpts_tx_corrupt_enable_int;
-- fd watchdog
-- fd watchdog latched
-- fd carrier detect
-- fd transmitter error
-- fieldrive rx not carrier detect  counter
-- fieldrive tx error counter
    rwaddr_reg <= wb_adr_i;
    wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
    wb_ack_o <= ack_sreg(0);
end syn;
