/*
  Register definitions for slave core: FMC masterFIP core registers

  * File           : /home/gumas/projects/cti/fmcmasterfip/project/software/regs/masterfip_csr_pts.h
  * Author         : auto-generated by wbgen2 from /home/gumas/projects/cti/fmcmasterfip/project/gateware/rtl/wbgen/fmc_masterfip_csr.wb
  * Created        : Thu Mar  3 11:00:31 2016
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/fmcmasterfip/project/gateware/rtl/wbgen/fmc_masterfip_csr.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_/HOME/GUMAS/PROJECTS/CTI/FMCMASTERFIP/PROJECT/GATEWARE/RTL/WBGEN/FMC_MASTERFIP_CSR_WB
#define __WBGEN2_REGDEFS_/HOME/GUMAS/PROJECTS/CTI/FMCMASTERFIP/PROJECT/GATEWARE/RTL/WBGEN/FMC_MASTERFIP_CSR_WB

#include <inttypes.h>

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: rstn */

/* definitions for field: reset of the masterFIP core in reg: rstn */
#define MF_RSTN_CORE                          WBGEN2_GEN_MASK(0, 1)

/* definitions for field: reset of the fieldrive chip (FD_RSTN) in reg: rstn */
#define MF_RSTN_FD                            WBGEN2_GEN_MASK(1, 1)

/* definitions for field: reset magic value in reg: rstn */
#define MF_RSTN_LOCK_MASK                     WBGEN2_GEN_MASK(16, 16)
#define MF_RSTN_LOCK_SHIFT                    16
#define MF_RSTN_LOCK_W(value)                 WBGEN2_GEN_WRITE(value, 16, 16)
#define MF_RSTN_LOCK_R(reg)                   WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: led */

/* definitions for field: out_of_sync in reg: led */
#define MF_LED_OUT_OF_SYNC                    WBGEN2_GEN_MASK(0, 1)

/* definitions for field: rx_err in reg: led */
#define MF_LED_RX_ERR                         WBGEN2_GEN_MASK(1, 1)

/* definitions for field: rx_act in reg: led */
#define MF_LED_RX_ACT                         WBGEN2_GEN_MASK(2, 1)

/* definitions for field: sync in reg: led */
#define MF_LED_SYNC                           WBGEN2_GEN_MASK(3, 1)

/* definitions for field: tx_act in reg: led */
#define MF_LED_TX_ACT                         WBGEN2_GEN_MASK(4, 1)

/* definitions for field: tx_err in reg: led */
#define MF_LED_TX_ERR                         WBGEN2_GEN_MASK(5, 1)

/* definitions for register: id */

/* definitions for register: dbg */

/* definitions for register: adc */

/* definitions for field: 1v8_shdn_n in reg: adc */
#define MF_ADC_1V8_SHDN_N                     WBGEN2_GEN_MASK(0, 1)

/* definitions for field: m5v_shdn_n in reg: adc */
#define MF_ADC_M5V_SHDN_N                     WBGEN2_GEN_MASK(1, 1)

/* definitions for field: 5v_en in reg: adc */
#define MF_ADC_5V_EN                          WBGEN2_GEN_MASK(2, 1)

/* definitions for field: prim_conn in reg: adc */
#define MF_ADC_PRIM_CONN                      WBGEN2_GEN_MASK(8, 1)

/* definitions for field: sec_conn in reg: adc */
#define MF_ADC_SEC_CONN                       WBGEN2_GEN_MASK(9, 1)

/* definitions for register: ext sync */

/* definitions for field: termination enable in reg: ext sync */
#define MF_EXT_SYNC_TERM_EN                   WBGEN2_GEN_MASK(0, 1)

/* definitions for field: tranceiver direction in reg: ext sync */
#define MF_EXT_SYNC_DIR                       WBGEN2_GEN_MASK(1, 1)

/* definitions for field: tranceiver output enable in reg: ext sync */
#define MF_EXT_SYNC_OE                        WBGEN2_GEN_MASK(2, 1)

/* definitions for field: test pulse in reg: ext sync */
#define MF_EXT_SYNC_TST                       WBGEN2_GEN_MASK(3, 1)

/* definitions for field: pulses counter reset in reg: ext sync */
#define MF_EXT_SYNC_P_CNT_RST                 WBGEN2_GEN_MASK(8, 1)

/* definitions for register: ext sync pulses cnt */

/* definitions for register: bus termination */

/* definitions for register: speed */

/* definitions for register: macrocycle lgth */

/* definitions for field: macrocycle lgth in reg: macrocycle lgth */
#define MF_MACROCYC_LGTH_MASK                 WBGEN2_GEN_MASK(0, 31)
#define MF_MACROCYC_LGTH_SHIFT                0
#define MF_MACROCYC_LGTH_W(value)             WBGEN2_GEN_WRITE(value, 0, 31)
#define MF_MACROCYC_LGTH_R(reg)               WBGEN2_GEN_READ(reg, 0, 31)

/* definitions for field: macrocycle cnt start in reg: macrocycle lgth */
#define MF_MACROCYC_START                     WBGEN2_GEN_MASK(31, 1)

/* definitions for register: turnaround lgth */

/* definitions for field: turnaround time in reg: turnaround lgth */
#define MF_TURNAR_LGTH_MASK                   WBGEN2_GEN_MASK(0, 31)
#define MF_TURNAR_LGTH_SHIFT                  0
#define MF_TURNAR_LGTH_W(value)               WBGEN2_GEN_WRITE(value, 0, 31)
#define MF_TURNAR_LGTH_R(reg)                 WBGEN2_GEN_READ(reg, 0, 31)

/* definitions for field: turnaround cnt start in reg: turnaround lgth */
#define MF_TURNAR_START                       WBGEN2_GEN_MASK(31, 1)

/* definitions for register: silence lgth */

/* definitions for field: silence time in reg: silence lgth */
#define MF_SILEN_LGTH_MASK                    WBGEN2_GEN_MASK(0, 31)
#define MF_SILEN_LGTH_SHIFT                   0
#define MF_SILEN_LGTH_W(value)                WBGEN2_GEN_WRITE(value, 0, 31)
#define MF_SILEN_LGTH_R(reg)                  WBGEN2_GEN_READ(reg, 0, 31)

/* definitions for field: silence cnt start in reg: silence lgth */
#define MF_SILEN_START                        WBGEN2_GEN_MASK(31, 1)

/* definitions for register: macrocycle time cnt */

/* definitions for register: macrocycles number cnt */

/* definitions for register: turnaround time cnt */

/* definitions for register: silence time cnt */

/* definitions for register: tx ctrl */

/* definitions for field: tx rst in reg: tx ctrl */
#define MF_TX_CTRL_RST                        WBGEN2_GEN_MASK(0, 1)

/* definitions for field: tx strt in reg: tx ctrl */
#define MF_TX_CTRL_START                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: tx number of bytes in reg: tx ctrl */
#define MF_TX_CTRL_BYTES_NUM_MASK             WBGEN2_GEN_MASK(8, 9)
#define MF_TX_CTRL_BYTES_NUM_SHIFT            8
#define MF_TX_CTRL_BYTES_NUM_W(value)         WBGEN2_GEN_WRITE(value, 8, 9)
#define MF_TX_CTRL_BYTES_NUM_R(reg)           WBGEN2_GEN_READ(reg, 8, 9)

/* definitions for register: tx status */

/* definitions for field: tx ended in reg: tx status */
#define MF_TX_STAT_STOP                       WBGEN2_GEN_MASK(0, 1)

/* definitions for field: tx current byte in reg: tx status */
#define MF_TX_STAT_BYTE_INDEX_MASK            WBGEN2_GEN_MASK(8, 9)
#define MF_TX_STAT_BYTE_INDEX_SHIFT           8
#define MF_TX_STAT_BYTE_INDEX_W(value)        WBGEN2_GEN_WRITE(value, 8, 9)
#define MF_TX_STAT_BYTE_INDEX_R(reg)          WBGEN2_GEN_READ(reg, 8, 9)

/* definitions for field: tx enable in reg: tx status */
#define MF_TX_STAT_ENA                        WBGEN2_GEN_MASK(24, 1)

/* definitions for register: fieldrive status */

/* definitions for field: fd watchdog in reg: fieldrive status */
#define MF_FD_WDGN                            WBGEN2_GEN_MASK(0, 1)

/* definitions for field: fd carrier detect in reg: fieldrive status */
#define MF_FD_CD_N                            WBGEN2_GEN_MASK(1, 1)

/* definitions for field: fd transmitter error in reg: fieldrive status */
#define MF_FD_TXER                            WBGEN2_GEN_MASK(2, 1)

/* definitions for register: rx ctrl */

/* definitions for field: rx rst in reg: rx ctrl */
#define MF_RX_CTRL_RST                        WBGEN2_GEN_MASK(0, 1)

/* definitions for register: rx status */

/* definitions for field: rx preamble detected in reg: rx status */
#define MF_RX_STAT_PREAM_OK                   WBGEN2_GEN_MASK(0, 1)

/* definitions for field: rx frame ok in reg: rx status */
#define MF_RX_STAT_FRAME_OK                   WBGEN2_GEN_MASK(1, 1)

/* definitions for field: rx frame error in reg: rx status */
#define MF_RX_STAT_FRAME_ERR                  WBGEN2_GEN_MASK(2, 1)

/* definitions for field: rx frame error code in reg: rx status */
#define MF_RX_STAT_FRAME_ERR_CODE_MASK        WBGEN2_GEN_MASK(3, 3)
#define MF_RX_STAT_FRAME_ERR_CODE_SHIFT       3
#define MF_RX_STAT_FRAME_ERR_CODE_W(value)    WBGEN2_GEN_WRITE(value, 3, 3)
#define MF_RX_STAT_FRAME_ERR_CODE_R(reg)      WBGEN2_GEN_READ(reg, 3, 3)

/* definitions for field: rx number of data bytes in reg: rx status */
#define MF_RX_STAT_BYTES_NUM_MASK             WBGEN2_GEN_MASK(8, 9)
#define MF_RX_STAT_BYTES_NUM_SHIFT            8
#define MF_RX_STAT_BYTES_NUM_W(value)         WBGEN2_GEN_WRITE(value, 8, 9)
#define MF_RX_STAT_BYTES_NUM_R(reg)           WBGEN2_GEN_READ(reg, 8, 9)

/* definitions for register: rx data ctrl byte */

/* definitions for register: rx data reg1 */

/* definitions for register: rx data reg2 */

/* definitions for register: rx data reg3 */

/* definitions for register: rx data reg4 */

/* definitions for register: rx data reg5 */

/* definitions for register: rx data reg6 */

/* definitions for register: rx data reg7 */

/* definitions for register: rx data reg8 */

/* definitions for register: rx data reg9 */

/* definitions for register: rx data reg10 */

/* definitions for register: rx data reg11 */

/* definitions for register: rx data reg12 */

/* definitions for register: rx data reg13 */

/* definitions for register: rx data reg14 */

/* definitions for register: rx data reg15 */

/* definitions for register: rx data reg16 */

/* definitions for register: rx data reg17 */

/* definitions for register: rx data reg18 */

/* definitions for register: rx data reg19 */

/* definitions for register: rx data reg20 */

/* definitions for register: rx data reg21 */

/* definitions for register: rx data reg22 */

/* definitions for register: rx data reg23 */

/* definitions for register: rx data reg24 */

/* definitions for register: rx data reg25 */

/* definitions for register: rx data reg26 */

/* definitions for register: rx data reg27 */

/* definitions for register: rx data reg28 */

/* definitions for register: rx data reg29 */

/* definitions for register: rx data reg30 */

/* definitions for register: rx data reg31 */

/* definitions for register: rx data reg32 */

/* definitions for register: rx data reg33 */

/* definitions for register: rx data reg34 */

/* definitions for register: rx data reg35 */

/* definitions for register: rx data reg36 */

/* definitions for register: rx data reg37 */

/* definitions for register: rx data reg38 */

/* definitions for register: rx data reg39 */

/* definitions for register: rx data reg40 */

/* definitions for register: rx data reg41 */

/* definitions for register: rx data reg42 */

/* definitions for register: rx data reg43 */

/* definitions for register: rx data reg44 */

/* definitions for register: rx data reg45 */

/* definitions for register: rx data reg46 */

/* definitions for register: rx data reg47 */

/* definitions for register: rx data reg48 */

/* definitions for register: rx data reg49 */

/* definitions for register: rx data reg50 */

/* definitions for register: rx data reg51 */

/* definitions for register: rx data reg52 */

/* definitions for register: rx data reg53 */

/* definitions for register: rx data reg54 */

/* definitions for register: rx data reg55 */

/* definitions for register: rx data reg56 */

/* definitions for register: rx data reg57 */

/* definitions for register: rx data reg58 */

/* definitions for register: rx data reg59 */

/* definitions for register: rx data reg60 */

/* definitions for register: rx data reg61 */

/* definitions for register: rx data reg62 */

/* definitions for register: rx data reg63 */

/* definitions for register: rx data reg64 */

/* definitions for register: rx data reg65 */

/* definitions for register: rx data reg66 */

/* definitions for register: tx ctrl byte */

/* definitions for register: tx data reg1 */

/* definitions for register: tx data reg2 */

/* definitions for register: tx data reg3 */

/* definitions for register: tx data reg4 */

/* definitions for register: tx data reg5 */

/* definitions for register: tx data reg6 */

/* definitions for register: tx data reg7 */

/* definitions for register: tx data reg8 */

/* definitions for register: tx data reg9 */

/* definitions for register: tx data reg10 */

/* definitions for register: tx data reg11 */

/* definitions for register: tx data reg12 */

/* definitions for register: tx data reg13 */

/* definitions for register: tx data reg14 */

/* definitions for register: tx data reg15 */

/* definitions for register: tx data reg16 */

/* definitions for register: tx data reg17 */

/* definitions for register: tx data reg18 */

/* definitions for register: tx data reg19 */

/* definitions for register: tx data reg20 */

/* definitions for register: tx data reg21 */

/* definitions for register: tx data reg22 */

/* definitions for register: tx data reg23 */

/* definitions for register: tx data reg24 */

/* definitions for register: tx data reg25 */

/* definitions for register: tx data reg26 */

/* definitions for register: tx data reg27 */

/* definitions for register: tx data reg28 */

/* definitions for register: tx data reg29 */

/* definitions for register: tx data reg30 */

/* definitions for register: tx data reg31 */

/* definitions for register: tx data reg32 */

/* definitions for register: tx data reg33 */

/* definitions for register: tx data reg34 */

/* definitions for register: tx data reg35 */

/* definitions for register: tx data reg36 */

/* definitions for register: tx data reg37 */

/* definitions for register: tx data reg38 */

/* definitions for register: tx data reg39 */

/* definitions for register: tx data reg40 */

/* definitions for register: tx data reg41 */

/* definitions for register: tx data reg42 */

/* definitions for register: tx data reg43 */

/* definitions for register: tx data reg44 */

/* definitions for register: tx data reg45 */

/* definitions for register: tx data reg46 */

/* definitions for register: tx data reg47 */

/* definitions for register: tx data reg48 */

/* definitions for register: tx data reg49 */

/* definitions for register: tx data reg50 */

/* definitions for register: tx data reg51 */

/* definitions for register: tx data reg52 */

/* definitions for register: tx data reg53 */

/* definitions for register: tx data reg54 */

/* definitions for register: tx data reg55 */

/* definitions for register: tx data reg56 */

/* definitions for register: tx data reg57 */

/* definitions for register: tx data reg58 */

/* definitions for register: tx data reg59 */

/* definitions for register: tx data reg60 */

/* definitions for register: tx data reg61 */

/* definitions for register: tx data reg62 */

/* definitions for register: tx data reg63 */

/* definitions for register: tx data reg64 */

/* definitions for register: tx data reg65 */

/* definitions for register: tx data reg66 */
/* [0x0]: REG rstn */
#define MF_REG_RSTN 0x00000000
/* [0x4]: REG led */
#define MF_REG_LED 0x00000004
/* [0x8]: REG id */
#define MF_REG_ID 0x00000008
/* [0xc]: REG dbg */
#define MF_REG_DBG 0x0000000c
/* [0x10]: REG adc */
#define MF_REG_ADC 0x00000010
/* [0x14]: REG ext sync */
#define MF_REG_EXT_SYNC 0x00000014
/* [0x18]: REG ext sync pulses cnt */
#define MF_REG_EXT_SYNC_P_CNT 0x00000018
/* [0x1c]: REG bus termination */
#define MF_REG_BUS_TERM_EN_N 0x0000001c
/* [0x20]: REG speed */
#define MF_REG_SPEED 0x00000020
/* [0x24]: REG macrocycle lgth */
#define MF_REG_MACROCYC 0x00000024
/* [0x28]: REG turnaround lgth */
#define MF_REG_TURNAR 0x00000028
/* [0x2c]: REG silence lgth */
#define MF_REG_SILEN 0x0000002c
/* [0x30]: REG macrocycle time cnt */
#define MF_REG_MACROCYC_TIME_CNT 0x00000030
/* [0x34]: REG macrocycles number cnt */
#define MF_REG_MACROCYC_NUM_CNT 0x00000034
/* [0x38]: REG turnaround time cnt */
#define MF_REG_TURNAR_TIME_CNT 0x00000038
/* [0x3c]: REG silence time cnt */
#define MF_REG_SILEN_TIME_CNT 0x0000003c
/* [0x40]: REG tx ctrl */
#define MF_REG_TX_CTRL 0x00000040
/* [0x44]: REG tx status */
#define MF_REG_TX_STAT 0x00000044
/* [0x48]: REG fieldrive status */
#define MF_REG_FD 0x00000048
/* [0x4c]: REG rx ctrl */
#define MF_REG_RX_CTRL 0x0000004c
/* [0x50]: REG rx status */
#define MF_REG_RX_STAT 0x00000050
/* [0x54]: REG rx data ctrl byte */
#define MF_REG_RX_DATA_CTRL 0x00000054
/* [0x58]: REG rx data reg1 */
#define MF_REG_RX_DATA_REG1 0x00000058
/* [0x5c]: REG rx data reg2 */
#define MF_REG_RX_DATA_REG2 0x0000005c
/* [0x60]: REG rx data reg3 */
#define MF_REG_RX_DATA_REG3 0x00000060
/* [0x64]: REG rx data reg4 */
#define MF_REG_RX_DATA_REG4 0x00000064
/* [0x68]: REG rx data reg5 */
#define MF_REG_RX_DATA_REG5 0x00000068
/* [0x6c]: REG rx data reg6 */
#define MF_REG_RX_DATA_REG6 0x0000006c
/* [0x70]: REG rx data reg7 */
#define MF_REG_RX_DATA_REG7 0x00000070
/* [0x74]: REG rx data reg8 */
#define MF_REG_RX_DATA_REG8 0x00000074
/* [0x78]: REG rx data reg9 */
#define MF_REG_RX_DATA_REG9 0x00000078
/* [0x7c]: REG rx data reg10 */
#define MF_REG_RX_DATA_REG10 0x0000007c
/* [0x80]: REG rx data reg11 */
#define MF_REG_RX_DATA_REG11 0x00000080
/* [0x84]: REG rx data reg12 */
#define MF_REG_RX_DATA_REG12 0x00000084
/* [0x88]: REG rx data reg13 */
#define MF_REG_RX_DATA_REG13 0x00000088
/* [0x8c]: REG rx data reg14 */
#define MF_REG_RX_DATA_REG14 0x0000008c
/* [0x90]: REG rx data reg15 */
#define MF_REG_RX_DATA_REG15 0x00000090
/* [0x94]: REG rx data reg16 */
#define MF_REG_RX_DATA_REG16 0x00000094
/* [0x98]: REG rx data reg17 */
#define MF_REG_RX_DATA_REG17 0x00000098
/* [0x9c]: REG rx data reg18 */
#define MF_REG_RX_DATA_REG18 0x0000009c
/* [0xa0]: REG rx data reg19 */
#define MF_REG_RX_DATA_REG19 0x000000a0
/* [0xa4]: REG rx data reg20 */
#define MF_REG_RX_DATA_REG20 0x000000a4
/* [0xa8]: REG rx data reg21 */
#define MF_REG_RX_DATA_REG21 0x000000a8
/* [0xac]: REG rx data reg22 */
#define MF_REG_RX_DATA_REG22 0x000000ac
/* [0xb0]: REG rx data reg23 */
#define MF_REG_RX_DATA_REG23 0x000000b0
/* [0xb4]: REG rx data reg24 */
#define MF_REG_RX_DATA_REG24 0x000000b4
/* [0xb8]: REG rx data reg25 */
#define MF_REG_RX_DATA_REG25 0x000000b8
/* [0xbc]: REG rx data reg26 */
#define MF_REG_RX_DATA_REG26 0x000000bc
/* [0xc0]: REG rx data reg27 */
#define MF_REG_RX_DATA_REG27 0x000000c0
/* [0xc4]: REG rx data reg28 */
#define MF_REG_RX_DATA_REG28 0x000000c4
/* [0xc8]: REG rx data reg29 */
#define MF_REG_RX_DATA_REG29 0x000000c8
/* [0xcc]: REG rx data reg30 */
#define MF_REG_RX_DATA_REG30 0x000000cc
/* [0xd0]: REG rx data reg31 */
#define MF_REG_RX_DATA_REG31 0x000000d0
/* [0xd4]: REG rx data reg32 */
#define MF_REG_RX_DATA_REG32 0x000000d4
/* [0xd8]: REG rx data reg33 */
#define MF_REG_RX_DATA_REG33 0x000000d8
/* [0xdc]: REG rx data reg34 */
#define MF_REG_RX_DATA_REG34 0x000000dc
/* [0xe0]: REG rx data reg35 */
#define MF_REG_RX_DATA_REG35 0x000000e0
/* [0xe4]: REG rx data reg36 */
#define MF_REG_RX_DATA_REG36 0x000000e4
/* [0xe8]: REG rx data reg37 */
#define MF_REG_RX_DATA_REG37 0x000000e8
/* [0xec]: REG rx data reg38 */
#define MF_REG_RX_DATA_REG38 0x000000ec
/* [0xf0]: REG rx data reg39 */
#define MF_REG_RX_DATA_REG39 0x000000f0
/* [0xf4]: REG rx data reg40 */
#define MF_REG_RX_DATA_REG40 0x000000f4
/* [0xf8]: REG rx data reg41 */
#define MF_REG_RX_DATA_REG41 0x000000f8
/* [0xfc]: REG rx data reg42 */
#define MF_REG_RX_DATA_REG42 0x000000fc
/* [0x100]: REG rx data reg43 */
#define MF_REG_RX_DATA_REG43 0x00000100
/* [0x104]: REG rx data reg44 */
#define MF_REG_RX_DATA_REG44 0x00000104
/* [0x108]: REG rx data reg45 */
#define MF_REG_RX_DATA_REG45 0x00000108
/* [0x10c]: REG rx data reg46 */
#define MF_REG_RX_DATA_REG46 0x0000010c
/* [0x110]: REG rx data reg47 */
#define MF_REG_RX_DATA_REG47 0x00000110
/* [0x114]: REG rx data reg48 */
#define MF_REG_RX_DATA_REG48 0x00000114
/* [0x118]: REG rx data reg49 */
#define MF_REG_RX_DATA_REG49 0x00000118
/* [0x11c]: REG rx data reg50 */
#define MF_REG_RX_DATA_REG50 0x0000011c
/* [0x120]: REG rx data reg51 */
#define MF_REG_RX_DATA_REG51 0x00000120
/* [0x124]: REG rx data reg52 */
#define MF_REG_RX_DATA_REG52 0x00000124
/* [0x128]: REG rx data reg53 */
#define MF_REG_RX_DATA_REG53 0x00000128
/* [0x12c]: REG rx data reg54 */
#define MF_REG_RX_DATA_REG54 0x0000012c
/* [0x130]: REG rx data reg55 */
#define MF_REG_RX_DATA_REG55 0x00000130
/* [0x134]: REG rx data reg56 */
#define MF_REG_RX_DATA_REG56 0x00000134
/* [0x138]: REG rx data reg57 */
#define MF_REG_RX_DATA_REG57 0x00000138
/* [0x13c]: REG rx data reg58 */
#define MF_REG_RX_DATA_REG58 0x0000013c
/* [0x140]: REG rx data reg59 */
#define MF_REG_RX_DATA_REG59 0x00000140
/* [0x144]: REG rx data reg60 */
#define MF_REG_RX_DATA_REG60 0x00000144
/* [0x148]: REG rx data reg61 */
#define MF_REG_RX_DATA_REG61 0x00000148
/* [0x14c]: REG rx data reg62 */
#define MF_REG_RX_DATA_REG62 0x0000014c
/* [0x150]: REG rx data reg63 */
#define MF_REG_RX_DATA_REG63 0x00000150
/* [0x154]: REG rx data reg64 */
#define MF_REG_RX_DATA_REG64 0x00000154
/* [0x158]: REG rx data reg65 */
#define MF_REG_RX_DATA_REG65 0x00000158
/* [0x15c]: REG rx data reg66 */
#define MF_REG_RX_DATA_REG66 0x0000015c
/* [0x160]: REG tx ctrl byte */
#define MF_REG_TX_DATA_CTRL 0x00000160
/* [0x164]: REG tx data reg1 */
#define MF_REG_TX_DATA_REG1 0x00000164
/* [0x168]: REG tx data reg2 */
#define MF_REG_TX_DATA_REG2 0x00000168
/* [0x16c]: REG tx data reg3 */
#define MF_REG_TX_DATA_REG3 0x0000016c
/* [0x170]: REG tx data reg4 */
#define MF_REG_TX_DATA_REG4 0x00000170
/* [0x174]: REG tx data reg5 */
#define MF_REG_TX_DATA_REG5 0x00000174
/* [0x178]: REG tx data reg6 */
#define MF_REG_TX_DATA_REG6 0x00000178
/* [0x17c]: REG tx data reg7 */
#define MF_REG_TX_DATA_REG7 0x0000017c
/* [0x180]: REG tx data reg8 */
#define MF_REG_TX_DATA_REG8 0x00000180
/* [0x184]: REG tx data reg9 */
#define MF_REG_TX_DATA_REG9 0x00000184
/* [0x188]: REG tx data reg10 */
#define MF_REG_TX_DATA_REG10 0x00000188
/* [0x18c]: REG tx data reg11 */
#define MF_REG_TX_DATA_REG11 0x0000018c
/* [0x190]: REG tx data reg12 */
#define MF_REG_TX_DATA_REG12 0x00000190
/* [0x194]: REG tx data reg13 */
#define MF_REG_TX_DATA_REG13 0x00000194
/* [0x198]: REG tx data reg14 */
#define MF_REG_TX_DATA_REG14 0x00000198
/* [0x19c]: REG tx data reg15 */
#define MF_REG_TX_DATA_REG15 0x0000019c
/* [0x1a0]: REG tx data reg16 */
#define MF_REG_TX_DATA_REG16 0x000001a0
/* [0x1a4]: REG tx data reg17 */
#define MF_REG_TX_DATA_REG17 0x000001a4
/* [0x1a8]: REG tx data reg18 */
#define MF_REG_TX_DATA_REG18 0x000001a8
/* [0x1ac]: REG tx data reg19 */
#define MF_REG_TX_DATA_REG19 0x000001ac
/* [0x1b0]: REG tx data reg20 */
#define MF_REG_TX_DATA_REG20 0x000001b0
/* [0x1b4]: REG tx data reg21 */
#define MF_REG_TX_DATA_REG21 0x000001b4
/* [0x1b8]: REG tx data reg22 */
#define MF_REG_TX_DATA_REG22 0x000001b8
/* [0x1bc]: REG tx data reg23 */
#define MF_REG_TX_DATA_REG23 0x000001bc
/* [0x1c0]: REG tx data reg24 */
#define MF_REG_TX_DATA_REG24 0x000001c0
/* [0x1c4]: REG tx data reg25 */
#define MF_REG_TX_DATA_REG25 0x000001c4
/* [0x1c8]: REG tx data reg26 */
#define MF_REG_TX_DATA_REG26 0x000001c8
/* [0x1cc]: REG tx data reg27 */
#define MF_REG_TX_DATA_REG27 0x000001cc
/* [0x1d0]: REG tx data reg28 */
#define MF_REG_TX_DATA_REG28 0x000001d0
/* [0x1d4]: REG tx data reg29 */
#define MF_REG_TX_DATA_REG29 0x000001d4
/* [0x1d8]: REG tx data reg30 */
#define MF_REG_TX_DATA_REG30 0x000001d8
/* [0x1dc]: REG tx data reg31 */
#define MF_REG_TX_DATA_REG31 0x000001dc
/* [0x1e0]: REG tx data reg32 */
#define MF_REG_TX_DATA_REG32 0x000001e0
/* [0x1e4]: REG tx data reg33 */
#define MF_REG_TX_DATA_REG33 0x000001e4
/* [0x1e8]: REG tx data reg34 */
#define MF_REG_TX_DATA_REG34 0x000001e8
/* [0x1ec]: REG tx data reg35 */
#define MF_REG_TX_DATA_REG35 0x000001ec
/* [0x1f0]: REG tx data reg36 */
#define MF_REG_TX_DATA_REG36 0x000001f0
/* [0x1f4]: REG tx data reg37 */
#define MF_REG_TX_DATA_REG37 0x000001f4
/* [0x1f8]: REG tx data reg38 */
#define MF_REG_TX_DATA_REG38 0x000001f8
/* [0x1fc]: REG tx data reg39 */
#define MF_REG_TX_DATA_REG39 0x000001fc
/* [0x200]: REG tx data reg40 */
#define MF_REG_TX_DATA_REG40 0x00000200
/* [0x204]: REG tx data reg41 */
#define MF_REG_TX_DATA_REG41 0x00000204
/* [0x208]: REG tx data reg42 */
#define MF_REG_TX_DATA_REG42 0x00000208
/* [0x20c]: REG tx data reg43 */
#define MF_REG_TX_DATA_REG43 0x0000020c
/* [0x210]: REG tx data reg44 */
#define MF_REG_TX_DATA_REG44 0x00000210
/* [0x214]: REG tx data reg45 */
#define MF_REG_TX_DATA_REG45 0x00000214
/* [0x218]: REG tx data reg46 */
#define MF_REG_TX_DATA_REG46 0x00000218
/* [0x21c]: REG tx data reg47 */
#define MF_REG_TX_DATA_REG47 0x0000021c
/* [0x220]: REG tx data reg48 */
#define MF_REG_TX_DATA_REG48 0x00000220
/* [0x224]: REG tx data reg49 */
#define MF_REG_TX_DATA_REG49 0x00000224
/* [0x228]: REG tx data reg50 */
#define MF_REG_TX_DATA_REG50 0x00000228
/* [0x22c]: REG tx data reg51 */
#define MF_REG_TX_DATA_REG51 0x0000022c
/* [0x230]: REG tx data reg52 */
#define MF_REG_TX_DATA_REG52 0x00000230
/* [0x234]: REG tx data reg53 */
#define MF_REG_TX_DATA_REG53 0x00000234
/* [0x238]: REG tx data reg54 */
#define MF_REG_TX_DATA_REG54 0x00000238
/* [0x23c]: REG tx data reg55 */
#define MF_REG_TX_DATA_REG55 0x0000023c
/* [0x240]: REG tx data reg56 */
#define MF_REG_TX_DATA_REG56 0x00000240
/* [0x244]: REG tx data reg57 */
#define MF_REG_TX_DATA_REG57 0x00000244
/* [0x248]: REG tx data reg58 */
#define MF_REG_TX_DATA_REG58 0x00000248
/* [0x24c]: REG tx data reg59 */
#define MF_REG_TX_DATA_REG59 0x0000024c
/* [0x250]: REG tx data reg60 */
#define MF_REG_TX_DATA_REG60 0x00000250
/* [0x254]: REG tx data reg61 */
#define MF_REG_TX_DATA_REG61 0x00000254
/* [0x258]: REG tx data reg62 */
#define MF_REG_TX_DATA_REG62 0x00000258
/* [0x25c]: REG tx data reg63 */
#define MF_REG_TX_DATA_REG63 0x0000025c
/* [0x260]: REG tx data reg64 */
#define MF_REG_TX_DATA_REG64 0x00000260
/* [0x264]: REG tx data reg65 */
#define MF_REG_TX_DATA_REG65 0x00000264
/* [0x268]: REG tx data reg66 */
#define MF_REG_TX_DATA_REG66 0x00000268
#endif
