target = "xilinx"
action = "synthesis"

syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top_fmc_masterfip"
syn_project = "spec_fmc_masterfip.xise"
syn_tool = "ise"

files = [
    "../../top/spec/spec_top_fmc_masterfip.ucf",
    "../../top/spec/spec_top_fmc_masterfip.vhd"]

modules = { "local" : ["../../rtl",
                        "../../ip_cores/fmc-adc-100m14b4cha-gw/hdl/adc/rtl",
                        "../../ip_cores/fmc-adc-100m14b4cha-gw/hdl/spec/rtl",
                        "../../ip_cores/fmc-adc-100m14b4cha-gw/hdl/ip_cores/timetag_core/rtl"],
            "git" : ["git://ohwr.org/hdl-core-lib/general-cores.git::proposed_master",
                     "git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::spec_bank3_64b_32b",
                     "git://ohwr.org/hdl-core-lib/gn4124-core.git::master",
                     "git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git::master"]}

fetchto="../../ip_cores"
