--_________________________________________________________________________________________________
--                                                                                                |
--                                        |SPEC masterFIP|                                        |
--                                                                                                |
--                                         CERN, BE/CO-HT                                         |
--________________________________________________________________________________________________|

---------------------------------------------------------------------------------------------------
--                                                                                                |
--                                        spec_masterfip                                          |
--                                                                                                |
---------------------------------------------------------------------------------------------------
-- File         spec_masterfip.vhd                                                                |
--                                                                                                |
-- Description  Top level of a simple masterFIP on a SPEC carrier.                                |
--              Figure 1 shows the architecture of the unit.                                      |
--                                                                                                |
--              This design does not use the Mock Turtle core and can only be used for very       |
--              simple WorldFIP manipulations.                                                    |
--                                                                                                |
--              The fmc_masterFIP_core mainly implements the WorldFIP serializer and deserialiser.|
--              Its interface component fmc_masterfip_csr provides a set of registers to basically|
--                - control the serialiser to send out WorldFIP frames and                        |
--                - monitor if a WorldFIP frame has arrived to the deserialiser                   |
--              The core accesses all the WorldFIP-specific parts of the masterFIP mezzanine board|
--              However there is no access to the ADC part of the masterFIP mezzanine board.      |
--                                                                                                |
--              The SPEC_CSR module provides general information on the SPEC PCB version, PLLs    |
--              locking state etc.                                                                |
--                                                                                                |
--              The 1-Wire core provides communication with the SPEC Thermometer&UniqueID chip.   |
--                                                                                                |
--              All the cores communicate with the GN4124 core through the SDB crossbar. The SDB  |
--              crossbar is responsible for managing the access to the GN4124 core.               |
--                                                                                                |
--              The design has only one clock domain, 100 MHz generated by a Xilinx internal PLL  |
--              which is using the 20 MHz VCXO on the SPEC.                                       |
--                                                                                                |
--                   __________________________________________________________________           |
--                  |                                                        SPEC FPGA |          |
--   ___________    |                                           ___        _____       |          |
--  |           |   |       ____________________________       |   |      |     |      |          |
--  | masterFIP |   |      |                            |      |   |      |     |      |          |
--  |   mezz    |<->|      |    masterFIP mezzanine     | ---  |   |      |     |      |          |
--  |___________|   |      |____________________________|      |   |      |  G  |      |          |
--                  |                                          |   |      |  N  |      |          |
--                  |       ____________________________       | S |      |  4  |      |          |
--   SPEC 1Wire  <->|      |        SPEC 1-Wire         | ---- | D | <--> |  1  |      |          |
--                  |      |____________________________|      | B |      |  2  |      |          |
--                  |                                          |   |      |  4  |      |          |
--                  |       ____________________________       |   |      |     |      |          |
--                  |      |          SPEC CSR          | ---- |   |      |     |      |          |
--                  |      |____________________________|      |   |      |     |      |          |
--                  |                                          |___|      |_____|      |          |
--                  |__________________________________________________________________|          |
--                                                Figure 1                                        |
--                                                                                                |
--                                                                                                |
-- Authors      Evangelia Gousiou (Evangelia.Gousiou@cern.ch)                                     |
-- Date         07/2014                                                                           |
-- Version      v1                                                                                |
--                                                                                                |
----------------                                                                                  |
-- Last changes                                                                                   |
--     07/2014  v1  EG  concept validation using very basic board                                 |
--     07/2015  v2  EG  validation of the masterFIP v1 prototype board                            |
--     01/2016  v3  EG  cleaned-up version to be used by PTS team                                 |
---------------------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------------------
--                               GNU LESSER GENERAL PUBLIC LICENSE                                |
--                              ------------------------------------                              |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either     |
-- version 2.1 of the License, or (at your option) any later version.                             |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;       |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.      |
-- See the GNU Lesser General Public License for more details.                                    |
-- You should have received a copy of the GNU Lesser General Public License along with this       |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html                     |
---------------------------------------------------------------------------------------------------

--=================================================================================================
--                                       Libraries & Packages
--=================================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.masterFIP_pkg.all;
use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.synthesis_descriptor.all;
library UNISIM;
use UNISIM.vcomponents.all;

--=================================================================================================
--                            Entity declaration for spec_masterfip
--=================================================================================================
entity spec_masterfip is
  generic
    (g_span             : integer := 32;                      -- address span in bus interfaces
     g_width            : integer := 32;                      -- data width in bus interfaces
     values_for_simul   : boolean := FALSE);                  -- set to TRUE in test-bench instantiation
  port
    (-- SPEC carrier
     clk_20m_vcxo_i     : in    std_logic;                    -- 20 MHz VCXO

     carrier_onewire_b  : inout std_logic;                    -- 1-wire

     button1_i          : in    std_logic := '1';             -- reset button
     button2_i          : in    std_logic := '1';             -- not used button

     led_green_o        : out   std_logic;                    -- LEDs carrier front pannel
     led_red_o          : out   std_logic;

     pcb_ver_i          : in    std_logic_vector(3 downto 0); -- PCB version
     prsnt_m2c_n_i      : in    std_logic;                    -- mezzanine presence

     -- Interface with GN4124
     rst_n_a_i          : in    std_logic;
     -- P2L Direction
     p2l_clk_p_i        : in    std_logic;                    -- Receiver Source Synchronous Clock+
     p2l_clk_n_i        : in    std_logic;                    -- Receiver Source Synchronous Clock-
     p2l_data_i         : in    std_logic_vector(15 downto 0);-- Parallel receive data
     p2l_dframe_i       : in    std_logic;                    -- Receive Frame
     p2l_valid_i        : in    std_logic;                    -- Receive Data Valid
     p2l_rdy_o          : out   std_logic;                    -- Rx Buffer Full Flag
     p_wr_req_i         : in    std_logic_vector(1 downto 0); -- PCIe Write Request
     p_wr_rdy_o         : out   std_logic_vector(1 downto 0); -- PCIe Write Ready
     rx_error_o         : out   std_logic;                    -- Receive Error
     vc_rdy_i           : in    std_logic_vector(1 downto 0); -- Virtual channel ready
     -- L2P Direction
     l2p_clk_p_o        : out   std_logic;                    -- Transmitter Source Synchronous Clock+ (freq set in GN4124 config registers)
     l2p_clk_n_o        : out   std_logic;                    -- Transmitter Source Synchronous Clock- (freq set in GN4124 config registers)
     l2p_data_o         : out   std_logic_vector(15 downto 0);-- Parallel transmit data
     l2p_dframe_o       : out   std_logic;                    -- Transmit Data Frame
     l2p_valid_o        : out   std_logic;                    -- Transmit Data Valid
     l2p_edb_o          : out   std_logic;                    -- Packet termination and discard
     l2p_rdy_i          : in    std_logic;                    -- Tx Buffer Full Flag
     l_wr_rdy_i         : in    std_logic_vector(1 downto 0); -- Local-to-PCIe Write
     p_rd_d_rdy_i       : in    std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
     tx_error_i         : in    std_logic;                    -- Transmit Error
     irq_p_o            : out   std_logic;                    -- Interrupt request pulse to GN4124 GPIO 8
     irq_aux_p_o        : out   std_logic;                    -- Interrupt request pulse to GN4124 GPIO 9, aux signal

     -- masterFIP mezzanine
     speed_b0_i         : in    std_logic;                    -- WorldFIP bus Speed
     speed_b1_i         : in    std_logic; 

     bus_term_en_n_o    : out   std_logic;                    -- WorldFIP bus termination
     
     fd_rxcdn_i         : in    std_logic;                    -- FielDrive
     fd_rxd_i           : in    std_logic;
     fd_txer_i          : in    std_logic;
     fd_wdgn_i          : in    std_logic;
     fd_rstn_o          : out   std_logic;
     fd_txck_o          : out   std_logic;
     fd_txd_o           : out   std_logic;
     fd_txena_o         : out   std_logic;
     
     ext_sync_term_en_o : out   std_logic;                    -- External synch pulse transceiver 
     ext_sync_dir_o     : out   std_logic;
     ext_sync_oe_o      : out   std_logic;
     ext_sync_tst_n_o   : out   std_logic;
     ext_sync_i         : in    std_logic;
     
     adc_1v8_shdn_n_o   : out   std_logic;                    -- Power supplies for the ADC
     adc_m5v_shdn_n_o   : out   std_logic;
     adc_5v_en_n_o      : out   std_logic;
     adc_prim_conn_n_o  : out   std_logic;
     adc_sec_conn_n_o   : out   std_logic;
     
     led_tx_err_n_o     : out   std_logic;                    -- LEDs mezzanine front pannel
     led_tx_act_n_o     : out   std_logic;
     led_rx_err_n_o     : out   std_logic;
     led_rx_act_n_o     : out   std_logic);

end spec_masterfip;

--=================================================================================================
--                                    architecture declaration
--=================================================================================================
architecture rtl of spec_masterfip is

---------------------------------------------------------------------------------------------------
--                                         SDB CONSTANTS                                         --
---------------------------------------------------------------------------------------------------
  -- Note: All address in sdb and crossbar are BYTE addresses!

  -- Master ports on the wishbone crossbar
  constant c_NUM_WB_MASTERS       : integer := 3;
  constant c_WB_SLAVE_SPEC_ONEWIRE: integer := 0;  -- SPEC 1-wire
  constant c_WB_SLAVE_SPEC_INFO   : integer := 1;  -- SPEC CSR
  constant c_WB_SLAVE_MASTERFIP   : integer := 2;  -- masterFIP core

  -- SDB header address
  constant c_SDB_ADDRESS          : t_wishbone_address := x"00000000";

  -- Slave port on the wishbone crossbar
  constant c_NUM_WB_SLAVES        : integer := 1;
  constant c_MASTER_GENNUM        : integer := 0;


  constant c_INTERCONNECT_LAYOUT  : t_sdb_record_array(4 downto 0) :=
    (0 => f_sdb_embed_device       (c_ONEWIRE_SDB_DEVICE,         x"00010000"),
     1 => f_sdb_embed_device       (c_SPEC_INFO_SDB_DEVICE,       x"00020000"),
     2 => f_sdb_embed_device       (c_MASTERFIP_SDB_DEVICE,       x"00030000"),
     3 => f_sdb_embed_repo_url     (c_SDB_REPO_URL),
     4 => f_sdb_embed_synthesis    (c_SDB_SYNTHESIS_INFO));


---------------------------------------------------------------------------------------------------
--                                            Signals                                            --
---------------------------------------------------------------------------------------------------

  -- clocks
  signal clk_20m_vcxo, clk_20m_vcxo_buf : std_logic;
  signal clk_100m_sys, pllout_clk_sys   : std_logic;
  signal pllout_clk_sys_fb              : std_logic;
  signal sys_locked, pll_status         : std_logic;
  -- reset
  signal rst_sys, rst_sys_n             : std_logic;
  -- WISHBONE from crossbar master port
  signal cnx_master_out                 : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
  signal cnx_master_in                  : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
  -- WISHBONE to crossbar slave port
  signal cnx_slave_out                  : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
  signal cnx_slave_in                   : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
  signal gn_wb_adr                      : std_logic_vector(31 downto 0);
  -- GN4124
  signal gn4124_status                  : std_logic_vector(31 downto 0);
  -- SPEC 1-wire
  signal carrier_owr_en, carrier_owr_i  : std_logic_vector(c_FMC_ONEWIRE_NB - 1 downto 0);
  -- aux
  signal aux                            : std_logic_vector(7 downto 0);
  -- LEDs
  signal led_clk_100m_divider           : unsigned(22 downto 0);
  signal led_clk_100m_aux               : std_logic_vector(7 downto 0);
  signal rx_err, rx_act, fd_txena       : std_logic;


--=================================================================================================
--                                       architecture begin
--=================================================================================================
begin

---------------------------------------------------------------------------------------------------
--                                100 MHz universal clk generation                               --
---------------------------------------------------------------------------------------------------

  cmp_spec_clk_ibuf : IBUFG
  port map
  (I => clk_20m_vcxo_i,
   O => clk_20m_vcxo_buf);

  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  cmp_sys_clk_pll : PLL_BASE
  generic map
    (BANDWIDTH          => "OPTIMIZED",
     CLK_FEEDBACK       => "CLKFBOUT",
     COMPENSATION       => "INTERNAL",
     DIVCLK_DIVIDE      => 1,
     CLKFBOUT_MULT      => 50,
     CLKFBOUT_PHASE     => 0.000,
     CLKOUT0_DIVIDE     => 10, --  100 MHz
     CLKOUT0_PHASE      => 0.000,
     CLKOUT0_DUTY_CYCLE => 0.500,
     CLKOUT1_DIVIDE     => 8,
     CLKOUT1_PHASE      => 0.000,
     CLKOUT1_DUTY_CYCLE => 0.500,
     CLKOUT2_DIVIDE     => 16,
     CLKOUT2_PHASE      => 0.000,
     CLKOUT2_DUTY_CYCLE => 0.500,
     CLKIN_PERIOD       => 50.0,
     REF_JITTER         => 0.016)
  port map
    (CLKFBOUT => pllout_clk_sys_fb,
     CLKOUT0  => pllout_clk_sys,
     CLKOUT1  => open,
     CLKOUT2  => open,
     CLKOUT3  => open,
     CLKOUT4  => open,
     CLKOUT5  => open,
     LOCKED   => sys_locked,
     RST      => '0',
     CLKFBIN  => pllout_clk_sys_fb,
     CLKIN    => clk_20m_vcxo_buf);
 
  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  cmp_sys_clk_buf : BUFG
  port map
    (O => clk_100m_sys,
     I => pllout_clk_sys);


---------------------------------------------------------------------------------------------------
--                                             RESET                                             --
---------------------------------------------------------------------------------------------------

  cmp_spec_rst_gen : spec_reset_gen
  port map
    (clk_sys_i        => clk_100m_sys,
     rst_pcie_n_a_i   => rst_n_a_i, -- reset from GN4124 chip
     rst_button_n_a_i => button1_i, -- reset from SPEC button
     rst_n_o          => rst_sys_n);

  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
     rst_sys          <= not rst_sys_n;


---------------------------------------------------------------------------------------------------
--                                     CSR WISHBONE CROSSBAR                                     --
---------------------------------------------------------------------------------------------------

--   0x00000 -> SDB
--   0x10000 -> SPEC 1-wire master
--   0x20000 -> SPEC CSR information
--   0x30000 -> masterFIP mezzanine SDB

  cmp_sdb_crossbar : xwb_sdb_crossbar
  generic map
    (g_num_masters => c_NUM_WB_SLAVES,
     g_num_slaves  => c_NUM_WB_MASTERS,
     g_registered  => true,
     g_wraparound  => true,
     g_layout      => c_INTERCONNECT_LAYOUT,
     g_sdb_addr    => c_SDB_ADDRESS)
  port map
    (clk_sys_i     => clk_100m_sys,
     rst_n_i       => rst_sys_n,
     slave_i       => cnx_slave_in,
     slave_o       => cnx_slave_out,
     master_i      => cnx_master_in,
     master_o      => cnx_master_out);


---------------------------------------------------------------------------------------------------
--                                           GN4124 CORE                                         --
---------------------------------------------------------------------------------------------------

  cmp_gn4124_core: gn4124_core
  port map
    (rst_n_a_i       => rst_n_a_i,
	 status_o        => gn4124_status,
     -- P2L Direction Source Sync DDR related signals
     p2l_clk_p_i     => p2l_clk_p_i,
     p2l_clk_n_i     => p2l_clk_n_i,
     p2l_data_i      => p2l_data_i,
     p2l_dframe_i    => p2l_dframe_i,
     p2l_valid_i     => p2l_valid_i,
     -- P2L Control
     p2l_rdy_o       => p2l_rdy_o,
     p_wr_req_i      => p_wr_req_i,
     p_wr_rdy_o      => p_wr_rdy_o,
     rx_error_o      => rx_error_o,
     -- L2P Direction Source Sync DDR related signals
     l2p_clk_p_o     => l2p_clk_p_o,
     l2p_clk_n_o     => l2p_clk_n_o,
     l2p_data_o      => l2p_data_o ,
     l2p_dframe_o    => l2p_dframe_o,
     l2p_valid_o     => l2p_valid_o,
     l2p_edb_o       => l2p_edb_o,
     -- L2P Control
     l2p_rdy_i       => l2p_rdy_i,
     l_wr_rdy_i      => l_wr_rdy_i,
     p_rd_d_rdy_i    => p_rd_d_rdy_i,
     tx_error_i      => tx_error_i,
     vc_rdy_i        => vc_rdy_i,
     -- Interrupt interface
     dma_irq_o       => open,
     irq_p_i         => '0',
     irq_p_o         => irq_p_o,
     -- CSR WISHBONE interface (master pipelined)
     csr_clk_i       => clk_100m_sys,
     csr_adr_o       => gn_wb_adr,
     csr_dat_o       => cnx_slave_in(c_MASTER_GENNUM).dat,
     csr_sel_o       => cnx_slave_in(c_MASTER_GENNUM).sel,
     csr_stb_o       => cnx_slave_in(c_MASTER_GENNUM).stb,
     csr_we_o        => cnx_slave_in(c_MASTER_GENNUM).we,
     csr_cyc_o       => cnx_slave_in(c_MASTER_GENNUM).cyc,
     csr_dat_i       => cnx_slave_out(c_MASTER_GENNUM).dat,
     csr_ack_i       => cnx_slave_out(c_MASTER_GENNUM).ack,
     csr_stall_i     => cnx_slave_out(c_MASTER_GENNUM).stall,
	 csr_err_i       => cnx_slave_out(c_MASTER_GENNUM).err,
	 csr_rty_i       => cnx_slave_out(c_MASTER_GENNUM).rty,
	 csr_int_i       => '0',
     -- DMA: not used
     dma_clk_i       => clk_100m_sys,
     dma_adr_o       => open,
     dma_cyc_o       => open,
     dma_dat_o       => open,
     dma_sel_o       => open,
     dma_stb_o       => open,
     dma_we_o        => open,
	 dma_err_i       => '0',
     dma_ack_i       => '1',
	 dma_rty_i       => '0',
	 dma_int_i       => '0',
     dma_dat_i       => (others => '0'),
     dma_stall_i     => '0',
     dma_reg_clk_i   => clk_100m_sys,
     dma_reg_adr_i   => (others => '0'),
     dma_reg_dat_i   => (others => '0'),
     dma_reg_sel_i   => (others => '0'),
     dma_reg_stb_i   => '0',
     dma_reg_we_i    => '0',
     dma_reg_cyc_i   => '0',
     dma_reg_dat_o   => open,
     dma_reg_ack_o   => open,
     dma_reg_stall_o => open);

  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  -- Convert 32-bit word address into byte address for crossbar
  cnx_slave_in(c_MASTER_GENNUM).adr <= gn_wb_adr(29 downto 0) & "00";


---------------------------------------------------------------------------------------------------
--                                         masterFIP core                                        --
---------------------------------------------------------------------------------------------------

  cmp_masterFIP_core : fmc_masterFIP_core
  generic map
    (g_span             => 32,
     g_width            => 32,
     values_for_simul   => FALSE)
  port map
    (clk_i              => clk_100m_sys,
     rst_i              => rst_sys,
     -- Bus speed
     speed_b0_i         => speed_b0_i,
     speed_b1_i         => speed_b1_i,
     -- Bus termination
     bus_term_en_n_o    => bus_term_en_n_o,
     -- FielDrive
     fd_rxcdn_i         => fd_rxcdn_i,
     fd_rxd_i           => fd_rxd_i,
     fd_txer_i          => fd_txer_i,
     fd_wdgn_i          => fd_wdgn_i,
     fd_rstn_o          => fd_rstn_o,
     fd_txck_o          => fd_txck_o,
     fd_txd_o           => fd_txd_o,
     fd_txena_o         => fd_txena,
     -- External synchronisation pulse transceiver 
     ext_sync_term_en_o => ext_sync_term_en_o,
     ext_sync_dir_o     => ext_sync_dir_o,
     ext_sync_oe_o      => ext_sync_oe_o,
     ext_sync_tst_n_o   => ext_sync_tst_n_o,
     ext_sync_i         => ext_sync_i,
     -- Power supplies for the ADC
     adc_1v8_shdn_n_o   => adc_1v8_shdn_n_o,
     adc_m5v_shdn_n_o   => adc_m5v_shdn_n_o,
     adc_5v_en_n_o      => adc_5v_en_n_o,
     adc_prim_conn_n_o  => adc_prim_conn_n_o,
     adc_sec_conn_n_o   => adc_sec_conn_n_o,
    -- WISHBONE interface with the GN4124 core
     wb_adr_i           => cnx_master_out(c_WB_SLAVE_MASTERFIP).adr,
     wb_dat_i           => cnx_master_out(c_WB_SLAVE_MASTERFIP).dat,
     wb_stb_i           => cnx_master_out(c_WB_SLAVE_MASTERFIP).stb,
     wb_we_i            => cnx_master_out(c_WB_SLAVE_MASTERFIP).we,
     wb_cyc_i           => cnx_master_out(c_WB_SLAVE_MASTERFIP).cyc,
     wb_sel_i           => cnx_master_out(c_WB_SLAVE_MASTERFIP).sel,
     wb_dat_o           => cnx_master_in(c_WB_SLAVE_MASTERFIP).dat,
     wb_ack_o           => cnx_master_in(c_WB_SLAVE_MASTERFIP).ack,
     wb_stall_o         => cnx_master_in(c_WB_SLAVE_MASTERFIP).stall,
    -- Aux
     aux_o              => aux);

  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  -- Unused wishbone signals
  cnx_master_in(c_WB_SLAVE_MASTERFIP).err   <= '0';
  cnx_master_in(c_WB_SLAVE_MASTERFIP).rty   <= '0';
  cnx_master_in(c_WB_SLAVE_MASTERFIP).int   <= '0';

  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  fd_txena_o <= fd_txena;

  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  -- LEDs font panel
  led_tx_err_n_o <= fd_txer_i;
  led_tx_act_n_o <= fd_txena;
  led_rx_err_n_o <= rx_err;
  led_rx_act_n_o <= rx_act;
  
  cmp_rx_err_extend_p: gc_extend_pulse
  generic map (g_width => 50000)
  port map
    (clk_i      => clk_100m_sys,
     rst_n_i    => rst_sys_n,
     pulse_i    => aux(0),
     extended_o => rx_err);

  cmp_rx_act_extend_p: gc_extend_pulse
  generic map (g_width => 50000)
  port map
    (clk_i      => clk_100m_sys,
     rst_n_i    => rst_sys_n,
     pulse_i    => aux(1),
     extended_o => rx_act);      


---------------------------------------------------------------------------------------------------
--                                          SPEC 1-wire                                          --
---------------------------------------------------------------------------------------------------

  cmp_carrier_onewire : xwb_onewire_master
  generic map
    (g_interface_mode      => CLASSIC,
     g_address_granularity => BYTE,
     g_num_ports           => 1,
     g_ow_btp_normal       => "5.0",
     g_ow_btp_overdrive    => "1.0")
  port map
    (clk_sys_i             => clk_100m_sys,
     rst_n_i               => rst_sys_n,
     slave_i               => cnx_master_out(c_WB_SLAVE_SPEC_ONEWIRE),
     slave_o               => cnx_master_in(c_WB_SLAVE_SPEC_ONEWIRE),
     desc_o                => open,
     owr_pwren_o           => open,
     owr_en_o              => carrier_owr_en,
     owr_i                 => carrier_owr_i);

  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  carrier_onewire_b       <= '0' when carrier_owr_en(0) = '1' else 'Z';
  carrier_owr_i(0)        <= carrier_onewire_b;


---------------------------------------------------------------------------------------------------
--                                    Carrier CSR information                                    --
---------------------------------------------------------------------------------------------------

-- Information on carrier type, mezzanine presence, pcb version

  cmp_carrier_csr : carrier_info
  port map
    (rst_n_i                           => rst_sys_n,
     clk_sys_i                         => clk_100m_sys,
     wb_adr_i                          => cnx_master_out(c_WB_SLAVE_SPEC_INFO).adr(3 downto 2),
     wb_dat_i                          => cnx_master_out(c_WB_SLAVE_SPEC_INFO).dat,
     wb_dat_o                          => cnx_master_in(c_WB_SLAVE_SPEC_INFO).dat,
     wb_cyc_i                          => cnx_master_out(c_WB_SLAVE_SPEC_INFO).cyc,
     wb_sel_i                          => cnx_master_out(c_WB_SLAVE_SPEC_INFO).sel,
     wb_stb_i                          => cnx_master_out(c_WB_SLAVE_SPEC_INFO).stb,
     wb_we_i                           => cnx_master_out(c_WB_SLAVE_SPEC_INFO).we,
     wb_ack_o                          => cnx_master_in(c_WB_SLAVE_SPEC_INFO).ack,
     wb_stall_o                        => cnx_master_in(c_WB_SLAVE_SPEC_INFO).stall,
     carrier_info_carrier_pcb_rev_i    => pcb_ver_i,
     carrier_info_carrier_reserved_i   => (others => '0'),
     carrier_info_carrier_type_i       => c_CARRIER_TYPE,
     carrier_info_stat_fmc_pres_i      => prsnt_m2c_n_i,
     carrier_info_stat_p2l_pll_lck_i   => gn4124_status(0),
     carrier_info_stat_sys_pll_lck_i   => pll_status,
     carrier_info_stat_ddr3_cal_done_i => '0',
     carrier_info_stat_reserved_i      => (others => '0'),
     carrier_info_ctrl_led_green_o     => open,
     carrier_info_ctrl_led_red_o       => open,
     carrier_info_ctrl_dac_clr_n_o     => open,
     carrier_info_ctrl_reserved_o      => open,
     carrier_info_rst_fmc0_n_o         => open,
     carrier_info_rst_fmc0_n_i         => '1',
     carrier_info_rst_fmc0_n_load_o    => open,
     carrier_info_rst_reserved_o       => open);

  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  -- Unused wishbone signals
  cnx_master_in(c_WB_SLAVE_SPEC_INFO).err <= '0';
  cnx_master_in(c_WB_SLAVE_SPEC_INFO).rty <= '0';
  cnx_master_in(c_WB_SLAVE_SPEC_INFO).int <= '0';


---------------------------------------------------------------------------------------------------
--                                           SPEC LEDs                                           --
---------------------------------------------------------------------------------------------------

  led_clk_100m_sys: process (clk_100m_sys)
  begin
    if rising_edge(clk_100m_sys) then

      if(rst_sys_n = '0') then
        led_clk_100m_aux     <= "01111111";
        led_clk_100m_divider <= (others => '0');
      else
        led_clk_100m_divider <= led_clk_100m_divider+ 1;
        if(led_clk_100m_divider = 0) then
          led_clk_100m_aux   <= led_clk_100m_aux(6 downto 0) & led_clk_100m_aux(7);
        end if;
      end if;
    end if;
  end process;

  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  led_green_o <= led_clk_100m_aux(0);

  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
  spec_red_led: gc_extend_pulse
  generic map
    (g_width    => 5000000)
  port map
    (clk_i      => clk_100m_sys,
     rst_n_i    => rst_sys_n,
     pulse_i    => (aux(0)),
     extended_o => led_red_o);


end rtl;
----------------------------------------------------------------------------------------------------
--  architecture ends
----------------------------------------------------------------------------------------------------