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-- Title          : Wishbone slave core for FMC masterFIP core registers
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-- File           : fmc_masterfip_csr.vhd
-- Author         : auto-generated by wbgen2 from fmc_masterfip_csr.wb
-- Created        : 12/04/15 19:19:40
-- Standard       : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_masterfip_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity fmc_masterfip_csr is
  port (
    rst_n_i                                  : in     std_logic;
    clk_sys_i                                : in     std_logic;
    wb_adr_i                                 : in     std_logic_vector(7 downto 0);
    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
-- Port for BIT field: 'reset of the masterFIP core' in reg: 'rstn'
    mf_rstn_core_o                           : out    std_logic;
-- Port for BIT field: 'reset of the fieldrive chip (FD_RSTN)' in reg: 'rstn'
    mf_rstn_fd_o                             : out    std_logic;
-- Ports for PASS_THROUGH field: 'reset magic value' in reg: 'rstn'
    mf_rstn_lock_o                           : out    std_logic_vector(15 downto 0);
    mf_rstn_lock_wr_o                        : out    std_logic;
-- Port for std_logic_vector field: 'debugging' in reg: 'dbg'
    mf_dbg_o                                 : out    std_logic_vector(31 downto 0);
-- Port for BIT field: '1v8_shdn_n' in reg: 'adc'
    mf_adc_1v8_shdn_n_o                      : out    std_logic;
-- Port for BIT field: 'm5v_shdn_n' in reg: 'adc'
    mf_adc_m5v_shdn_n_o                      : out    std_logic;
-- Port for BIT field: '5v_en_n' in reg: 'adc'
    mf_adc_5v_en_n_o                         : out    std_logic;
-- Port for BIT field: 'prim_conn_n' in reg: 'adc'
    mf_adc_prim_conn_n_o                     : out    std_logic;
-- Port for BIT field: 'sec_conn_n' in reg: 'adc'
    mf_adc_sec_conn_n_o                      : out    std_logic;
-- Port for BIT field: 'termination enable' in reg: 'ext sync'
    mf_ext_sync_term_en_o                    : out    std_logic;
-- Port for BIT field: 'tranceiver direction' in reg: 'ext sync'
    mf_ext_sync_dir_o                        : out    std_logic;
-- Port for BIT field: 'tranceiver output enable' in reg: 'ext sync'
    mf_ext_sync_oe_o                         : out    std_logic;
-- Port for BIT field: 'test pulse' in reg: 'ext sync'
    mf_ext_sync_tst_n_o                      : out    std_logic;
-- Port for BIT field: 'pulses counter reset' in reg: 'ext sync'
    mf_ext_sync_p_cnt_rst_o                  : out    std_logic;
-- Port for std_logic_vector field: 'ext_sync_p_cnt' in reg: 'ext sync pulses cnt'
    mf_ext_sync_p_cnt_i                      : in     std_logic_vector(31 downto 0);
-- Port for BIT field: '150ohms terination of the bus' in reg: 'bus termination'
    mf_bus_term_en_n_o                       : out    std_logic;
-- Port for std_logic_vector field: 'speed' in reg: 'speed'
    mf_speed_i                               : in     std_logic_vector(1 downto 0);
-- Port for std_logic_vector field: 'macrocycle lgth' in reg: 'macrocycle lgth'
    mf_macrocyc_lgth_o                       : out    std_logic_vector(30 downto 0);
-- Port for BIT field: 'macrocycle cnt start' in reg: 'macrocycle lgth'
    mf_macrocyc_start_o                      : out    std_logic;
-- Port for std_logic_vector field: 'turnaround time' in reg: 'turnaround lgth'
    mf_turnar_lgth_o                         : out    std_logic_vector(30 downto 0);
-- Port for BIT field: 'turnaround cnt start' in reg: 'turnaround lgth'
    mf_turnar_start_o                        : out    std_logic;
-- Port for std_logic_vector field: 'silence time' in reg: 'silence lgth'
    mf_silen_lgth_o                          : out    std_logic_vector(30 downto 0);
-- Port for BIT field: 'silence cnt start' in reg: 'silence lgth'
    mf_silen_start_o                         : out    std_logic;
-- Port for std_logic_vector field: 'macrocycle time counter' in reg: 'macrocycle time cnt'
    mf_macrocyc_time_cnt_i                   : in     std_logic_vector(30 downto 0);
-- Port for std_logic_vector field: 'number of macrocycles' in reg: 'macrocycles number cnt'
    mf_macrocyc_num_cnt_i                    : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'turnaround time counter' in reg: 'turnaround time cnt'
    mf_turnar_time_cnt_i                     : in     std_logic_vector(30 downto 0);
-- Port for std_logic_vector field: 'silence time counter' in reg: 'silence time cnt'
    mf_silen_time_cnt_i                      : in     std_logic_vector(30 downto 0);
-- Port for BIT field: 'tx rst' in reg: 'tx ctrl'
    mf_tx_ctrl_rst_o                         : out    std_logic;
-- Port for BIT field: 'tx strt' in reg: 'tx ctrl'
    mf_tx_ctrl_start_o                       : out    std_logic;
-- Port for std_logic_vector field: 'tx number of bytes' in reg: 'tx ctrl'
    mf_tx_ctrl_bytes_num_o                   : out    std_logic_vector(8 downto 0);
-- Port for BIT field: 'tx ended' in reg: 'tx status'
    mf_tx_stat_stop_i                        : in     std_logic;
-- Port for std_logic_vector field: 'tx current byte' in reg: 'tx status'
    mf_tx_stat_byte_index_i                  : in     std_logic_vector(8 downto 0);
-- Port for BIT field: 'tx enable' in reg: 'tx status'
    mf_tx_stat_ena_i                         : in     std_logic;
-- Port for BIT field: 'fd watchdog' in reg: 'fieldrive status'
    mf_fd_wdgn_i                             : in     std_logic;
-- Port for BIT field: 'fd transmitter error' in reg: 'fieldrive status'
    mf_fd_txer_i                             : in     std_logic;
-- Port for BIT field: 'rx rst' in reg: 'rx ctrl'
    mf_rx_ctrl_rst_o                         : out    std_logic;
-- Port for BIT field: 'rx preamble detected' in reg: 'rx status'
    mf_rx_stat_pream_ok_i                    : in     std_logic;
-- Port for BIT field: 'rx frame ok' in reg: 'rx status'
    mf_rx_stat_frame_ok_i                    : in     std_logic;
-- Port for BIT field: 'rx frame error' in reg: 'rx status'
    mf_rx_stat_frame_err_i                   : in     std_logic;
-- Port for std_logic_vector field: 'rx frame error code' in reg: 'rx status'
    mf_rx_stat_frame_err_code_i              : in     std_logic_vector(2 downto 0);
-- Port for std_logic_vector field: 'rx number of data bytes' in reg: 'rx status'
    mf_rx_stat_bytes_num_i                   : in     std_logic_vector(8 downto 0);
-- Port for std_logic_vector field: 'rx data ctrl byte' in reg: 'rx data ctrl byte'
    mf_rx_data_ctrl_i                        : in     std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'reg 1' in reg: 'rx data reg1'
    mf_rx_data_reg1_i                        : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg2' in reg: 'rx data reg2'
    mf_rx_data_reg2_i                        : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg3' in reg: 'rx data reg3'
    mf_rx_data_reg3_i                        : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg4' in reg: 'rx data reg4'
    mf_rx_data_reg4_i                        : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg5' in reg: 'rx data reg5'
    mf_rx_data_reg5_i                        : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg6' in reg: 'rx data reg6'
    mf_rx_data_reg6_i                        : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg7' in reg: 'rx data reg7'
    mf_rx_data_reg7_i                        : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg8' in reg: 'rx data reg8'
    mf_rx_data_reg8_i                        : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg9' in reg: 'rx data reg9'
    mf_rx_data_reg9_i                        : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg10' in reg: 'rx data reg10'
    mf_rx_data_reg10_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg11' in reg: 'rx data reg11'
    mf_rx_data_reg11_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg12' in reg: 'rx data reg12'
    mf_rx_data_reg12_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg13' in reg: 'rx data reg13'
    mf_rx_data_reg13_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg14' in reg: 'rx data reg14'
    mf_rx_data_reg14_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg15' in reg: 'rx data reg15'
    mf_rx_data_reg15_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg16' in reg: 'rx data reg16'
    mf_rx_data_reg16_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg17' in reg: 'rx data reg17'
    mf_rx_data_reg17_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg18' in reg: 'rx data reg18'
    mf_rx_data_reg18_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg19' in reg: 'rx data reg19'
    mf_rx_data_reg19_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg20' in reg: 'rx data reg20'
    mf_rx_data_reg20_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg21' in reg: 'rx data reg21'
    mf_rx_data_reg21_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg22' in reg: 'rx data reg22'
    mf_rx_data_reg22_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg23' in reg: 'rx data reg23'
    mf_rx_data_reg23_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg24' in reg: 'rx data reg24'
    mf_rx_data_reg24_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg25' in reg: 'rx data reg25'
    mf_rx_data_reg25_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg26' in reg: 'rx data reg26'
    mf_rx_data_reg26_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg27' in reg: 'rx data reg27'
    mf_rx_data_reg27_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg28' in reg: 'rx data reg28'
    mf_rx_data_reg28_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg29' in reg: 'rx data reg29'
    mf_rx_data_reg29_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg30' in reg: 'rx data reg30'
    mf_rx_data_reg30_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg31' in reg: 'rx data reg31'
    mf_rx_data_reg31_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg32' in reg: 'rx data reg32'
    mf_rx_data_reg32_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg 33' in reg: 'rx data reg33'
    mf_rx_data_reg33_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg34' in reg: 'rx data reg34'
    mf_rx_data_reg34_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg35' in reg: 'rx data reg35'
    mf_rx_data_reg35_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg36' in reg: 'rx data reg36'
    mf_rx_data_reg36_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg37' in reg: 'rx data reg37'
    mf_rx_data_reg37_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg38' in reg: 'rx data reg38'
    mf_rx_data_reg38_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg39' in reg: 'rx data reg39'
    mf_rx_data_reg39_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg40' in reg: 'rx data reg40'
    mf_rx_data_reg40_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg41' in reg: 'rx data reg41'
    mf_rx_data_reg41_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg42' in reg: 'rx data reg42'
    mf_rx_data_reg42_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg43' in reg: 'rx data reg43'
    mf_rx_data_reg43_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg44' in reg: 'rx data reg44'
    mf_rx_data_reg44_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg45' in reg: 'rx data reg45'
    mf_rx_data_reg45_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg46' in reg: 'rx data reg46'
    mf_rx_data_reg46_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg47' in reg: 'rx data reg47'
    mf_rx_data_reg47_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg48' in reg: 'rx data reg48'
    mf_rx_data_reg48_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg49' in reg: 'rx data reg49'
    mf_rx_data_reg49_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg50' in reg: 'rx data reg50'
    mf_rx_data_reg50_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg51' in reg: 'rx data reg51'
    mf_rx_data_reg51_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg52' in reg: 'rx data reg52'
    mf_rx_data_reg52_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg53' in reg: 'rx data reg53'
    mf_rx_data_reg53_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg54' in reg: 'rx data reg54'
    mf_rx_data_reg54_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg55' in reg: 'rx data reg55'
    mf_rx_data_reg55_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg56' in reg: 'rx data reg56'
    mf_rx_data_reg56_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg57' in reg: 'rx data reg57'
    mf_rx_data_reg57_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg58' in reg: 'rx data reg58'
    mf_rx_data_reg58_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg59' in reg: 'rx data reg59'
    mf_rx_data_reg59_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg60' in reg: 'rx data reg60'
    mf_rx_data_reg60_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg61' in reg: 'rx data reg61'
    mf_rx_data_reg61_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg62' in reg: 'rx data reg62'
    mf_rx_data_reg62_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg63' in reg: 'rx data reg63'
    mf_rx_data_reg63_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg64' in reg: 'rx data reg64'
    mf_rx_data_reg64_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg65' in reg: 'rx data reg65'
    mf_rx_data_reg65_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg66' in reg: 'rx data reg66'
    mf_rx_data_reg66_i                       : in     std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'tx ctrl byte' in reg: 'tx ctrl byte'
    mf_tx_data_ctrl_o                        : out    std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'reg1' in reg: 'tx data reg1'
    mf_tx_data_reg1_o                        : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg2' in reg: 'tx data reg2'
    mf_tx_data_reg2_o                        : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg3' in reg: 'tx data reg3'
    mf_tx_data_reg3_o                        : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg4' in reg: 'tx data reg4'
    mf_tx_data_reg4_o                        : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg5' in reg: 'tx data reg5'
    mf_tx_data_reg5_o                        : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg6' in reg: 'tx data reg6'
    mf_tx_data_reg6_o                        : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg7' in reg: 'tx data reg7'
    mf_tx_data_reg7_o                        : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg8' in reg: 'tx data reg8'
    mf_tx_data_reg8_o                        : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg9' in reg: 'tx data reg9'
    mf_tx_data_reg9_o                        : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg10' in reg: 'tx data reg10'
    mf_tx_data_reg10_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg11' in reg: 'tx data reg11'
    mf_tx_data_reg11_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg12' in reg: 'tx data reg12'
    mf_tx_data_reg12_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg13' in reg: 'tx data reg13'
    mf_tx_data_reg13_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg14' in reg: 'tx data reg14'
    mf_tx_data_reg14_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg15' in reg: 'tx data reg15'
    mf_tx_data_reg15_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg16' in reg: 'tx data reg16'
    mf_tx_data_reg16_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg17' in reg: 'tx data reg17'
    mf_tx_data_reg17_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg18' in reg: 'tx data reg18'
    mf_tx_data_reg18_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg19' in reg: 'tx data reg19'
    mf_tx_data_reg19_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg20' in reg: 'tx data reg20'
    mf_tx_data_reg20_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg21' in reg: 'tx data reg21'
    mf_tx_data_reg21_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg22' in reg: 'tx data reg22'
    mf_tx_data_reg22_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg23' in reg: 'tx data reg23'
    mf_tx_data_reg23_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg24' in reg: 'tx data reg24'
    mf_tx_data_reg24_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg25' in reg: 'tx data reg25'
    mf_tx_data_reg25_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg26' in reg: 'tx data reg26'
    mf_tx_data_reg26_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg27' in reg: 'tx data reg27'
    mf_tx_data_reg27_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg28' in reg: 'tx data reg28'
    mf_tx_data_reg28_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg29' in reg: 'tx data reg29'
    mf_tx_data_reg29_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg30' in reg: 'tx data reg30'
    mf_tx_data_reg30_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg31' in reg: 'tx data reg31'
    mf_tx_data_reg31_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg32' in reg: 'tx data reg32'
    mf_tx_data_reg32_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg 33' in reg: 'tx data reg33'
    mf_tx_data_reg33_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg34' in reg: 'tx data reg34'
    mf_tx_data_reg34_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg35' in reg: 'tx data reg35'
    mf_tx_data_reg35_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg36' in reg: 'tx data reg36'
    mf_tx_data_reg36_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg37' in reg: 'tx data reg37'
    mf_tx_data_reg37_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg38' in reg: 'tx data reg38'
    mf_tx_data_reg38_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg39' in reg: 'tx data reg39'
    mf_tx_data_reg39_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg40' in reg: 'tx data reg40'
    mf_tx_data_reg40_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg41' in reg: 'tx data reg41'
    mf_tx_data_reg41_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg42' in reg: 'tx data reg42'
    mf_tx_data_reg42_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg43' in reg: 'tx data reg43'
    mf_tx_data_reg43_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg44' in reg: 'tx data reg44'
    mf_tx_data_reg44_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg45' in reg: 'tx data reg45'
    mf_tx_data_reg45_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg46' in reg: 'tx data reg46'
    mf_tx_data_reg46_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg47' in reg: 'tx data reg47'
    mf_tx_data_reg47_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg48' in reg: 'tx data reg48'
    mf_tx_data_reg48_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg49' in reg: 'tx data reg49'
    mf_tx_data_reg49_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg50' in reg: 'tx data reg50'
    mf_tx_data_reg50_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg51' in reg: 'tx data reg51'
    mf_tx_data_reg51_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg52' in reg: 'tx data reg52'
    mf_tx_data_reg52_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg53' in reg: 'tx data reg53'
    mf_tx_data_reg53_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg54' in reg: 'tx data reg54'
    mf_tx_data_reg54_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg55' in reg: 'tx data reg55'
    mf_tx_data_reg55_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg56' in reg: 'tx data reg56'
    mf_tx_data_reg56_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg57' in reg: 'tx data reg57'
    mf_tx_data_reg57_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg58' in reg: 'tx data reg58'
    mf_tx_data_reg58_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg59' in reg: 'tx data reg59'
    mf_tx_data_reg59_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg60' in reg: 'tx data reg60'
    mf_tx_data_reg60_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg61' in reg: 'tx data reg61'
    mf_tx_data_reg61_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg62' in reg: 'tx data reg62'
    mf_tx_data_reg62_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg63' in reg: 'tx data reg63'
    mf_tx_data_reg63_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg64' in reg: 'tx data reg64'
    mf_tx_data_reg64_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg65' in reg: 'tx data reg65'
    mf_tx_data_reg65_o                       : out    std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'reg66' in reg: 'tx data reg66'
    mf_tx_data_reg66_o                       : out    std_logic_vector(31 downto 0)
  );
end fmc_masterfip_csr;

architecture syn of fmc_masterfip_csr is

signal mf_rstn_core_int                         : std_logic      ;
signal mf_rstn_fd_int                           : std_logic      ;
signal mf_dbg_int                               : std_logic_vector(31 downto 0);
signal mf_adc_1v8_shdn_n_int                    : std_logic      ;
signal mf_adc_m5v_shdn_n_int                    : std_logic      ;
signal mf_adc_5v_en_n_int                       : std_logic      ;
signal mf_adc_prim_conn_n_int                   : std_logic      ;
signal mf_adc_sec_conn_n_int                    : std_logic      ;
signal mf_ext_sync_term_en_int                  : std_logic      ;
signal mf_ext_sync_dir_int                      : std_logic      ;
signal mf_ext_sync_oe_int                       : std_logic      ;
signal mf_ext_sync_tst_n_int                    : std_logic      ;
signal mf_ext_sync_p_cnt_rst_int                : std_logic      ;
signal mf_bus_term_en_n_int                     : std_logic      ;
signal mf_macrocyc_lgth_int                     : std_logic_vector(30 downto 0);
signal mf_macrocyc_start_int                    : std_logic      ;
signal mf_turnar_lgth_int                       : std_logic_vector(30 downto 0);
signal mf_turnar_start_int                      : std_logic      ;
signal mf_silen_lgth_int                        : std_logic_vector(30 downto 0);
signal mf_silen_start_int                       : std_logic      ;
signal mf_tx_ctrl_rst_int                       : std_logic      ;
signal mf_tx_ctrl_start_int                     : std_logic      ;
signal mf_tx_ctrl_bytes_num_int                 : std_logic_vector(8 downto 0);
signal mf_rx_ctrl_rst_int                       : std_logic      ;
signal mf_tx_data_ctrl_int                      : std_logic_vector(7 downto 0);
signal mf_tx_data_reg1_int                      : std_logic_vector(31 downto 0);
signal mf_tx_data_reg2_int                      : std_logic_vector(31 downto 0);
signal mf_tx_data_reg3_int                      : std_logic_vector(31 downto 0);
signal mf_tx_data_reg4_int                      : std_logic_vector(31 downto 0);
signal mf_tx_data_reg5_int                      : std_logic_vector(31 downto 0);
signal mf_tx_data_reg6_int                      : std_logic_vector(31 downto 0);
signal mf_tx_data_reg7_int                      : std_logic_vector(31 downto 0);
signal mf_tx_data_reg8_int                      : std_logic_vector(31 downto 0);
signal mf_tx_data_reg9_int                      : std_logic_vector(31 downto 0);
signal mf_tx_data_reg10_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg11_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg12_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg13_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg14_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg15_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg16_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg17_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg18_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg19_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg20_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg21_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg22_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg23_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg24_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg25_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg26_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg27_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg28_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg29_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg30_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg31_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg32_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg33_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg34_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg35_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg36_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg37_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg38_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg39_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg40_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg41_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg42_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg43_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg44_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg45_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg46_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg47_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg48_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg49_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg50_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg51_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg52_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg53_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg54_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg55_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg56_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg57_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg58_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg59_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg60_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg61_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg62_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg63_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg64_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg65_int                     : std_logic_vector(31 downto 0);
signal mf_tx_data_reg66_int                     : std_logic_vector(31 downto 0);
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(7 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
  wrdata_reg <= wb_dat_i;
  bwsel_reg <= wb_sel_i;
  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
  allones <= (others => '1');
  allzeros <= (others => '0');
-- 
-- Main register bank access process.
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      mf_rstn_core_int <= '0';
      mf_rstn_fd_int <= '0';
      mf_rstn_lock_wr_o <= '0';
      mf_dbg_int <= "00000000000000000000000000000000";
      mf_adc_1v8_shdn_n_int <= '0';
      mf_adc_m5v_shdn_n_int <= '0';
      mf_adc_5v_en_n_int <= '0';
      mf_adc_prim_conn_n_int <= '0';
      mf_adc_sec_conn_n_int <= '0';
      mf_ext_sync_term_en_int <= '0';
      mf_ext_sync_dir_int <= '0';
      mf_ext_sync_oe_int <= '0';
      mf_ext_sync_tst_n_int <= '0';
      mf_ext_sync_p_cnt_rst_int <= '0';
      mf_bus_term_en_n_int <= '0';
      mf_macrocyc_lgth_int <= "0000000000000000000000000000000";
      mf_macrocyc_start_int <= '0';
      mf_turnar_lgth_int <= "0000000000000000000000000000000";
      mf_turnar_start_int <= '0';
      mf_silen_lgth_int <= "0000000000000000000000000000000";
      mf_silen_start_int <= '0';
      mf_tx_ctrl_rst_int <= '0';
      mf_tx_ctrl_start_int <= '0';
      mf_tx_ctrl_bytes_num_int <= "000000000";
      mf_rx_ctrl_rst_int <= '0';
      mf_tx_data_ctrl_int <= "00000000";
      mf_tx_data_reg1_int <= "00000000000000000000000000000000";
      mf_tx_data_reg2_int <= "00000000000000000000000000000000";
      mf_tx_data_reg3_int <= "00000000000000000000000000000000";
      mf_tx_data_reg4_int <= "00000000000000000000000000000000";
      mf_tx_data_reg5_int <= "00000000000000000000000000000000";
      mf_tx_data_reg6_int <= "00000000000000000000000000000000";
      mf_tx_data_reg7_int <= "00000000000000000000000000000000";
      mf_tx_data_reg8_int <= "00000000000000000000000000000000";
      mf_tx_data_reg9_int <= "00000000000000000000000000000000";
      mf_tx_data_reg10_int <= "00000000000000000000000000000000";
      mf_tx_data_reg11_int <= "00000000000000000000000000000000";
      mf_tx_data_reg12_int <= "00000000000000000000000000000000";
      mf_tx_data_reg13_int <= "00000000000000000000000000000000";
      mf_tx_data_reg14_int <= "00000000000000000000000000000000";
      mf_tx_data_reg15_int <= "00000000000000000000000000000000";
      mf_tx_data_reg16_int <= "00000000000000000000000000000000";
      mf_tx_data_reg17_int <= "00000000000000000000000000000000";
      mf_tx_data_reg18_int <= "00000000000000000000000000000000";
      mf_tx_data_reg19_int <= "00000000000000000000000000000000";
      mf_tx_data_reg20_int <= "00000000000000000000000000000000";
      mf_tx_data_reg21_int <= "00000000000000000000000000000000";
      mf_tx_data_reg22_int <= "00000000000000000000000000000000";
      mf_tx_data_reg23_int <= "00000000000000000000000000000000";
      mf_tx_data_reg24_int <= "00000000000000000000000000000000";
      mf_tx_data_reg25_int <= "00000000000000000000000000000000";
      mf_tx_data_reg26_int <= "00000000000000000000000000000000";
      mf_tx_data_reg27_int <= "00000000000000000000000000000000";
      mf_tx_data_reg28_int <= "00000000000000000000000000000000";
      mf_tx_data_reg29_int <= "00000000000000000000000000000000";
      mf_tx_data_reg30_int <= "00000000000000000000000000000000";
      mf_tx_data_reg31_int <= "00000000000000000000000000000000";
      mf_tx_data_reg32_int <= "00000000000000000000000000000000";
      mf_tx_data_reg33_int <= "00000000000000000000000000000000";
      mf_tx_data_reg34_int <= "00000000000000000000000000000000";
      mf_tx_data_reg35_int <= "00000000000000000000000000000000";
      mf_tx_data_reg36_int <= "00000000000000000000000000000000";
      mf_tx_data_reg37_int <= "00000000000000000000000000000000";
      mf_tx_data_reg38_int <= "00000000000000000000000000000000";
      mf_tx_data_reg39_int <= "00000000000000000000000000000000";
      mf_tx_data_reg40_int <= "00000000000000000000000000000000";
      mf_tx_data_reg41_int <= "00000000000000000000000000000000";
      mf_tx_data_reg42_int <= "00000000000000000000000000000000";
      mf_tx_data_reg43_int <= "00000000000000000000000000000000";
      mf_tx_data_reg44_int <= "00000000000000000000000000000000";
      mf_tx_data_reg45_int <= "00000000000000000000000000000000";
      mf_tx_data_reg46_int <= "00000000000000000000000000000000";
      mf_tx_data_reg47_int <= "00000000000000000000000000000000";
      mf_tx_data_reg48_int <= "00000000000000000000000000000000";
      mf_tx_data_reg49_int <= "00000000000000000000000000000000";
      mf_tx_data_reg50_int <= "00000000000000000000000000000000";
      mf_tx_data_reg51_int <= "00000000000000000000000000000000";
      mf_tx_data_reg52_int <= "00000000000000000000000000000000";
      mf_tx_data_reg53_int <= "00000000000000000000000000000000";
      mf_tx_data_reg54_int <= "00000000000000000000000000000000";
      mf_tx_data_reg55_int <= "00000000000000000000000000000000";
      mf_tx_data_reg56_int <= "00000000000000000000000000000000";
      mf_tx_data_reg57_int <= "00000000000000000000000000000000";
      mf_tx_data_reg58_int <= "00000000000000000000000000000000";
      mf_tx_data_reg59_int <= "00000000000000000000000000000000";
      mf_tx_data_reg60_int <= "00000000000000000000000000000000";
      mf_tx_data_reg61_int <= "00000000000000000000000000000000";
      mf_tx_data_reg62_int <= "00000000000000000000000000000000";
      mf_tx_data_reg63_int <= "00000000000000000000000000000000";
      mf_tx_data_reg64_int <= "00000000000000000000000000000000";
      mf_tx_data_reg65_int <= "00000000000000000000000000000000";
      mf_tx_data_reg66_int <= "00000000000000000000000000000000";
    elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          mf_rstn_lock_wr_o <= '0';
          ack_in_progress <= '0';
        else
          mf_rstn_lock_wr_o <= '0';
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(7 downto 0) is
          when "00000000" => 
            if (wb_we_i = '1') then
              mf_rstn_core_int <= wrdata_reg(0);
              mf_rstn_fd_int <= wrdata_reg(1);
              mf_rstn_lock_wr_o <= '1';
            end if;
            rddata_reg(0) <= mf_rstn_core_int;
            rddata_reg(1) <= mf_rstn_fd_int;
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00000001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= "11000000000000001111111111101110";
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00000010" => 
            if (wb_we_i = '1') then
              mf_dbg_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_dbg_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00000011" => 
            if (wb_we_i = '1') then
              mf_adc_1v8_shdn_n_int <= wrdata_reg(0);
              mf_adc_m5v_shdn_n_int <= wrdata_reg(1);
              mf_adc_5v_en_n_int <= wrdata_reg(2);
              mf_adc_prim_conn_n_int <= wrdata_reg(8);
              mf_adc_sec_conn_n_int <= wrdata_reg(9);
            end if;
            rddata_reg(0) <= mf_adc_1v8_shdn_n_int;
            rddata_reg(1) <= mf_adc_m5v_shdn_n_int;
            rddata_reg(2) <= mf_adc_5v_en_n_int;
            rddata_reg(8) <= mf_adc_prim_conn_n_int;
            rddata_reg(9) <= mf_adc_sec_conn_n_int;
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00000100" => 
            if (wb_we_i = '1') then
              mf_ext_sync_term_en_int <= wrdata_reg(0);
              mf_ext_sync_dir_int <= wrdata_reg(1);
              mf_ext_sync_oe_int <= wrdata_reg(2);
              mf_ext_sync_tst_n_int <= wrdata_reg(3);
              mf_ext_sync_p_cnt_rst_int <= wrdata_reg(8);
            end if;
            rddata_reg(0) <= mf_ext_sync_term_en_int;
            rddata_reg(1) <= mf_ext_sync_dir_int;
            rddata_reg(2) <= mf_ext_sync_oe_int;
            rddata_reg(3) <= mf_ext_sync_tst_n_int;
            rddata_reg(8) <= mf_ext_sync_p_cnt_rst_int;
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00000101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_ext_sync_p_cnt_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00000110" => 
            if (wb_we_i = '1') then
              mf_bus_term_en_n_int <= wrdata_reg(0);
            end if;
            rddata_reg(0) <= mf_bus_term_en_n_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00000111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(1 downto 0) <= mf_speed_i;
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00001000" => 
            if (wb_we_i = '1') then
              mf_macrocyc_lgth_int <= wrdata_reg(30 downto 0);
              mf_macrocyc_start_int <= wrdata_reg(31);
            end if;
            rddata_reg(30 downto 0) <= mf_macrocyc_lgth_int;
            rddata_reg(31) <= mf_macrocyc_start_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00001001" => 
            if (wb_we_i = '1') then
              mf_turnar_lgth_int <= wrdata_reg(30 downto 0);
              mf_turnar_start_int <= wrdata_reg(31);
            end if;
            rddata_reg(30 downto 0) <= mf_turnar_lgth_int;
            rddata_reg(31) <= mf_turnar_start_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00001010" => 
            if (wb_we_i = '1') then
              mf_silen_lgth_int <= wrdata_reg(30 downto 0);
              mf_silen_start_int <= wrdata_reg(31);
            end if;
            rddata_reg(30 downto 0) <= mf_silen_lgth_int;
            rddata_reg(31) <= mf_silen_start_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00001011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(30 downto 0) <= mf_macrocyc_time_cnt_i;
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00001100" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_macrocyc_num_cnt_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00001101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(30 downto 0) <= mf_turnar_time_cnt_i;
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00001110" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(30 downto 0) <= mf_silen_time_cnt_i;
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00001111" => 
            if (wb_we_i = '1') then
              mf_tx_ctrl_rst_int <= wrdata_reg(0);
              mf_tx_ctrl_start_int <= wrdata_reg(1);
              mf_tx_ctrl_bytes_num_int <= wrdata_reg(16 downto 8);
            end if;
            rddata_reg(0) <= mf_tx_ctrl_rst_int;
            rddata_reg(1) <= mf_tx_ctrl_start_int;
            rddata_reg(16 downto 8) <= mf_tx_ctrl_bytes_num_int;
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00010000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(0) <= mf_tx_stat_stop_i;
            rddata_reg(16 downto 8) <= mf_tx_stat_byte_index_i;
            rddata_reg(24) <= mf_tx_stat_ena_i;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00010001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(0) <= mf_fd_wdgn_i;
            rddata_reg(1) <= mf_fd_txer_i;
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00010010" => 
            if (wb_we_i = '1') then
              mf_rx_ctrl_rst_int <= wrdata_reg(0);
            end if;
            rddata_reg(0) <= mf_rx_ctrl_rst_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00010011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(0) <= mf_rx_stat_pream_ok_i;
            rddata_reg(1) <= mf_rx_stat_frame_ok_i;
            rddata_reg(2) <= mf_rx_stat_frame_err_i;
            rddata_reg(5 downto 3) <= mf_rx_stat_frame_err_code_i;
            rddata_reg(16 downto 8) <= mf_rx_stat_bytes_num_i;
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00010100" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(7 downto 0) <= mf_rx_data_ctrl_i;
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00010101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg1_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00010110" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg2_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00010111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg3_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00011000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg4_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00011001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg5_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00011010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg6_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00011011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg7_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00011100" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg8_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00011101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg9_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00011110" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg10_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00011111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg11_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00100000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg12_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00100001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg13_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00100010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg14_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00100011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg15_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00100100" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg16_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00100101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg17_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00100110" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg18_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00100111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg19_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00101000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg20_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00101001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg21_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00101010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg22_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00101011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg23_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00101100" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg24_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00101101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg25_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00101110" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg26_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00101111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg27_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00110000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg28_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00110001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg29_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00110010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg30_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00110011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg31_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00110100" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg32_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00110101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg33_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00110110" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg34_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00110111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg35_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00111000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg36_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00111001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg37_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00111010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg38_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00111011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg39_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00111100" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg40_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00111101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg41_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00111110" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg42_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00111111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg43_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01000000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg44_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01000001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg45_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01000010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg46_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01000011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg47_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01000100" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg48_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01000101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg49_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01000110" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg50_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01000111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg51_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01001000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg52_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01001001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg53_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01001010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg54_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01001011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg55_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01001100" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg56_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01001101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg57_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01001110" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg58_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01001111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg59_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01010000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg60_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01010001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg61_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01010010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg62_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01010011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg63_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01010100" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg64_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01010101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg65_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01010110" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= mf_rx_data_reg66_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01010111" => 
            if (wb_we_i = '1') then
              mf_tx_data_ctrl_int <= wrdata_reg(7 downto 0);
            end if;
            rddata_reg(7 downto 0) <= mf_tx_data_ctrl_int;
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01011000" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg1_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg1_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01011001" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg2_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg2_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01011010" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg3_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg3_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01011011" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg4_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg4_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01011100" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg5_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg5_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01011101" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg6_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg6_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01011110" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg7_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg7_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01011111" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg8_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg8_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01100000" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg9_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg9_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01100001" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg10_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg10_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01100010" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg11_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg11_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01100011" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg12_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg12_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01100100" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg13_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg13_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01100101" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg14_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg14_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01100110" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg15_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg15_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01100111" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg16_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg16_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01101000" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg17_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg17_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01101001" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg18_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg18_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01101010" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg19_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg19_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01101011" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg20_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg20_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01101100" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg21_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg21_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01101101" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg22_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg22_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01101110" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg23_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg23_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01101111" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg24_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg24_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01110000" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg25_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg25_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01110001" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg26_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg26_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01110010" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg27_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg27_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01110011" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg28_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg28_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01110100" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg29_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg29_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01110101" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg30_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg30_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01110110" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg31_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg31_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01110111" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg32_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg32_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01111000" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg33_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg33_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01111001" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg34_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg34_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01111010" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg35_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg35_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01111011" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg36_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg36_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01111100" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg37_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg37_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01111101" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg38_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg38_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01111110" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg39_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg39_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01111111" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg40_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg40_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10000000" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg41_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg41_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10000001" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg42_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg42_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10000010" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg43_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg43_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10000011" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg44_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg44_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10000100" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg45_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg45_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10000101" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg46_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg46_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10000110" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg47_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg47_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10000111" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg48_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg48_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10001000" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg49_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg49_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10001001" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg50_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg50_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10001010" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg51_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg51_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10001011" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg52_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg52_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10001100" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg53_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg53_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10001101" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg54_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg54_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10001110" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg55_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg55_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10001111" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg56_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg56_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10010000" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg57_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg57_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10010001" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg58_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg58_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10010010" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg59_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg59_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10010011" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg60_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg60_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10010100" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg61_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg61_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10010101" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg62_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg62_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10010110" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg63_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg63_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10010111" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg64_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg64_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10011000" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg65_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg65_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10011001" => 
            if (wb_we_i = '1') then
              mf_tx_data_reg66_int <= wrdata_reg(31 downto 0);
            end if;
            rddata_reg(31 downto 0) <= mf_tx_data_reg66_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_dat_o <= rddata_reg;
-- reset of the masterFIP core
  mf_rstn_core_o <= mf_rstn_core_int;
-- reset of the fieldrive chip (FD_RSTN)
  mf_rstn_fd_o <= mf_rstn_fd_int;
-- reset magic value
-- pass-through field: reset magic value in register: rstn
  mf_rstn_lock_o <= wrdata_reg(31 downto 16);
-- debugging
  mf_dbg_o <= mf_dbg_int;
-- 1v8_shdn_n
  mf_adc_1v8_shdn_n_o <= mf_adc_1v8_shdn_n_int;
-- m5v_shdn_n
  mf_adc_m5v_shdn_n_o <= mf_adc_m5v_shdn_n_int;
-- 5v_en_n
  mf_adc_5v_en_n_o <= mf_adc_5v_en_n_int;
-- prim_conn_n
  mf_adc_prim_conn_n_o <= mf_adc_prim_conn_n_int;
-- sec_conn_n
  mf_adc_sec_conn_n_o <= mf_adc_sec_conn_n_int;
-- termination enable
  mf_ext_sync_term_en_o <= mf_ext_sync_term_en_int;
-- tranceiver direction
  mf_ext_sync_dir_o <= mf_ext_sync_dir_int;
-- tranceiver output enable
  mf_ext_sync_oe_o <= mf_ext_sync_oe_int;
-- test pulse
  mf_ext_sync_tst_n_o <= mf_ext_sync_tst_n_int;
-- pulses counter reset
  mf_ext_sync_p_cnt_rst_o <= mf_ext_sync_p_cnt_rst_int;
-- ext_sync_p_cnt
-- 150ohms terination of the bus
  mf_bus_term_en_n_o <= mf_bus_term_en_n_int;
-- speed
-- macrocycle lgth
  mf_macrocyc_lgth_o <= mf_macrocyc_lgth_int;
-- macrocycle cnt start
  mf_macrocyc_start_o <= mf_macrocyc_start_int;
-- turnaround time
  mf_turnar_lgth_o <= mf_turnar_lgth_int;
-- turnaround cnt start
  mf_turnar_start_o <= mf_turnar_start_int;
-- silence time
  mf_silen_lgth_o <= mf_silen_lgth_int;
-- silence cnt start
  mf_silen_start_o <= mf_silen_start_int;
-- macrocycle time counter
-- number of macrocycles
-- turnaround time counter
-- silence time counter
-- tx rst
  mf_tx_ctrl_rst_o <= mf_tx_ctrl_rst_int;
-- tx strt
  mf_tx_ctrl_start_o <= mf_tx_ctrl_start_int;
-- tx number of bytes
  mf_tx_ctrl_bytes_num_o <= mf_tx_ctrl_bytes_num_int;
-- tx ended
-- tx current byte
-- tx enable
-- fd watchdog
-- fd transmitter error
-- rx rst
  mf_rx_ctrl_rst_o <= mf_rx_ctrl_rst_int;
-- rx preamble detected
-- rx frame ok
-- rx frame error
-- rx frame error code
-- rx number of data bytes
-- rx data ctrl byte
-- reg 1
-- reg2
-- reg3
-- reg4
-- reg5
-- reg6
-- reg7
-- reg8
-- reg9
-- reg10
-- reg11
-- reg12
-- reg13
-- reg14
-- reg15
-- reg16
-- reg17
-- reg18
-- reg19
-- reg20
-- reg21
-- reg22
-- reg23
-- reg24
-- reg25
-- reg26
-- reg27
-- reg28
-- reg29
-- reg30
-- reg31
-- reg32
-- reg 33
-- reg34
-- reg35
-- reg36
-- reg37
-- reg38
-- reg39
-- reg40
-- reg41
-- reg42
-- reg43
-- reg44
-- reg45
-- reg46
-- reg47
-- reg48
-- reg49
-- reg50
-- reg51
-- reg52
-- reg53
-- reg54
-- reg55
-- reg56
-- reg57
-- reg58
-- reg59
-- reg60
-- reg61
-- reg62
-- reg63
-- reg64
-- reg65
-- reg66
-- tx ctrl byte
  mf_tx_data_ctrl_o <= mf_tx_data_ctrl_int;
-- reg1
  mf_tx_data_reg1_o <= mf_tx_data_reg1_int;
-- reg2
  mf_tx_data_reg2_o <= mf_tx_data_reg2_int;
-- reg3
  mf_tx_data_reg3_o <= mf_tx_data_reg3_int;
-- reg4
  mf_tx_data_reg4_o <= mf_tx_data_reg4_int;
-- reg5
  mf_tx_data_reg5_o <= mf_tx_data_reg5_int;
-- reg6
  mf_tx_data_reg6_o <= mf_tx_data_reg6_int;
-- reg7
  mf_tx_data_reg7_o <= mf_tx_data_reg7_int;
-- reg8
  mf_tx_data_reg8_o <= mf_tx_data_reg8_int;
-- reg9
  mf_tx_data_reg9_o <= mf_tx_data_reg9_int;
-- reg10
  mf_tx_data_reg10_o <= mf_tx_data_reg10_int;
-- reg11
  mf_tx_data_reg11_o <= mf_tx_data_reg11_int;
-- reg12
  mf_tx_data_reg12_o <= mf_tx_data_reg12_int;
-- reg13
  mf_tx_data_reg13_o <= mf_tx_data_reg13_int;
-- reg14
  mf_tx_data_reg14_o <= mf_tx_data_reg14_int;
-- reg15
  mf_tx_data_reg15_o <= mf_tx_data_reg15_int;
-- reg16
  mf_tx_data_reg16_o <= mf_tx_data_reg16_int;
-- reg17
  mf_tx_data_reg17_o <= mf_tx_data_reg17_int;
-- reg18
  mf_tx_data_reg18_o <= mf_tx_data_reg18_int;
-- reg19
  mf_tx_data_reg19_o <= mf_tx_data_reg19_int;
-- reg20
  mf_tx_data_reg20_o <= mf_tx_data_reg20_int;
-- reg21
  mf_tx_data_reg21_o <= mf_tx_data_reg21_int;
-- reg22
  mf_tx_data_reg22_o <= mf_tx_data_reg22_int;
-- reg23
  mf_tx_data_reg23_o <= mf_tx_data_reg23_int;
-- reg24
  mf_tx_data_reg24_o <= mf_tx_data_reg24_int;
-- reg25
  mf_tx_data_reg25_o <= mf_tx_data_reg25_int;
-- reg26
  mf_tx_data_reg26_o <= mf_tx_data_reg26_int;
-- reg27
  mf_tx_data_reg27_o <= mf_tx_data_reg27_int;
-- reg28
  mf_tx_data_reg28_o <= mf_tx_data_reg28_int;
-- reg29
  mf_tx_data_reg29_o <= mf_tx_data_reg29_int;
-- reg30
  mf_tx_data_reg30_o <= mf_tx_data_reg30_int;
-- reg31
  mf_tx_data_reg31_o <= mf_tx_data_reg31_int;
-- reg32
  mf_tx_data_reg32_o <= mf_tx_data_reg32_int;
-- reg 33
  mf_tx_data_reg33_o <= mf_tx_data_reg33_int;
-- reg34
  mf_tx_data_reg34_o <= mf_tx_data_reg34_int;
-- reg35
  mf_tx_data_reg35_o <= mf_tx_data_reg35_int;
-- reg36
  mf_tx_data_reg36_o <= mf_tx_data_reg36_int;
-- reg37
  mf_tx_data_reg37_o <= mf_tx_data_reg37_int;
-- reg38
  mf_tx_data_reg38_o <= mf_tx_data_reg38_int;
-- reg39
  mf_tx_data_reg39_o <= mf_tx_data_reg39_int;
-- reg40
  mf_tx_data_reg40_o <= mf_tx_data_reg40_int;
-- reg41
  mf_tx_data_reg41_o <= mf_tx_data_reg41_int;
-- reg42
  mf_tx_data_reg42_o <= mf_tx_data_reg42_int;
-- reg43
  mf_tx_data_reg43_o <= mf_tx_data_reg43_int;
-- reg44
  mf_tx_data_reg44_o <= mf_tx_data_reg44_int;
-- reg45
  mf_tx_data_reg45_o <= mf_tx_data_reg45_int;
-- reg46
  mf_tx_data_reg46_o <= mf_tx_data_reg46_int;
-- reg47
  mf_tx_data_reg47_o <= mf_tx_data_reg47_int;
-- reg48
  mf_tx_data_reg48_o <= mf_tx_data_reg48_int;
-- reg49
  mf_tx_data_reg49_o <= mf_tx_data_reg49_int;
-- reg50
  mf_tx_data_reg50_o <= mf_tx_data_reg50_int;
-- reg51
  mf_tx_data_reg51_o <= mf_tx_data_reg51_int;
-- reg52
  mf_tx_data_reg52_o <= mf_tx_data_reg52_int;
-- reg53
  mf_tx_data_reg53_o <= mf_tx_data_reg53_int;
-- reg54
  mf_tx_data_reg54_o <= mf_tx_data_reg54_int;
-- reg55
  mf_tx_data_reg55_o <= mf_tx_data_reg55_int;
-- reg56
  mf_tx_data_reg56_o <= mf_tx_data_reg56_int;
-- reg57
  mf_tx_data_reg57_o <= mf_tx_data_reg57_int;
-- reg58
  mf_tx_data_reg58_o <= mf_tx_data_reg58_int;
-- reg59
  mf_tx_data_reg59_o <= mf_tx_data_reg59_int;
-- reg60
  mf_tx_data_reg60_o <= mf_tx_data_reg60_int;
-- reg61
  mf_tx_data_reg61_o <= mf_tx_data_reg61_int;
-- reg62
  mf_tx_data_reg62_o <= mf_tx_data_reg62_int;
-- reg63
  mf_tx_data_reg63_o <= mf_tx_data_reg63_int;
-- reg64
  mf_tx_data_reg64_o <= mf_tx_data_reg64_int;
-- reg65
  mf_tx_data_reg65_o <= mf_tx_data_reg65_int;
-- reg66
  mf_tx_data_reg66_o <= mf_tx_data_reg66_int;
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;
