/*
  Register definitions for slave core: masterFIP EIC

  * File           : /home/gumas/projects/cti/fmcmasterfip/project/software/regs/masterfip_eic.h
  * Author         : auto-generated by wbgen2 from /home/gumas/projects/cti/fmcmasterfip/project/gateware/ip_cores/masterfip-gw/rtl/wbgen/fmc_masterfip_eic.wb
  * Created        : Mon Feb  8 14:26:21 2016
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/fmcmasterfip/project/gateware/ip_cores/masterfip-gw/rtl/wbgen/fmc_masterfip_eic.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_/HOME/GUMAS/PROJECTS/CTI/FMCMASTERFIP/PROJECT/GATEWARE/IP_CORES/MASTERFIP-GW/RTL/WBGEN/FMC_MASTERFIP_EIC_WB
#define __WBGEN2_REGDEFS_/HOME/GUMAS/PROJECTS/CTI/FMCMASTERFIP/PROJECT/GATEWARE/IP_CORES/MASTERFIP-GW/RTL/WBGEN/FMC_MASTERFIP_EIC_WB

#include <inttypes.h>

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: Interrupt disable register */

/* definitions for field: start new macrocycle in reg: Interrupt disable register */
#define FMC_MASTERFIP_EIC_EIC_IDR_MACROCY_START WBGEN2_GEN_MASK(0, 1)

/* definitions for field: silence time expired in reg: Interrupt disable register */
#define FMC_MASTERFIP_EIC_EIC_IDR_SILEN_TIME_EXPIRE WBGEN2_GEN_MASK(1, 1)

/* definitions for field: turnaround time expired in reg: Interrupt disable register */
#define FMC_MASTERFIP_EIC_EIC_IDR_TURNAR_TIME_EXPIRE WBGEN2_GEN_MASK(2, 1)

/* definitions for field: end of frame transmission in reg: Interrupt disable register */
#define FMC_MASTERFIP_EIC_EIC_IDR_TX_COMPLETED WBGEN2_GEN_MASK(3, 1)

/* definitions for field: reception of a new fss in reg: Interrupt disable register */
#define FMC_MASTERFIP_EIC_EIC_IDR_RX_FSS_OK   WBGEN2_GEN_MASK(4, 1)

/* definitions for field: reception of a new complete frame in reg: Interrupt disable register */
#define FMC_MASTERFIP_EIC_EIC_IDR_RX_FRAME_OK WBGEN2_GEN_MASK(5, 1)

/* definitions for field: reception of a frame with wrong crc in reg: Interrupt disable register */
#define FMC_MASTERFIP_EIC_EIC_IDR_RX_CRC_WRONG WBGEN2_GEN_MASK(6, 1)

/* definitions for register: Interrupt enable register */

/* definitions for field: start new macrocycle in reg: Interrupt enable register */
#define FMC_MASTERFIP_EIC_EIC_IER_MACROCY_START WBGEN2_GEN_MASK(0, 1)

/* definitions for field: silence time expired in reg: Interrupt enable register */
#define FMC_MASTERFIP_EIC_EIC_IER_SILEN_TIME_EXPIRE WBGEN2_GEN_MASK(1, 1)

/* definitions for field: turnaround time expired in reg: Interrupt enable register */
#define FMC_MASTERFIP_EIC_EIC_IER_TURNAR_TIME_EXPIRE WBGEN2_GEN_MASK(2, 1)

/* definitions for field: end of frame transmission in reg: Interrupt enable register */
#define FMC_MASTERFIP_EIC_EIC_IER_TX_COMPLETED WBGEN2_GEN_MASK(3, 1)

/* definitions for field: reception of a new fss in reg: Interrupt enable register */
#define FMC_MASTERFIP_EIC_EIC_IER_RX_FSS_OK   WBGEN2_GEN_MASK(4, 1)

/* definitions for field: reception of a new complete frame in reg: Interrupt enable register */
#define FMC_MASTERFIP_EIC_EIC_IER_RX_FRAME_OK WBGEN2_GEN_MASK(5, 1)

/* definitions for field: reception of a frame with wrong crc in reg: Interrupt enable register */
#define FMC_MASTERFIP_EIC_EIC_IER_RX_CRC_WRONG WBGEN2_GEN_MASK(6, 1)

/* definitions for register: Interrupt mask register */

/* definitions for field: start new macrocycle in reg: Interrupt mask register */
#define FMC_MASTERFIP_EIC_EIC_IMR_MACROCY_START WBGEN2_GEN_MASK(0, 1)

/* definitions for field: silence time expired in reg: Interrupt mask register */
#define FMC_MASTERFIP_EIC_EIC_IMR_SILEN_TIME_EXPIRE WBGEN2_GEN_MASK(1, 1)

/* definitions for field: turnaround time expired in reg: Interrupt mask register */
#define FMC_MASTERFIP_EIC_EIC_IMR_TURNAR_TIME_EXPIRE WBGEN2_GEN_MASK(2, 1)

/* definitions for field: end of frame transmission in reg: Interrupt mask register */
#define FMC_MASTERFIP_EIC_EIC_IMR_TX_COMPLETED WBGEN2_GEN_MASK(3, 1)

/* definitions for field: reception of a new fss in reg: Interrupt mask register */
#define FMC_MASTERFIP_EIC_EIC_IMR_RX_FSS_OK   WBGEN2_GEN_MASK(4, 1)

/* definitions for field: reception of a new complete frame in reg: Interrupt mask register */
#define FMC_MASTERFIP_EIC_EIC_IMR_RX_FRAME_OK WBGEN2_GEN_MASK(5, 1)

/* definitions for field: reception of a frame with wrong crc in reg: Interrupt mask register */
#define FMC_MASTERFIP_EIC_EIC_IMR_RX_CRC_WRONG WBGEN2_GEN_MASK(6, 1)

/* definitions for register: Interrupt status register */

/* definitions for field: start new macrocycle in reg: Interrupt status register */
#define FMC_MASTERFIP_EIC_EIC_ISR_MACROCY_START WBGEN2_GEN_MASK(0, 1)

/* definitions for field: silence time expired in reg: Interrupt status register */
#define FMC_MASTERFIP_EIC_EIC_ISR_SILEN_TIME_EXPIRE WBGEN2_GEN_MASK(1, 1)

/* definitions for field: turnaround time expired in reg: Interrupt status register */
#define FMC_MASTERFIP_EIC_EIC_ISR_TURNAR_TIME_EXPIRE WBGEN2_GEN_MASK(2, 1)

/* definitions for field: end of frame transmission in reg: Interrupt status register */
#define FMC_MASTERFIP_EIC_EIC_ISR_TX_COMPLETED WBGEN2_GEN_MASK(3, 1)

/* definitions for field: reception of a new fss in reg: Interrupt status register */
#define FMC_MASTERFIP_EIC_EIC_ISR_RX_FSS_OK   WBGEN2_GEN_MASK(4, 1)

/* definitions for field: reception of a new complete frame in reg: Interrupt status register */
#define FMC_MASTERFIP_EIC_EIC_ISR_RX_FRAME_OK WBGEN2_GEN_MASK(5, 1)

/* definitions for field: reception of a frame with wrong crc in reg: Interrupt status register */
#define FMC_MASTERFIP_EIC_EIC_ISR_RX_CRC_WRONG WBGEN2_GEN_MASK(6, 1)
/* [0x0]: REG Interrupt disable register */
#define FMC_MASTERFIP_EIC_REG_EIC_IDR 0x00000000
/* [0x4]: REG Interrupt enable register */
#define FMC_MASTERFIP_EIC_REG_EIC_IER 0x00000004
/* [0x8]: REG Interrupt mask register */
#define FMC_MASTERFIP_EIC_REG_EIC_IMR 0x00000008
/* [0xc]: REG Interrupt status register */
#define FMC_MASTERFIP_EIC_REG_EIC_ISR 0x0000000c
#endif
