peripheral {
  name = "FMC masterFIP PTS registers";
  description = "Wishbone slave for FMC masterFIP PTS";
  hdl_entity = "masterfip_pts_csr";

  prefix = "mfpts";


  --------------------------------------------------------------------------------------------------
   reg {
      name = "rst";
      prefix = "rst";
      description = "software reset of the masterFIP core";

      field {
         name = "reset of the masterFIP core";
         description = "write 1: generates a 1-clk-tick-long (10ns) masterFIP core reset;\
                    note: there is no need to clear the bit before writing another '1'";
         type = MONOSTABLE;
         prefix = "core"; 
      };
      
   };

-------------------------------------------------------------------------------
--                               external synch                              --
-------------------------------------------------------------------------------
  reg {
    name = "ext sync";
    prefix = "ext_sync";
  
    field {
      name = "termination enable";
      prefix = "term_en";
      description = "write 0: disable 50ohms termination of the external sync pulse\
                     write 1: enable  50ohms termination of the external sync pulse";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
  
    field {
      name = "transceiver direction";
      prefix = "dir";
      description = "write 0: normal operation (input)\
                     write 1: test mode where a pulse from the FPGA can be output to the front panel LEMO connector";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
  
    field {
      name = "transceiver output enable";
      prefix = "oe";
      description = " This line is negated in the GW in order to correctly control the relay\
                      write 1: the external sync pulse arrives to the FPGA\
                      write 0: the external sync pulse does not arrive to the FPGA";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };

    
    field {
      name = "External sync output value (when buffer is switched)";
      prefix = "output_value";
      description = "Value outputted then sync is set to output direction";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };
      
    field {
      name = "FPGA IO direction";
      prefix = "fpga_io_dir";
      description = "Direction of FPGA IO";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };

    field {
      name        = "raw_input";
      prefix      = "raw_input";
      description = "External sync input value. Only valid when direction is set to input";
      type        = BIT;
      access_bus  = READ_ONLY;
      access_dev  = WRITE_ONLY;
    };  

  };


-------------------------------------------------------------------------------
--                         fieldrive status signals                          --
-------------------------------------------------------------------------------

  reg {
    name = "PTS options";
    prefix = "tx_corrupt";
  
    field {
      name = "enable";
      description = "When corrupt is set to 1 serial tx data is forced to 0.";
      prefix = "enable";
      type = BIT;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
    };  
  };

  reg {
    name = "fieldrive status";
    prefix = "fd";
  
    field {
      name = "fd watchdog";
      description = "fd_wdgn input from the fieldrive chip";
      prefix = "wdgn";
      type = BIT;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    }; 
    field {
      name = "fd watchdog latched";
      description = "Active watchdog state is latched. Register is reseted by reset core and reset fd";
      prefix = "wdgn_latch";
      type = BIT;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };  
    field {
      name = "fd carrier detect";
      description = "CDn input from the fieldrive chip";
      prefix = "cd_n";
      type = BIT;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };  
    field {
      name = "fd transmitter error";
      description = "fd_txer input from the fieldrive chip";
      prefix = "txer";
      type = BIT;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };  
  };


  reg{
    name = "fieldrive rx not carrier detect  counter";
    prefix = "fd_rxcdn_cnt";

    field {
      name = "fieldrive rx not carrier detect  counter";
      description = "Number of RX NOT carrier detect periods. Counter is reset by macrocycle, core reset and fd reset";
      type = SLV;
      size = 32;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };    
  };  

  reg{
    name = "fieldrive tx error counter";
    prefix = "fd_txerr_cnt";

    field {
      name = "fieldrive tx error counter";
      description = "Number of TX Errors. Counter is reset by macrocycle, core reset and fd reset";
      type = SLV;
      size = 32;
      access_bus = READ_ONLY;
      access_dev = WRITE_ONLY;
    };    
  };

  
};