Commit 4a5088eb authored by Marek Gumiński's avatar Marek Gumiński

Removed unused gateware submodules.

Added masterfip-gw submodule.
Updated other submodules to work with masterfip-gw.
Generated csr files for new masterfip_core.
Updated ise project.
Verified implementation of spec_masterfip_pts.
parent 2c46e85b
[submodule "gateware/ip_cores/general-cores"]
path = gateware/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
[submodule "gateware/ip_cores/fmc-adc-100m14b4cha-gw"]
path = gateware/ip_cores/fmc-adc-100m14b4cha-gw
url = git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha/fmc-adc-100m14b4cha-gw.git
[submodule "gateware/ip_cores/gn4124-core"]
path = gateware/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
......@@ -13,9 +10,6 @@
[submodule "gateware/ip_cores/wr-node-core"]
path = gateware/ip_cores/wr-node-core
url = git://ohwr.org/white-rabbit/wr-node-core.git
[submodule "gateware/ip_cores/ddr3-sp6-core"]
path = gateware/ip_cores/ddr3-sp6-core
url = git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git
[submodule "software/spec-sw"]
path = software/spec-sw
url = git://ohwr.org/fmc-projects/spec/spec-sw.git
......@@ -28,3 +22,9 @@
[submodule "gateware/ip_cores/gw-masterfip"]
path = gateware/ip_cores/gw-masterfip
url = git://ohwr.org/cern-fip/masterfip/masterfip-gw.git
[submodule "gateware/ip_cores/etherbone-core"]
path = gateware/ip_cores/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git
[submodule "gateware/ip_cores/nanofip-gateware"]
path = gateware/ip_cores/nanofip-gateware
url = git://ohwr.org/cern-fip/nanofip/nanofip-gateware.git
ddr3-sp6-core @ 7496ea02
Subproject commit 7496ea0237449047f452be15567546b5dff364f5
etherbone-core @ c1e676dc
Subproject commit c1e676dc9d35028910c50431d70328e522396c89
Subproject commit 94c7ce240aad469c5ea7e6a821ffe4697b94da46
general-cores @ 1c2dd12b
Subproject commit 2f134e412e762fd8970c673bf4ea77c3e162e9bb
Subproject commit 1c2dd12b1bceeab3b32b41c3522931c658ad15a7
gn4124-core @ e3a0bf97
Subproject commit ffea5479190c09938cbba9b7076953c5c41645f3
Subproject commit e3a0bf97e125020c83bff6e40199a717e7fda738
nanofip-gateware @ 752512a8
Subproject commit 752512a82a05ce5ac4c69ad19f68921762bdd512
wr-cores @ d0d4d09d
Subproject commit f3437dd82dd2267c63f3df341daac8972184cd9e
Subproject commit d0d4d09d5f0355dfc6c078171bc6856e580a7496
wr-node-core @ 96a78592
Subproject commit 13d98e48f9870bfa6a914c1eba698d7d90c1c6e8
Subproject commit 96a78592b4d20140bf13662476605ab7e96d7710
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/fmc_masterfip_csr_pts.vhd
-- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
-- Created : Tue Mar 7 12:59:02 2017
-- Created : Wed Mar 15 14:47:49 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
......
This source diff could not be displayed because it is too large. You can view the blob instead.
#----------------------------------------
# BANK 0 P2V5: Clock
#----------------------------------------
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# BANK 1 P1V8: PCIe interface
#----------------------------------------
NET "l_rst_n_i" LOC = N20;
NET "l_rst_n_i" IOSTANDARD = "LVCMOS18";
NET "L2P_CLKN_o" LOC = K22;
NET "L2P_CLKN_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP_o" LOC = K21;
NET "L2P_CLKP_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_DFRAME_o" LOC = U22;
NET "L2P_DFRAME_o" IOSTANDARD = "SSTL18_I";
NET "L2P_EDB_o" LOC = U20;
NET "L2P_EDB_o" IOSTANDARD = "SSTL18_I";
NET "L2P_RDY_i" LOC = U19;
NET "L2P_RDY_i" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID_o" LOC = T18;
NET "L2P_VALID_o" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY_i[0]" LOC = R20;
NET "L_WR_RDY_i[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY_i[1]" LOC = T22;
NET "L_WR_RDY_i[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_CLKN_i" LOC = M19;
NET "P2L_CLKN_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP_i" LOC = M20;
NET "P2L_CLKP_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DFRAME_i" LOC = J22;
NET "P2L_DFRAME_i" IOSTANDARD = "SSTL18_I";
NET "P2L_RDY_o" LOC = J16;
NET "P2L_RDY_o" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID_i" LOC = L19;
NET "P2L_VALID_i" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY_i[0]" LOC = N16;
NET "P_RD_D_RDY_i[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY_i[1]" LOC = P19;
NET "P_RD_D_RDY_i[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY_o[0]" LOC = L15;
NET "P_WR_RDY_o[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY_o[1]" LOC = K16;
NET "P_WR_RDY_o[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ_i[0]" LOC = M22;
NET "P_WR_REQ_i[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ_i[1]" LOC = M21;
NET "P_WR_REQ_i[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR_o" LOC = J17;
NET "RX_ERROR_o" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR_i" LOC = M17;
NET "TX_ERROR_i" IOSTANDARD = "SSTL18_I";
NET "VC_RDY_i[0]" LOC = B21;
NET "VC_RDY_i[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY_i[1]" LOC = B22;
NET "VC_RDY_i[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[0]" LOC = P16;
NET "L2P_DATA_o[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[1]" LOC = P21;
NET "L2P_DATA_o[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[2]" LOC = P18;
NET "L2P_DATA_o[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[3]" LOC = T20;
NET "L2P_DATA_o[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[4]" LOC = V21;
NET "L2P_DATA_o[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[5]" LOC = V19;
NET "L2P_DATA_o[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[6]" LOC = W22;
NET "L2P_DATA_o[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[7]" LOC = Y22;
NET "L2P_DATA_o[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[8]" LOC = P22;
NET "L2P_DATA_o[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[9]" LOC = R22;
NET "L2P_DATA_o[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[10]" LOC = T21;
NET "L2P_DATA_o[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[11]" LOC = T19;
NET "L2P_DATA_o[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[12]" LOC = V22;
NET "L2P_DATA_o[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[13]" LOC = V20;
NET "L2P_DATA_o[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[14]" LOC = W20;
NET "L2P_DATA_o[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA_o[15]" LOC = Y21;
NET "L2P_DATA_o[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[0]" LOC = K20;
NET "P2L_DATA_i[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[1]" LOC = H22;
NET "P2L_DATA_i[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[2]" LOC = H21;
NET "P2L_DATA_i[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[3]" LOC = L17;
NET "P2L_DATA_i[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[4]" LOC = K17;
NET "P2L_DATA_i[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[5]" LOC = G22;
NET "P2L_DATA_i[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[6]" LOC = G20;
NET "P2L_DATA_i[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[7]" LOC = K18;
NET "P2L_DATA_i[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[8]" LOC = K19;
NET "P2L_DATA_i[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[9]" LOC = H20;
NET "P2L_DATA_i[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[10]" LOC = J19;
NET "P2L_DATA_i[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[11]" LOC = E22;
NET "P2L_DATA_i[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[12]" LOC = E20;
NET "P2L_DATA_i[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[13]" LOC = F22;
NET "P2L_DATA_i[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[14]" LOC = F21;
NET "P2L_DATA_i[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA_i[15]" LOC = H19;
NET "P2L_DATA_i[15]" IOSTANDARD = "SSTL18_I";
#----------------------------------------
# BANK 0 P2V5: SPEC LEDs
#----------------------------------------
NET "GPIO_b[1]" LOC = U16;
NET "GPIO_b[1]" IOSTANDARD = "LVCMOS25";
NET "GPIO_b[0]" LOC = AB19;
NET "GPIO_b[0]" IOSTANDARD = "LVCMOS25";
NET "LED_RED_O" LOC = D5;
NET "LED_RED_O" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN_O" LOC = E5;
NET "LED_GREEN_O" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# BANK 0 P2V5: SPEC DAC
#----------------------------------------
NET "dac_cs_n_o[0]" LOC = A3;
NET "dac_cs_n_o[0]" IOSTANDARD = "LVCMOS25";
NET "dac_cs_n_o[1]" LOC = B3;
NET "dac_cs_n_o[1]" IOSTANDARD = "LVCMOS25";
NET "dac_sclk_o" LOC = A4;
NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Bank 2 P2V5: FMC
#----------------------------------------
NET "fmc_prsnt_m2c_n_i" LOC = AB14;
NET "fmc_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "fmc_onewire_b" LOC = "C18";
NET "fmc_onewire_b" IOSTANDARD = "LVCMOS25";
NET "fd_rstn_o" LOC = "Y18";
NET "fd_rstn_o" IOSTANDARD = "LVCMOS25";
NET "fd_txd_o" LOC = "T14";
NET "fd_txd_o" IOSTANDARD = "LVCMOS25";
NET "fd_txck_o" LOC = "W17";
NET "fd_txck_o" IOSTANDARD = "LVCMOS25";
NET "fd_txer_i" LOC = "T11";
NET "fd_txer_i" IOSTANDARD = "LVCMOS25";
NET "fd_rxcdn_i" LOC = "T15";
NET "fd_rxcdn_i" IOSTANDARD = "LVCMOS25";
NET "fd_rxd_i" LOC = "U15";
NET "fd_rxd_i" IOSTANDARD = "LVCMOS25";
NET "fd_wdgn_i" LOC = "R11";
NET "fd_wdgn_i" IOSTANDARD = "LVCMOS25";
NET "fd_txena_o" LOC = "R13";
NET "fd_txena_o" IOSTANDARD = "LVCMOS25";
NET "speed_b0_i" LOC = Y5;
NET "speed_b0_i" IOSTANDARD = "LVCMOS25";
NET "speed_b1_i" LOC = AB5;
NET "speed_b1_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_term_en_o" LOC = AB13;
NET "ext_sync_term_en_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_i" LOC = T8;
NET "ext_sync_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_oe_n_o" LOC = W6;
NET "ext_sync_oe_n_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_dir_o" LOC = Y6;
NET "ext_sync_dir_o" IOSTANDARD = "LVCMOS25";
NET "adc_1v8_shdn_n_o" LOC = V17;
NET "adc_1v8_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_m5v_shdn_n_o" LOC = W18;
NET "adc_m5v_shdn_n_o" IOSTANDARD = "LVCMOS25";
NET "adc_5v_en_n_o" LOC = R8;
NET "adc_5v_en_n_o" IOSTANDARD = "LVCMOS25";
NET "led_tx_err_n_o" LOC = C19;
NET "led_tx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_tx_act_n_o" LOC = A19;
NET "led_tx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_err_n_o" LOC = B20;
NET "led_rx_err_n_o" IOSTANDARD = "LVCMOS25";
NET "led_rx_act_n_o" LOC = A20;
NET "led_rx_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_sync_act_n_o" LOC = W10;
NET "led_sync_act_n_o" IOSTANDARD = "LVCMOS25";
NET "led_sync_err_n_o" LOC = Y10;
NET "led_sync_err_n_o" IOSTANDARD = "LVCMOS25";
NET "tp1_o" LOC = AA16;
NET "tp1_o" IOSTANDARD = "LVCMOS25";
NET "tp2_o" LOC = AB16;
NET "tp2_o" IOSTANDARD = "LVCMOS25";
NET "tp3_o" LOC = Y17;
NET "tp3_o" IOSTANDARD = "LVCMOS25";
NET "tp4_o" LOC = AB17;
NET "tp4_o" IOSTANDARD = "LVCMOS25";
# <ucfgen_end>
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2015/07/27
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk = PERIOD "U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_feedback = PERIOD "U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback" 5 ns HIGH 50%;
NET "l_rst_n_i" TIG;
NET "cmp_mock_turtle/gen_with_gennum.U_GN4124_Core/rst_*" TIG;
\ No newline at end of file
This diff is collapsed.
......@@ -68,32 +68,23 @@ class fmcmasterfip:
# Carrier specific components
#------------------------------------
# Carrier CSR address
# TODO: recreate
CARRIER_CSR_ADDR = 0x00001200
# Carrier One Wire
CARR_ONEWIRE_ADDR = 0x00001100
CROSSBAR_MAIN = 0x20000
CROSSBAR_MAIN = 0x10000
#------------------------------------
# MasterFIP FMC address
# eeprom
# TODO: recreate
MASTERFIP_I2C_EEPROM = CROSSBAR_MAIN + 0x1000
# ADC configuration
MASTERFIP_SPI_ADC = CROSSBAR_MAIN + 0x1100
# SI570 configuration (not mount)
MASTERFIP_I2C_SI570 = CROSSBAR_MAIN + 0x1200
# ADC core registers
MASTERFIP_CSR_ADC = CROSSBAR_MAIN + 0x1300
# Thermometer
MASTERFIP_OW_THERM = CROSSBAR_MAIN + 0x1400
# Masterfip core registers
MASTERFIP_CORE_ADDR = CROSSBAR_MAIN + 0x8000
SAMPLING_FREQ_ADDR_IN_BINARY_DATA = 72;
# Masterfip core registers
MASTERFIP_CORE_ADDR = 0x10000
freq_options = [ 31250, 1e6, 25e5, 5e6 ]
adc_sampling_freq = 100e6
###############################################################################################
......@@ -118,10 +109,6 @@ class fmcmasterfip:
###################################################################
# creation of interfaces to modules controlling external devices
self.carr_onewire = ow.COpenCoresOneWire(self.carrier, self.CARR_ONEWIRE_ADDR, 199, 39) #for 40 MHz clock
self.carr_ds18b20 = ds18b20.CDS18B20(self.carr_onewire, 0)
self.fmc_onewire = ow.COpenCoresOneWire(self.carrier, self.MASTERFIP_OW_THERM, 499, 99) #for 40 MHz clock
self.fmc_ds18b20 = ds18b20.CDS18B20(self.fmc_onewire, 0)
......@@ -136,7 +123,7 @@ class fmcmasterfip:
###################### firmware initialization ####################
###################################################################
self.verify_bitstream_type();
self.verify_carrier_status();
# self.verify_carrier_status();
self.rst_core()
time.sleep(0.5)
......
......@@ -2,7 +2,7 @@
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/carrier_addrtable.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/carrier_csr.wb
# * Created : Tue Mar 7 12:59:04 2017
# * Created : Wed Mar 15 14:47:52 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/carrier_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......
......@@ -2,7 +2,7 @@
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_addrtable.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
# * Created : Tue Mar 7 12:59:02 2017
# * Created : Wed Mar 15 14:47:50 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......
This diff is collapsed.
This diff is collapsed.
......@@ -27,4 +27,11 @@ top=`echo "$prg" | sed 's/fmcmasterfip\/.*/fmcmasterfip/'`
-P "$top/python/regs/carrier_addrtable.py" \
"$top/gateware/rtl/wbgen/carrier_csr.wb"
"$top/scripts/wbgen2" \
-D "$top/python/regs/masterfip_csr.htm" \
-P "$top/python/regs/masterfip_csr.py" \
-l vhdl \
-V "$top/gateware/rtl/wbgen/masterfip_csr.vhd" \
"$top/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb"
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