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MasterFIP - Testing
Commits
790f6bf9
Commit
790f6bf9
authored
Nov 16, 2016
by
Evangelia Gousiou
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removed testing of EXT_SYNC_TST_N, as in the v2 of the board this feature is completely removed.
parent
e3662c5c
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3 changed files
with
78 additions
and
69 deletions
+78
-69
MasterFip_PTS_UserGuide.docx
doc/MasterFip_PTS_UserGuide.docx
+0
-0
test06.py
python/test06.py
+75
-66
utilities.py
python/utilities.py
+3
-3
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doc/MasterFip_PTS_UserGuide.docx
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790f6bf9
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python/test06.py
View file @
790f6bf9
...
...
@@ -22,10 +22,9 @@ def test_sync_output( dut, box ):
# enable output
dut
.
fipcore
.
write_regname
(
'ext_sync.oe'
,
1
)
# disable termination
(should bring input to gnd via resistors)
# disable termination
dut
.
fipcore
.
write_regname
(
'ext_sync.term_en'
,
0
)
# disable test pull up
dut
.
fipcore
.
write_regname
(
'ext_sync.tst'
,
0
)
# set output value
dut
.
fipcore
.
write_regname
(
'ext_sync.output_value'
,
0
)
# set trigger to output direction
...
...
@@ -38,8 +37,7 @@ def test_sync_output( dut, box ):
util
.
info_msg
(
"Connecting ADC to channel 1 of secondary transformer side "
)
# connect ADC to secondary transformer side (connected to trigger)
dut
.
close_relay
(
2
)
# wait
time
.
sleep
(
DEL
)
...
...
@@ -50,7 +48,7 @@ def test_sync_output( dut, box ):
adc_samples
=
dut
.
adc_single_sample
()
if
adc_samples
[
1
]
<
util
.
test0
9
_thd
:
if
adc_samples
[
1
]
<
util
.
test0
6
_thd
:
# util.info_msg("Value read by ADC: CH1=%d, CH2=%d" %( adc_samples[0], adc_samples[1] ) )
util
.
info_msg
(
"Value read by ADC:
%
d"
%
(
adc_samples
[
1
]
)
)
else
:
...
...
@@ -60,9 +58,8 @@ def test_sync_output( dut, box ):
time
.
sleep
(
0.1
)
#######################
#
util
.
info_msg
(
""
)
util
.
info_msg
(
"Generating high output"
)
dut
.
fipcore
.
write_regname
(
'ext_sync.output_value'
,
1
)
...
...
@@ -83,7 +80,7 @@ def test_sync_output( dut, box ):
adc_samples
=
dut
.
adc_single_sample
()
sampled
[
t
]
+=
adc_samples
[
1
];
if
adc_samples
[
1
]
>=
util
.
test0
9
_thd
:
if
adc_samples
[
1
]
>=
util
.
test0
6
_thd
:
util
.
info_msg
(
"Value read by ADC:
%
d"
%
adc_samples
[
1
]
)
else
:
...
...
@@ -100,19 +97,73 @@ def test_sync_output( dut, box ):
output_ratio_term
=
float
(
sampled
[
0
])
/
float
(
sampled
[
1
])
if
output_ratio_term
<
util
.
test0
9
_thdratio
:
util
.
err_msg
(
"Ratio of output value with and without termination is
%
f. Should be over
%
f."
%
(
output_ratio_term
,
util
.
test0
9
_thdratio
)
)
if
output_ratio_term
<
util
.
test0
6
_thdratio
:
util
.
err_msg
(
"Ratio of output value with and without termination is
%
f. Should be over
%
f."
%
(
output_ratio_term
,
util
.
test0
6
_thdratio
)
)
result
[
'External sync termination'
]
=
0
else
:
util
.
info_msg
(
"Ratio of output value with and without termination is
%
f. Should be over
%
f."
%
(
output_ratio_term
,
util
.
test0
9
_thdratio
)
)
util
.
info_msg
(
"Ratio of output value with and without termination is
%
f. Should be over
%
f."
%
(
output_ratio_term
,
util
.
test0
6
_thdratio
)
)
result
[
'External sync termination'
]
=
1
# set output value
dut
.
fipcore
.
write_regname
(
'ext_sync.output_value'
,
0
)
time
.
sleep
(
DEL
)
#######################
util
.
info_msg
(
"
\n
Disabling bidir buffer output:"
)
# disable output
dut
.
fipcore
.
write_regname
(
'ext_sync.oe'
,
0
)
time
.
sleep
(
DEL
)
for
i
in
xrange
(
NRSAMPLES
):
adc_samples
=
dut
.
adc_single_sample
()
sampled
[
t
]
+=
adc_samples
[
1
];
if
adc_samples
[
1
]
<=
util
.
test06_thd
:
util
.
info_msg
(
"Value read by ADC:
%
d"
%
adc_samples
[
1
]
)
result
[
'Read low value with bidir buffer OE disabled'
]
=
1
else
:
util
.
err_msg
(
"Output remains high when the bidir buffer OE is disabled. Value read by ADC:
%
d"
%
adc_samples
[
1
])
result
[
'Read low value with bidir buffer OE disabled'
]
=
0
time
.
sleep
(
0.1
)
time
.
sleep
(
DEL
)
util
.
info_msg
(
""
)
util
.
info_msg
(
"Output verified to go low when the bidir buffer OE is disabled."
)
#######################
util
.
info_msg
(
"
\n
Enabling bidir buffer output:"
)
# disable output
dut
.
fipcore
.
write_regname
(
'ext_sync.oe'
,
1
)
for
i
in
xrange
(
NRSAMPLES
):
adc_samples
=
dut
.
adc_single_sample
()
sampled
[
t
]
+=
adc_samples
[
1
];
if
adc_samples
[
1
]
>=
util
.
test06_thd
:
util
.
info_msg
(
"Value read by ADC:
%
d"
%
adc_samples
[
1
]
)
result
[
'Read high value with bidir buffer OE enabled'
]
=
1
else
:
util
.
err_msg
(
"Output is high when the bidir buffer OE is enabled. Value read by ADC:
%
d"
%
adc_samples
[
1
])
result
[
'Read high value with bidir buffer OE enabled'
]
=
0
time
.
sleep
(
0.1
)
time
.
sleep
(
DEL
)
util
.
info_msg
(
""
)
util
.
info_msg
(
"Output verified to go high when the bidir buffer OE is enabled."
)
#######################
# set output value low
dut
.
fipcore
.
write_regname
(
'ext_sync.output_value'
,
0
)
time
.
sleep
(
DEL
)
util
.
info_msg
(
""
)
util
.
info_msg
(
"Generating low output again"
)
result
[
'Trigger output verified to go low for the second time'
]
=
1
...
...
@@ -120,17 +171,17 @@ def test_sync_output( dut, box ):
adc_samples
=
dut
.
adc_single_sample
()
util
.
dbg_msg
(
"Read ADC value: CH1=
%
d, CH2=
%
d low trigger output"
%
(
adc_samples
[
0
],
adc_samples
[
1
]
)
)
if
adc_samples
[
1
]
<
util
.
test0
9
_thd
:
if
adc_samples
[
1
]
<
util
.
test0
6
_thd
:
util
.
info_msg
(
"Value read by ADC:
%
d"
%
adc_samples
[
1
]
)
else
:
util
.
err_msg
(
"Value read by ADC:
%
d"
%
adc_samples
[
1
]
)
result
[
'Trigger output verified to go low for the second time'
]
=
0
time
.
sleep
(
0.1
)
time
.
sleep
(
0.1
)
return
result
###############################################################################
def
test_sync_input
(
dut
,
box
):
...
...
@@ -143,15 +194,14 @@ def test_sync_input( dut, box ):
time
.
sleep
(
DEL
)
util
.
info_msg
(
"Setting trigger to input"
)
util
.
info_msg
(
"Disabling Test pullup resistor"
)
# set trigger to input direction
dut
.
fipcore
.
write_regname
(
'ext_sync.dir'
,
0
)
# enable output
# enable tranceiver output
dut
.
fipcore
.
write_regname
(
'ext_sync.oe'
,
1
)
# enable termination (should bring input to gnd via resistors)
dut
.
fipcore
.
write_regname
(
'ext_sync.term_en'
,
1
)
# disable test pull up
dut
.
fipcore
.
write_regname
(
'ext_sync.tst'
,
0
)
time
.
sleep
(
DEL
);
...
...
@@ -162,47 +212,9 @@ def test_sync_input( dut, box ):
util
.
err_msg
(
"Value read from trigger input is 1"
)
result
[
'Read low value on trigger input with pulldown resistor enabled'
]
=
0
util
.
info_msg
(
""
)
util
.
info_msg
(
"Enabling Test pullup resistor"
)
dut
.
fipcore
.
write_regname
(
'ext_sync.tst'
,
1
)
time
.
sleep
(
DEL
);
if
dut
.
fipcore
.
read_regname
(
'ext_sync_raw_input'
)
==
1
:
result
[
'Read low value on trigger input with pullup resistor enabled'
]
=
1
util
.
info_msg
(
"Value read from trigger input is 1"
)
else
:
util
.
err_msg
(
"Value read from trigger input is 0"
)
result
[
'Read low value on trigger input with pullup resistor enabled'
]
=
0
util
.
info_msg
(
""
)
util
.
info_msg
(
"Disabling bidir buffer outputs"
)
util
.
info_msg
(
"Repeating pullup switching"
)
util
.
info_msg
(
"Since outputs are disabled both values should be the same"
)
# disable output
dut
.
fipcore
.
write_regname
(
'ext_sync.oe'
,
0
)
# should read the same value on pullup and pulldown since buffer outputs are high-z
dut
.
fipcore
.
write_regname
(
'ext_sync.tst'
,
1
)
time
.
sleep
(
DEL
);
output_disabled_pullup
=
dut
.
fipcore
.
read_regname
(
'ext_sync_raw_input'
)
dut
.
fipcore
.
write_regname
(
'ext_sync.tst'
,
0
)
time
.
sleep
(
DEL
);
output_disabled_pulldown
=
dut
.
fipcore
.
read_regname
(
'ext_sync_raw_input'
)
if
output_disabled_pulldown
==
output_disabled_pullup
:
result
[
'Trigger output enable'
]
=
1
util
.
info_msg
(
"Value read with and without pullup was the same"
)
else
:
result
[
'Trigger output enable'
]
=
0
util
.
err_msg
(
"Value read with and without pullup was different"
)
#######################
util
.
info_msg
(
""
)
util
.
info_msg
(
"Connecting input to reference voltage in calibration box"
)
...
...
@@ -215,9 +227,6 @@ def test_sync_input( dut, box ):
dut
.
fipcore
.
write_regname
(
'ext_sync.oe'
,
1
)
# disable termination
dut
.
fipcore
.
write_regname
(
'ext_sync.term_en'
,
0
)
# disable test pull up
dut
.
fipcore
.
write_regname
(
'ext_sync.tst'
,
0
)
# input should be "floating"
time
.
sleep
(
DEL
)
if
dut
.
fipcore
.
read_regname
(
'ext_sync_raw_input'
)
==
0
:
...
...
@@ -246,7 +255,7 @@ def test_sync_input( dut, box ):
def
main
(
card
=
None
,
default_directory
=
'.'
,
suite
=
None
,
serial
=
""
):
testname
=
"Test0
9
: Trigger Input/Output"
testname
=
"Test0
6
: Trigger Input/Output"
util
.
header_msg
(
testname
,
[
"Bidirectional Buffer communication"
,
"Termination switching"
,
"Test pullup resistor switching"
,
...
...
@@ -287,4 +296,4 @@ def main (card=None, default_directory='.',suite=None, serial=""):
errors
=
util
.
summarise_test_results
(
testname
,
test_results
)
if
__name__
==
'__main__'
:
main
()
\ No newline at end of file
main
()
python/utilities.py
View file @
790f6bf9
...
...
@@ -23,8 +23,8 @@ test05_fru_gen_path = "/software/fmc-bus/tools/fru-generator"
test05_gensdbfs_path
=
"/software/fpga-config-space/sdbfs/userspace/gensdbfs"
test05_sdbfs_path
=
"/python/sdbfs/"
test0
9
_thd
=
2000
;
test0
9
_thdratio
=
1.8
test0
6
_thd
=
2000
;
test0
6
_thdratio
=
1.8
mintemp
=
0
maxtemp
=
80
...
...
@@ -203,4 +203,4 @@ def calibration_box_init():
box
=
calibr_box
.
CCalibr_box
(
box_tty
[
0
])
return
box
\ No newline at end of file
return
box
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