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MasterFIP - Testing
Commit d840928c authored by Marek Gumiński's avatar Marek Gumiński
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Finished masterfip_pts. 

Added masterfip_pts core to top module.
Modified and verified test06 to match gateware changes.
Changed sync input to inout on top module.
parent 7dabae5e
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gateware/rtl/fmc_masterfip_csr_pts.vhd
View file @ d840928c
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/fmc_masterfip_csr_pts.vhd
-- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
-- Created : Wed Mar 29 15:35:06 2017
-- Created : Thu Mar 30 10:54:22 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
......
gateware/rtl/masterfip_pts.vhd 0 → 100644
View file @ d840928c
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.masterFIP_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
-- use work.wrcore_pkg.all;
use work.genram_pkg.all;
--=================================================================================================
-- Entity declaration for fmc_masterFIP_core
--=================================================================================================
entity masterfip_pts is
port(
-- Clock and reset
clk_i : in std_logic; -- 100 MHz clock
rst_i : in std_logic;
-- External synchronisation pulse transceiver
ext_sync_term_en_o : out std_logic; -- enable 50 Ohms termination of the pulse
ext_sync_dir_o : out std_logic; -- transceiver direction
ext_sync_oe_n_o : out std_logic; -- transceiver output enable
ext_sync_io : inout std_logic; -- sync pulse
-- FielDrive
fd_rxcdn_i : in std_logic;
fd_txer_i : in std_logic;
fd_wdgn_i : in std_logic;
fd_txd_corrupt_o : out std_logic;
-- WISHBONE classic bus interface
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out
);
end masterfip_pts;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of masterfip_pts is
-- resets
signal rst_n : std_logic;
signal core_rst,
core_rst_n,
core_rst_tmp : std_logic;
-- ext pulse
signal ext_sync_p,
ext_sync_oe,
ext_sync_iodir,
ext_sync_out_val,
ext_sync_dir : std_logic;
-- FielDrive output monitoring
signal fd_cnt_reinit,
fd_wdgn_sync,
fd_wdgn_latch,
fd_txer_p,
fd_rxcdn_p : std_logic;
signal fd_txer_cnt,
fd_rxcdn_cnt : std_logic_vector (32-1 downto 0);
-- signals that should be driven by masterfip core
-- not sure if removing them will work
signal fd_host_rstn : std_logic;
signal macrocyc_load_p : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- resets --
---------------------------------------------------------------------------------------------------
rst_n <= not rst_i;
core_rst <= core_rst_tmp or rst_i;
core_rst_n <= not core_rst;
macrocyc_load_p <= '1';
fd_host_rstn <= '0';
---------------------------------------------------------
---- External synchronisation IO
---------------------------------------------------------
-- FPGA IO direction is controlled by ext_sync_iodir line
-- external bidirectional buffer is controlled by other line
-- during normal operation direction should be the same
-- but for PTS directions are controlled separately
ext_sync_io <= ext_sync_out_val when ext_sync_iodir = '1' else 'Z';
ext_sync_dir_o <= ext_sync_dir;
-- since external line oe_n is active low and wbregs default value is zero
-- register is called oe and its value is negated here
ext_sync_oe_n_o <= '0' when ext_sync_oe = '1' else 'Z';
---------------------------------------------------------------------------------------------------
-- FielDrive TXERR, WDGN --
---------------------------------------------------------------------------------------------------
-- synchronisation of the fd_wdgn_i signal
cmp_fd_wdgn_i_pulse_detect: gc_sync_ffs
generic map(
g_sync_edge => "positive"
)
port map(
clk_i => clk_i,
rst_n_i => rst_n,
data_i => fd_wdgn_i,
synced_o => fd_wdgn_sync
);
-- process that registers the activation of fd_wdgn_i
-- the signals are reset upon a core_rst_n or a fd_host_rstn
p_fd_wdgn_capture : process(clk_i)
begin
if rising_edge(clk_i) then
if(core_rst = '1' or fd_host_rstn = '0') then
fd_wdgn_latch <= '1';
else
if fd_wdgn_sync = '0' then
fd_wdgn_latch <= '0';
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
fd_cnt_reinit <= '1' when core_rst_n = '0' or
macrocyc_load_p = '1' or
fd_host_rstn = '0' else
'0';
-- edge detection on the fd_txer_i signal
cmp_fd_txer_i_pulse_detect: gc_sync_ffs
generic map(
g_sync_edge => "positive"
)
port map(
clk_i => clk_i,
rst_n_i => rst_n,
data_i => fd_txer_i,
ppulse_o => fd_txer_p
);
-- counter counting the number of fd_wdgn_p
cmp_fd_txer_cnt:incr_counter
generic map(
g_counter_lgth => 32
)
port map(
clk_i => clk_i,
counter_incr_i => fd_txer_p,
counter_reinit_i => fd_cnt_reinit,
counter_is_full_o => open,
counter_o => fd_txer_cnt
);
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- edge detection on the fd_rxcdn_i signal
cmp_fd_cdn_i_pulse_detect: gc_sync_ffs
generic map(
g_sync_edge => "positive"
)
port map(
clk_i => clk_i,
rst_n_i => rst_n,
data_i => fd_rxcdn_i,
ppulse_o => fd_rxcdn_p
);
-- counter counting the number of fd_rxcdn_p
cmp_fd_cdn_cnt:incr_counter
generic map(
g_counter_lgth => 32
)
port map(
clk_i => clk_i,
counter_incr_i => fd_rxcdn_p,
counter_reinit_i => fd_cnt_reinit,
counter_is_full_o => open,
counter_o => fd_rxcdn_cnt
);
---------------------------------------------------------------------------------------------------
-- REGISTERS --
---------------------------------------------------------------------------------------------------
cmp_masterfip_csr: entity work.masterfip_pts_csr
port map (
-- wishbone
rst_n_i => rst_n,
clk_sys_i => clk_i,
wb_adr_i => slave_i.adr(4 downto 2),
wb_dat_i => slave_i.dat,
wb_dat_o => slave_o.dat,
wb_cyc_i => slave_i.cyc,
wb_sel_i => slave_i.sel,
wb_stb_i => slave_i.stb,
wb_we_i => slave_i.we,
wb_ack_o => slave_o.ack,
wb_stall_o => slave_o.stall,
-- resets
mfpts_rst_core_o => core_rst_tmp, -- reset has to be confirmed with lock word mf_rstn_lock_o
-- external sync pulse
mfpts_ext_sync_term_en_o => ext_sync_term_en_o,
mfpts_ext_sync_dir_o => ext_sync_dir,
mfpts_ext_sync_oe_o => ext_sync_oe,
mfpts_ext_sync_output_value_o => ext_sync_out_val,
mfpts_ext_sync_fpga_io_dir_o => ext_sync_iodir,
mfpts_ext_sync_raw_input_i => ext_sync_io,
mfpts_tx_corrupt_enable_o => fd_txd_corrupt_o,
mfpts_fd_wdgn_i => fd_wdgn_i, -- FIELDRIVE watchdog, signal comes from the FIELDRIVE
mfpts_fd_wdgn_latch_i => fd_wdgn_latch,
mfpts_fd_cd_n_i => fd_rxcdn_i,
mfpts_fd_rxcdn_cnt_i => fd_rxcdn_cnt,
mfpts_fd_txer_i => fd_txer_i, -- FIELDRIVE txerr, signal comes from the FIELDRIVE
mfpts_fd_txerr_cnt_i => fd_txer_cnt
);
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
----------------------------------------------------------------------------------------------------
gateware/rtl/wbgen/masterfip_csr.vhd
View file @ d840928c
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_csr.vhd
-- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
-- Created : Wed Mar 29 15:35:08 2017
-- Created : Thu Mar 30 10:54:24 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
......
gateware/rtl/wbgen/masterfip_pts_csr.vhd
View file @ d840928c
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.vhd
-- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
-- Created : Wed Mar 29 15:35:11 2017
-- Created : Thu Mar 30 10:54:26 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
......@@ -37,11 +37,9 @@ entity masterfip_pts_csr is
mfpts_ext_sync_oe_o : out std_logic;
-- Port for BIT field: 'External sync output value (when buffer is switched)' in reg: 'ext sync'
mfpts_ext_sync_output_value_o : out std_logic;
-- Port for BIT field: 'pulses counter reset' in reg: 'ext sync'
mfpts_ext_sync_p_cnt_rst_o : out std_logic;
-- Port for BIT field: 'FPGA IO direction' in reg: 'ext sync'
mfpts_ext_sync_fpga_io_dir_o : out std_logic;
-- Port for BIT field: 'ext_sync_raw_input' in reg: 'ext sync raw input'
-- Port for BIT field: 'raw_input' in reg: 'ext sync'
mfpts_ext_sync_raw_input_i : in std_logic;
-- Port for BIT field: 'enable' in reg: 'PTS options'
mfpts_tx_corrupt_enable_o : out std_logic;
......@@ -53,6 +51,8 @@ entity masterfip_pts_csr is
mfpts_fd_cd_n_i : in std_logic;
-- Port for BIT field: 'fd transmitter error' in reg: 'fieldrive status'
mfpts_fd_txer_i : in std_logic;
-- Port for std_logic_vector field: 'fieldrive rx not carrier detect counter' in reg: 'fieldrive rx not carrier detect counter'
mfpts_fd_rxcdn_cnt_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'fieldrive tx error counter' in reg: 'fieldrive tx error counter'
mfpts_fd_txerr_cnt_i : in std_logic_vector(31 downto 0)
);
......@@ -66,7 +66,6 @@ signal mfpts_ext_sync_term_en_int : std_logic ;
signal mfpts_ext_sync_dir_int : std_logic ;
signal mfpts_ext_sync_oe_int : std_logic ;
signal mfpts_ext_sync_output_value_int : std_logic ;
signal mfpts_ext_sync_p_cnt_rst_int : std_logic ;
signal mfpts_ext_sync_fpga_io_dir_int : std_logic ;
signal mfpts_tx_corrupt_enable_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
......@@ -101,7 +100,6 @@ begin
mfpts_ext_sync_dir_int <= '0';
mfpts_ext_sync_oe_int <= '0';
mfpts_ext_sync_output_value_int <= '0';
mfpts_ext_sync_p_cnt_rst_int <= '0';
mfpts_ext_sync_fpga_io_dir_int <= '0';
mfpts_tx_corrupt_enable_int <= '0';
elsif rising_edge(clk_sys_i) then
......@@ -162,52 +160,14 @@ begin
mfpts_ext_sync_dir_int <= wrdata_reg(1);
mfpts_ext_sync_oe_int <= wrdata_reg(2);
mfpts_ext_sync_output_value_int <= wrdata_reg(3);
mfpts_ext_sync_p_cnt_rst_int <= wrdata_reg(8);
mfpts_ext_sync_fpga_io_dir_int <= wrdata_reg(9);
mfpts_ext_sync_fpga_io_dir_int <= wrdata_reg(4);
end if;
rddata_reg(0) <= mfpts_ext_sync_term_en_int;
rddata_reg(1) <= mfpts_ext_sync_dir_int;
rddata_reg(2) <= mfpts_ext_sync_oe_int;
rddata_reg(3) <= mfpts_ext_sync_output_value_int;
rddata_reg(8) <= mfpts_ext_sync_p_cnt_rst_int;
rddata_reg(9) <= mfpts_ext_sync_fpga_io_dir_int;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= mfpts_ext_sync_raw_input_i;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(4) <= mfpts_ext_sync_fpga_io_dir_int;
rddata_reg(5) <= mfpts_ext_sync_raw_input_i;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
......@@ -236,7 +196,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
when "010" =>
if (wb_we_i = '1') then
mfpts_tx_corrupt_enable_int <= wrdata_reg(0);
end if;
......@@ -274,7 +234,7 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
when "011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= mfpts_fd_wdgn_i;
......@@ -311,6 +271,12 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= mfpts_fd_rxcdn_cnt_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101" =>
if (wb_we_i = '1') then
end if;
......@@ -351,17 +317,16 @@ begin
mfpts_ext_sync_oe_o <= mfpts_ext_sync_oe_int;
-- External sync output value (when buffer is switched)
mfpts_ext_sync_output_value_o <= mfpts_ext_sync_output_value_int;
-- pulses counter reset
mfpts_ext_sync_p_cnt_rst_o <= mfpts_ext_sync_p_cnt_rst_int;
-- FPGA IO direction
mfpts_ext_sync_fpga_io_dir_o <= mfpts_ext_sync_fpga_io_dir_int;
-- ext_sync_raw_input
-- raw_input
-- enable
mfpts_tx_corrupt_enable_o <= mfpts_tx_corrupt_enable_int;
-- fd watchdog
-- fd watchdog latched
-- fd carrier detect
-- fd transmitter error
-- fieldrive rx not carrier detect counter
-- fieldrive tx error counter
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
......
gateware/rtl/wbgen/masterfip_pts_csr.wb
View file @ d840928c
......@@ -70,16 +70,6 @@ peripheral {
access_dev = READ_ONLY;
};
field {
name = "pulses counter reset";
prefix = "p_cnt_rst";
description = "resets the pulses counter";
type = BIT;
align = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "FPGA IO direction";
prefix = "fpga_io_dir";
......@@ -89,22 +79,21 @@ peripheral {
access_dev = READ_ONLY;
};
};
reg {
name = "ext sync raw input";
prefix = "ext_sync_raw_input";
field {
name = "ext_sync_raw_input";
description = "External sync input value. Only valid whrn direction is set to input";
name = "raw_input";
prefix = "raw_input";
description = "External sync input value. Only valid when direction is set to input";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
};
-------------------------------------------------------------------------------
-- fieldrive status signals --
-------------------------------------------------------------------------------
reg {
name = "PTS options";
......@@ -118,12 +107,8 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
-------------------------------------------------------------------------------
-- fieldrive status signals --
-------------------------------------------------------------------------------
reg {
name = "fieldrive status";
prefix = "fd";
......@@ -162,6 +147,21 @@ peripheral {
};
};
reg{
name = "fieldrive rx not carrier detect counter";
prefix = "fd_rxcdn_cnt";
field {
name = "fieldrive rx not carrier detect counter";
description = "Number of RX NOT carrier detect periods. Counter is reset by macrocycle, core reset and fd reset";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg{
name = "fieldrive tx error counter";
prefix = "fd_txerr_cnt";
......
gateware/syn/spec/spec_masterfip_mt.xise
View file @ d840928c
This diff is collapsed.
gateware/top/spec/spec_masterfip_pts2.ucf
View file @ d840928c
......@@ -228,8 +228,8 @@ NET "speed_b1_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_term_en_o" LOC = AB13;
NET "ext_sync_term_en_o" IOSTANDARD = "LVCMOS25";
NET "ext_sync_i" LOC = T8;
NET "ext_sync_i" IOSTANDARD = "LVCMOS25";
NET "ext_sync_io" LOC = T8;
NET "ext_sync_io" IOSTANDARD = "LVCMOS25";
NET "ext_sync_oe_n_o" LOC = W6;
NET "ext_sync_oe_n_o" IOSTANDARD = "LVCMOS25";
......
gateware/top/spec/spec_masterfip_pts2.vhd
View file @ d840928c
......@@ -232,7 +232,7 @@ entity spec_masterfip_pts2 is
ext_sync_term_en_o : out std_logic; -- enable 50 Ohm termin of the pulse
ext_sync_dir_o : out std_logic := '0'; -- direction fixed B -> A
ext_sync_oe_n_o : out std_logic := '0'; -- output fixed to enabled
ext_sync_i : in std_logic; -- sync pulse
ext_sync_io : inout std_logic; -- sync pulse
-- FMC Front panel LEDs: controlled by the MT firmware, updated every macrocycle
led_rx_act_n_o : out std_logic;
......@@ -333,21 +333,25 @@ architecture rtl of spec_masterfip_pts2 is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- crossbar constants
constant c_NUM_WB_SLAVES : integer := 3;
constant c_NUM_WB_SLAVES : integer := 4;
constant c_WB_SLAVE_MF_CORE : integer := 0;
constant c_WB_SLAVE_STATUS_CSR : integer := 1;
constant c_WB_SLAVE_FMC_I2C : integer := 2;
constant c_WB_SLAVE_MF_PTS_CSR : integer := 3;
constant C_SLAVE_ADDR : t_wishbone_address_array(c_NUM_WB_SLAVES-1 downto 0):= (
c_WB_SLAVE_MF_CORE => x"00010000",
c_WB_SLAVE_STATUS_CSR => x"00011000",
c_WB_SLAVE_FMC_I2C => x"00012000"
c_WB_SLAVE_FMC_I2C => x"00012000",
c_WB_SLAVE_MF_PTS_CSR => x"00013000"
);
constant C_SLAVE_MASK : t_wishbone_address_array(c_NUM_WB_SLAVES-1 downto 0):= (
c_WB_SLAVE_MF_CORE => x"fffff000",
c_WB_SLAVE_STATUS_CSR => x"fffff000",
c_WB_SLAVE_FMC_I2C => x"fffff000"
c_WB_SLAVE_FMC_I2C => x"fffff000",
c_WB_SLAVE_MF_PTS_CSR => x"fffff000"
);
......@@ -375,6 +379,9 @@ architecture rtl of spec_masterfip_pts2 is
signal sys_sda_in : std_logic;
signal sys_sda_out : std_logic;
signal sys_sda_oe_n : std_logic;
signal rst_sys : std_logic;
signal fd_txd_corrupt : std_logic;
--=================================================================================================
......@@ -385,8 +392,8 @@ begin
---------------------------------------------------------------------------------------------------
-- FIXED SIGNALS --
---------------------------------------------------------------------------------------------------
ext_sync_dir_o <= '0'; -- Direction fixed to: B -> A
ext_sync_oe_n_o <= '0'; -- Output fixed to: enabled
-- ext_sync_dir_o <= '0'; -- Direction fixed to: B -> A
-- ext_sync_oe_n_o <= '0'; -- Output fixed to: enabled
-- To be removed on hw V3
-- Note: For the hw v1 signals ext_sync_tst_n_o, adc_prim_conn_n_o and adc_sec_conn_n_o, in order
......@@ -396,7 +403,7 @@ begin
adc_m5v_shdn_n_o <= '0'; -- OFF
adc_5v_en_n_o <= '1'; -- OFF
rst_sys <= not rst_n_sys;
---------------------------------------------------------------------------------------------------
-- MOCK TURTLE CORE --
......@@ -511,8 +518,8 @@ begin
fd_txd_o => fd_txd,
fd_txena_o => fd_txena_o,
-- External Synch
ext_sync_term_en_o => ext_sync_term_en_o,
ext_sync_a_i => ext_sync_i,
ext_sync_term_en_o => open,
ext_sync_a_i => '0',
ext_sync_dir_o => open, -- hard-wired to '0'
ext_sync_oe_n_o => open, -- hard-wired to '0'
-- LEDs
......@@ -543,7 +550,8 @@ begin
led_sync_err_n_o <= leds(5); -- probe on R6
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
fd_txd_o <= fd_txd;
-- fd_txd_o <= fd_txd;
fd_txd_o <= fd_txd when fd_txd_corrupt = '0' else '0';
tp1_o <= fd_rxd_i;
tp2_o <= fd_txd;
tp3_o <= leds(8);
......@@ -623,6 +631,35 @@ begin
-- Tri-state buffer for SDA and SCL
---------------------------------------------------------
---- Module containing PTS cores
---------------------------------------------------------
pts_core_inst: entity work.masterfip_pts
port map(
-- Clock and reset
clk_i => clk_100m_sys,
rst_i => rst_sys,
-- External synchronisation pulse transceiver
ext_sync_term_en_o => ext_sync_term_en_o,
ext_sync_dir_o => ext_sync_dir_o,
ext_sync_oe_n_o => ext_sync_oe_n_o,
ext_sync_io => ext_sync_io,
-- FielDrive
fd_rxcdn_i => fd_rxcdn_i,
fd_txer_i => fd_txer_i,
fd_wdgn_i => fd_wdgn_i,
fd_txd_corrupt_o => fd_txd_corrupt,
-- WISHBONE classic bus interface
slave_i => wbmain_slaves_ms(c_WB_SLAVE_MF_PTS_CSR),
slave_o => wbmain_slaves_sm(c_WB_SLAVE_MF_PTS_CSR)
);
---------------------------------------------------------------------------------------------------
-- SPEC front panel LEDs --
---------------------------------------------------------------------------------------------------
......
python/fmcmasterfip.py
View file @ d840928c
......@@ -40,6 +40,7 @@ import i2c
# addressing
import masterfip_csr;
import masterfip_pts_csr;
import carrier_addrtable;
......@@ -79,7 +80,10 @@ class fmcmasterfip:
CARRIER_CSR_ADDR = 0x00011000
# MasterFIP FMC eeprom
MASTERFIP_I2C_EEPROM = 0x00012000
MASTERFIP_I2C_EEPROM_ADDR = 0x00012000
# MasterFIP FMC eeprom
MASTERFIP_PTS_CSR_ADDR = 0x00013000
freq_options = [ 31250, 1e6, 25e5, 5e6 ]
......@@ -106,12 +110,13 @@ class fmcmasterfip:
###################################################################
# creation of interfaces to modules controlling external devices
self.fmc_sys_i2c = i2c.COpenCoresI2C(self.carrier, self.MASTERFIP_I2C_EEPROM, 199)
self.fmc_sys_i2c = i2c.COpenCoresI2C(self.carrier, self.MASTERFIP_I2C_EEPROM_ADDR, 199)
self.fmc_eeprom_24aa64 = eeprom_24aa64.C24AA64(self.fmc_sys_i2c, self.EEPROM_ADDR)
# creation of interfaces to modules controlling main functionality
self.fipcore = wbslave.wbslave(carrier, self.MASTERFIP_CORE_ADDR, masterfip_csr.addr)
self.carrier_csr = wbslave.wbslave(carrier, self.CARRIER_CSR_ADDR, carrier_addrtable.addr)
self.fippts = wbslave.wbslave(carrier, self.MASTERFIP_PTS_CSR_ADDR, masterfip_pts_csr.addr)
###################################################################
###################### firmware initialization ####################
......
python/regs/carrier_addrtable.py
View file @ d840928c
......@@ -2,7 +2,7 @@
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/carrier_addrtable.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/carrier_csr.wb
# * Created : Wed Mar 29 15:35:08 2017
# * Created : Thu Mar 30 10:54:24 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/carrier_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......
python/regs/masterfip_addrtable.py
View file @ d840928c
......@@ -2,7 +2,7 @@
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_addrtable.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
# * Created : Wed Mar 29 15:35:06 2017
# * Created : Thu Mar 30 10:54:22 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......
python/regs/masterfip_csr.py
View file @ d840928c
......@@ -2,7 +2,7 @@
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_csr.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
# * Created : Wed Mar 29 15:35:09 2017
# * Created : Thu Mar 30 10:54:24 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......
python/regs/masterfip_pts_csr.htm
View file @ d840928c
This diff is collapsed.
python/regs/masterfip_pts_csr.py
View file @ d840928c
......@@ -2,7 +2,7 @@
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_pts_csr.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
# * Created : Wed Mar 29 15:35:11 2017
# * Created : Thu Mar 30 10:54:26 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......@@ -17,18 +17,18 @@ addr = {
'ext_sync.dir' : [ 0x1, 0x2, "rw"],
'ext_sync.oe' : [ 0x1, 0x4, "rw"],
'ext_sync.output_value' : [ 0x1, 0x8, "rw"],
'ext_sync.p_cnt_rst' : [ 0x1, 0x100, "rw"],
'ext_sync.fpga_io_dir' : [ 0x1, 0x200, "rw"],
'ext_sync.fpga_io_dir' : [ 0x1, 0x10, "rw"],
'ext_sync.raw_input' : [ 0x1, 0x20, "rw"],
'ext_sync_raw_input' : [ 0x2, 0xffffffff, "r"],
'tx_corrupt' : [ 0x2, 0xffffffff, "rw"],
'tx_corrupt' : [ 0x3, 0xffffffff, "rw"],
'fd' : [ 0x3, 0xffffffff, "r"],
'fd.wdgn' : [ 0x3, 0x1, "r"],
'fd.wdgn_latch' : [ 0x3, 0x2, "r"],
'fd.cd_n' : [ 0x3, 0x4, "r"],
'fd.txer' : [ 0x3, 0x8, "r"],
'fd' : [ 0x4, 0xffffffff, "r"],
'fd.wdgn' : [ 0x4, 0x1, "r"],
'fd.wdgn_latch' : [ 0x4, 0x2, "r"],
'fd.cd_n' : [ 0x4, 0x4, "r"],
'fd.txer' : [ 0x4, 0x8, "r"],
'fd_rxcdn_cnt' : [ 0x4, 0xffffffff, "r"],
'fd_txerr_cnt' : [ 0x5, 0xffffffff, "r"],
'':[0,0]
......
python/test06.py
View file @ d840928c
......@@ -26,21 +26,21 @@ def test_sync_input( dut, box ):
util.info_msg("Setting synchronisation line to input")
dut.fipcore.write_regname('ext_sync.dir', 0)
dut.fipcore.write_regname('ext_sync.fpga_io_dir', 0)
dut.fippts.write_regname('ext_sync.dir', 0)
dut.fippts.write_regname('ext_sync.fpga_io_dir', 0)
util.info_msg("Enabling buffer")
dut.fipcore.write_regname('ext_sync.oe', 1)
dut.fippts.write_regname('ext_sync.oe', 1)
util.info_msg("Disabling termination")
dut.fipcore.write_regname('ext_sync.term_en', 0)
dut.fippts.write_regname('ext_sync.term_en', 0)
util.info_msg("Connecting synchronisation line to low voltage in relay box")
box.trigger_input_low()
time.sleep(DEL)
if dut.fipcore.read_regname('ext_sync_raw_input') == 0:
if dut.fippts.read_regname('ext_sync.raw_input') == 0:
result['Input low'] = 1
util.info_msg("Read low input value")
else :
......@@ -55,7 +55,7 @@ def test_sync_input( dut, box ):
time.sleep(DEL)
if dut.fipcore.read_regname('ext_sync_raw_input') == 1:
if dut.fippts.read_regname('ext_sync.raw_input') == 1:
result['Input high'] = 1
util.info_msg("Read high input value")
else :
......@@ -76,21 +76,21 @@ def test_termination( dut, box ):
util.info_msg("Setting synchronisation line to input")
dut.fipcore.write_regname('ext_sync.dir', 0)
dut.fipcore.write_regname('ext_sync.fpga_io_dir', 0)
dut.fippts.write_regname('ext_sync.dir', 0)
dut.fippts.write_regname('ext_sync.fpga_io_dir', 0)
util.info_msg("Enabling buffer")
dut.fipcore.write_regname('ext_sync.oe', 1)
dut.fippts.write_regname('ext_sync.oe', 1)
util.info_msg("Disabling termination")
dut.fipcore.write_regname('ext_sync.term_en', 0)
dut.fippts.write_regname('ext_sync.term_en', 0)
util.info_msg("Connecting synchronisation line to high voltage in relay box")
box.trigger_input_high()
time.sleep(DEL)
if dut.fipcore.read_regname('ext_sync_raw_input') == 1:
if dut.fippts.read_regname('ext_sync.raw_input') == 1:
result['Termination disabled'] = 1
util.info_msg("Read high input value")
else :
......@@ -101,12 +101,12 @@ def test_termination( dut, box ):
util.info_msg("Enabling termination (pulldown)")
dut.fipcore.write_regname('ext_sync.term_en', 1)
dut.fippts.write_regname('ext_sync.term_en', 1)
time.sleep(DEL)
if dut.fipcore.read_regname('ext_sync_raw_input') == 0:
if dut.fippts.read_regname('ext_sync.raw_input') == 0:
result['Termination enabled'] = 1
util.info_msg("Read low input value")
else :
......@@ -115,7 +115,7 @@ def test_termination( dut, box ):
###############################################################################
dut.fipcore.write_regname('ext_sync.term_en', 0)
dut.fippts.write_regname('ext_sync.term_en', 0)
box.trigger_input_low()
return result
......@@ -131,21 +131,21 @@ def test_oen( dut, box ):
util.info_msg("Setting synchronisation line to input")
dut.fipcore.write_regname('ext_sync.dir', 0)
dut.fipcore.write_regname('ext_sync.fpga_io_dir', 0)
dut.fippts.write_regname('ext_sync.dir', 0)
dut.fippts.write_regname('ext_sync.fpga_io_dir', 0)
util.info_msg("Disabling buffer")
dut.fipcore.write_regname('ext_sync.oe', 0)
dut.fippts.write_regname('ext_sync.oe', 0)
util.info_msg("Disabling termination")
dut.fipcore.write_regname('ext_sync.term_en', 0)
dut.fippts.write_regname('ext_sync.term_en', 0)
util.info_msg("Connecting synchronisation line to low voltage in relay box")
box.trigger_input_low()
time.sleep(DEL)
lowinput = dut.fipcore.read_regname('ext_sync_raw_input')
lowinput = dut.fippts.read_regname('ext_sync.raw_input')
if lowinput == 0:
util.info_msg("Read low input value")
......@@ -160,7 +160,7 @@ def test_oen( dut, box ):
time.sleep(DEL)
highinput = dut.fipcore.read_regname('ext_sync_raw_input')
highinput = dut.fippts.read_regname('ext_sync.raw_input')
if highinput == 0:
util.info_msg("Read low input value")
......@@ -194,23 +194,23 @@ def test_dir( dut, box ):
util.info_msg("Setting synchronisation line buffer to OUTPUT")
dut.fipcore.write_regname('ext_sync.dir', 1)
dut.fippts.write_regname('ext_sync.dir', 1)
util.info_msg("Setting synchronisation IO in FPGA to INPUT")
dut.fipcore.write_regname('ext_sync.fpga_io_dir', 0)
dut.fippts.write_regname('ext_sync.fpga_io_dir', 0)
util.info_msg("Enabling buffer")
dut.fipcore.write_regname('ext_sync.oe', 1)
dut.fippts.write_regname('ext_sync.oe', 1)
util.info_msg("Disabling termination")
dut.fipcore.write_regname('ext_sync.term_en', 0)
dut.fippts.write_regname('ext_sync.term_en', 0)
util.info_msg("Connecting synchronisation line to low voltage in relay box")
box.trigger_input_low()
time.sleep(DEL)
lowinput = dut.fipcore.read_regname('ext_sync_raw_input')
lowinput = dut.fippts.read_regname('ext_sync.raw_input')
if lowinput == 0:
util.info_msg("Read low input value")
......@@ -225,7 +225,7 @@ def test_dir( dut, box ):
time.sleep(DEL)
highinput = dut.fipcore.read_regname('ext_sync_raw_input')
highinput = dut.fippts.read_regname('ext_sync.raw_input')
if highinput == 0:
util.info_msg("Read low input value")
......@@ -233,7 +233,7 @@ def test_dir( dut, box ):
util.info_msg("Read high input value" )
box.trigger_input_low()
dut.fipcore.write_regname('ext_sync.dir', 0)
dut.fippts.write_regname('ext_sync.dir', 0)
time.sleep(DEL)
###############################################################################
......
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