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MasterFIP - Testing
Commit e18ab308 authored by Marek Gumiński's avatar Marek Gumiński
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Fixed test02 (except for watchdog) 

Watchdog test require changes is fmcmasterfip_core.
Small modification in test01 preventing unwanted blink of diodes.
parent d840928c
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Showing with 32 additions and 36 deletions
gateware/rtl/fmc_masterfip_csr_pts.vhd
View file @ e18ab308
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/fmc_masterfip_csr_pts.vhd
-- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
-- Created : Thu Mar 30 10:54:22 2017
-- Created : Thu Mar 30 13:56:49 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
......
gateware/rtl/masterfip_pts.vhd
View file @ e18ab308
......@@ -93,8 +93,8 @@ begin
core_rst <= core_rst_tmp or rst_i;
core_rst_n <= not core_rst;
macrocyc_load_p <= '1';
fd_host_rstn <= '0';
macrocyc_load_p <= '0';
fd_host_rstn <= '1';
---------------------------------------------------------
......
gateware/rtl/wbgen/masterfip_pts_csr.vhd
View file @ e18ab308
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.vhd
-- Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
-- Created : Thu Mar 30 10:54:26 2017
-- Created : Thu Mar 30 13:56:54 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
......
python/fmcmasterfip.py
View file @ e18ab308
......@@ -213,6 +213,8 @@ class fmcmasterfip:
self.fipcore.write_regname('rst.core', 1)
time.sleep(1)
self.fippts.write_regname('rst.core', 1)
def rst_fd(self):
self.fipcore.write_regname('rst.fd', 1)
......
python/regs/carrier_addrtable.py
View file @ e18ab308
......@@ -2,7 +2,7 @@
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/carrier_addrtable.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/carrier_csr.wb
# * Created : Thu Mar 30 10:54:24 2017
# * Created : Thu Mar 30 13:56:51 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/carrier_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......
python/regs/masterfip_addrtable.py
View file @ e18ab308
......@@ -2,7 +2,7 @@
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_addrtable.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
# * Created : Thu Mar 30 10:54:22 2017
# * Created : Thu Mar 30 13:56:49 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/fmc_masterfip_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......
python/regs/masterfip_csr.py
View file @ e18ab308
......@@ -2,7 +2,7 @@
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_csr.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
# * Created : Thu Mar 30 10:54:24 2017
# * Created : Thu Mar 30 13:56:51 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/ip_cores/gw-masterfip/rtl/wbgen/masterfip_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......
python/regs/masterfip_pts_csr.py
View file @ e18ab308
......@@ -2,7 +2,7 @@
#
# * File : /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/python/regs/masterfip_pts_csr.py
# * Author : auto-generated by wbgen2 from /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
# * Created : Thu Mar 30 10:54:26 2017
# * Created : Thu Mar 30 13:56:54 2017
#
# THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE /home/gumas/projects/cti/pts_masterfip/pts/fmcmasterfip/gateware/rtl/wbgen/masterfip_pts_csr.wb
# DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
......
python/test01.py
View file @ e18ab308
......@@ -79,12 +79,7 @@ def test_running_led( dut ):
dut.fipcore.write_regname( regname, 1 )
time.sleep(0.7)
dut.fipcore.write_regname( regname, 0 )
dut.fipcore.write_regname( 'led', 0 )
time.sleep(0.7)
dut.fipcore.write_regname( 'led.ext_sync_used', 1 )
time.sleep(0.7)
if not util.ask_user("Was there no more than one led enabled at a time?"):
util.err_msg("LED's verification failed!")
return 0
......
python/test02.py
View file @ e18ab308
......@@ -23,7 +23,7 @@ def wait_transmission_termination( dut, ret = 1000, val = 2 ):
util.info_msg("Waiting for termination of transmission (inactive CD_N)")
for i in xrange( ret ):
if dut.fipcore.read_regname('fd_rxcdn_cnt') > val-1:
if dut.fippts.read_regname('fd_rxcdn_cnt') > val-1:
# util.dbg_msg("Finished waiting for cdn after %d tries" % i)
break
......@@ -31,7 +31,7 @@ def wait_transmission_termination( dut, ret = 1000, val = 2 ):
time.sleep(0.001)
#
for i in xrange( ret ):
if dut.fipcore.read_regname('fd.cd_n') == 1:
if dut.fippts.read_regname('fd.cd_n') == 1:
util.info_msg("CD_N line did go high after transmission termination after %d tries." %i)
return True
else:
......@@ -46,12 +46,11 @@ def verify_rx_status( stat ):
test_result = {
'Number of bytes' : 0,
'CRC' : 0,
'Frame size' : 0,
'Frame format' : 0,
'Preamble' : 0
}
if util.bitvector(stat, 8, 16) != 10:
if util.bitvector(stat, 8, 16) != 7:
util.info_msg("Wrong number of bytes received")
else:
test_result['Number of bytes'] = 1
......@@ -126,7 +125,7 @@ def test_cdn( dut, maxtries = 50 ):
# no transmission
# cdn should be high
for i in xrange(10):
if dut.fipcore.read_regname('fd.cd_n') == 0 :
if dut.fippts.read_regname('fd.cd_n') == 0 :
if i == 9:
test_result['CD_N during idle'] = 0
util.err_msg("CD_N doesn't change value to inactive")
......@@ -142,13 +141,13 @@ def test_cdn( dut, maxtries = 50 ):
# after each request response will arrive
# counter should increase by 2
# dut.rst_core()
before = dut.fipcore.read_regname('fd_rxcdn_cnt')
before = dut.fippts.read_regname('fd_rxcdn_cnt')
util.info_msg ("CD_N counter value before transmission: %d" % before )
dut.send_id_dat(0x7F14)
time.sleep(1)
det = dut.fipcore.read_regname('fd_rxcdn_cnt')
det = dut.fippts.read_regname('fd_rxcdn_cnt')
det = det - before
......@@ -174,14 +173,14 @@ def test_txerr( dut, box, maxtries = 50 ):
'TX_ERR during idle' : 0
}
dut.fipcore.write_regname('test',0)
dut.fippts.write_regname('tx_corrupt',0)
########################################################################
util.section_msg("Checking if TX_ERR is not stack on active value")
for i in xrange(10):
# check pin value during bus idle
if dut.fipcore.read_regname('fd.txer') == 0 :
if dut.fippts.read_regname('fd.txer') == 0 :
test_result['TX_ERR during idle'] = 1
util.info_msg("TX_ERR is inactive during bus idle")
break
......@@ -196,7 +195,7 @@ def test_txerr( dut, box, maxtries = 50 ):
util.section_msg("Checking if TX_ERR is not going active during normal transmission")
dut.rst_core()
util.info_msg("TX_ERR counter before transmission: %d" % dut.fipcore.read_regname('fd_txerr_cnt') )
util.info_msg("TX_ERR counter before transmission: %d" % dut.fippts.read_regname('fd_txerr_cnt') )
dut.send_id_dat(0x7F14)
......@@ -206,7 +205,7 @@ def test_txerr( dut, box, maxtries = 50 ):
test_result = util.merge_dictionaries_prefix(test_result, tmp, "", "Transmission verification during TX_ERR test. " )
time.sleep(0.5)
det = dut.fipcore.read_regname('fd_txerr_cnt')
det = dut.fippts.read_regname('fd_txerr_cnt')
if det == 0:
......@@ -221,10 +220,10 @@ def test_txerr( dut, box, maxtries = 50 ):
util.section_msg("Checking if TX_ERR IS going active during corrupted transmission (serial output is constant 1)")
dut.rst_core()
util.info_msg("TX_ERR counter before transmission: %d" % dut.fipcore.read_regname('fd_txerr_cnt') )
util.info_msg("TX_ERR counter before transmission: %d" % dut.fippts.read_regname('fd_txerr_cnt') )
# corrupting serial output!!!!!
dut.fipcore.write_regname('test',1)
dut.fippts.write_regname('tx_corrupt',1)
dut.fipcore.write_regname('tx_ctrl', 1)
dut.fipcore.write_regname('tx_ctrl', 0)
......@@ -233,7 +232,7 @@ def test_txerr( dut, box, maxtries = 50 ):
dut.fipcore.write_regname('tx_ctrl', 0x202)
time.sleep(0.5)
det = dut.fipcore.read_regname('fd_txerr_cnt')
det = dut.fippts.read_regname('fd_txerr_cnt')
# since worldfip cable is disconnected
# transmission errors should be detected
......@@ -247,7 +246,7 @@ def test_txerr( dut, box, maxtries = 50 ):
# fixing serial output!!!!!
dut.fipcore.write_regname('test',0)
dut.fippts.write_regname('tx_corrupt',0)
wait_transmission_termination( dut )
return test_result
......@@ -261,7 +260,7 @@ def test_wdgn( dut ):
result = { }
for i in xrange(10):
tmp = dut.fipcore.read_regname('fd.wdgn')
tmp = dut.fippts.read_regname('fd.wdgn')
if tmp :
util.info_msg("WDG_N value during bus idle: %x" % tmp )
result['WDG_N during idle'] = 1
......@@ -286,7 +285,7 @@ def test_wdgn( dut ):
dut.fipcore.write_regname('tx_ctrl', 0x202)
wait_transmission_termination(dut, 100, 2 )
tmp = dut.fipcore.read_regname('fd.wdgn_latch')
tmp = dut.fippts.read_regname('fd.wdgn_latch')
if tmp > 0:
util.info_msg( "WDG_N was inactive after normal transmission" )
else:
......@@ -307,23 +306,23 @@ def test_wdgn( dut ):
wait_transmission_termination(dut, 100, 1 )
tmp = dut.fipcore.read_regname('fd.wdgn_latch')
tmp = dut.fippts.read_regname('fd.wdgn_latch')
if tmp == 1:
util.err_msg( "WDG_N did not go active during corrupted transmission\nCan't continue with FieldDrive RST_N test" )
result['WDG_N during long transmission'] = 0
result['RST_N'] = 0
return
return result
else:
util.info_msg( "WDG_N went active during corrupted transmission" )
result['WDG_N during long transmission'] = 1
tmp = dut.fipcore.read_regname('fd.wdgn')
tmp = dut.fippts.read_regname('fd.wdgn')
if tmp == 1:
util.err_msg( "WDG_N was inactive after corrupted transmission finished\nCan't continue with FieldDrive RST_N test" )
result['WDG_N latch in FieldDrive'] = 0
result['RST_N'] = 0
return
return result
else:
util.info_msg( "WDG_N was active after corrupted transmission finished" )
result['WDG_N latch in FieldDrive'] = 1
......@@ -333,7 +332,7 @@ def test_wdgn( dut ):
dut.rst_fd()
tmp = dut.fipcore.read_regname('fd.wdgn')
tmp = dut.fippts.read_regname('fd.wdgn')
if tmp == 0:
util.err_msg( "WDG_N did not go inactive after reset." )
result['RST_N'] = 0
......
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