minor cleanup to make simulators happier

1df956cb · Dimitris Lampridis · e3833c69 · 1df956cb · 1df956cb · 1df956cb
Commit 1df956cb authored Jan 30, 2019 by Dimitris Lampridis
5 changed files
--- a/hdl/rtl/endpoint/mt_ethernet_tx_framer.vhd
+++ b/hdl/rtl/endpoint/mt_ethernet_tx_framer.vhd
@@ -64,6 +64,8 @@ begin  -- arch
      if rst_n_i = '0' then
        state       <= IDLE;
        src_o.valid <= '0';
+        src_o.last  <= '0';
+        src_o.data  <= (others => '0');
      else
        case state is
          when IDLE =>
@@ -135,7 +137,9 @@ begin  -- arch
    end if;
  end process p_fsm;

--  src_o.tag   <= "00";
  src_o.error <= '0';
+  src_o.hdr   <= '0';
+
+  snk_o.pkt_ready <= '0';

 end architecture arch;
--- a/hdl/rtl/endpoint/mt_rmq_rx_deframer.vhd
+++ b/hdl/rtl/endpoint/mt_rmq_rx_deframer.vhd
@@ -93,8 +93,11 @@ begin
  src_o.error <= snk_i.error;
  src_o.valid <= snk_i.valid;
  src_o.data  <= snk_i.data;
-  src_o.hdr <= is_header;
--  src_o.tag   <= c_MT_STREAM_TAG_HEADER when valid_mask = '0' else c_MT_STREAM_TAG_PAYLOAD;
+  src_o.hdr   <= is_header;
+
+  snk_o.pkt_ready <= '0';
+
+  p_udp_length_o <= (others => '0');

  p_fsm : process(clk_i)
    variable next_state : t_state;

--- a/hdl/rtl/endpoint/mt_rmq_stream_register.vhd
+++ b/hdl/rtl/endpoint/mt_rmq_stream_register.vhd
@@ -121,4 +121,6 @@ begin
  src_o       <= src_out;
  snk_o.ready <= ready_reg;

+  snk_o.pkt_ready <= '0';
+
 end arch;
--- a/hdl/rtl/endpoint/mt_wr_sink.vhd
+++ b/hdl/rtl/endpoint/mt_wr_sink.vhd
@@ -143,12 +143,13 @@ begin  -- arch
      almost_full_o => full,
      q_valid_o     => q_valid);

-  post_data               <= fout(15 downto 0);
-  src_o.data(15 downto 0) <= post_data;
-  post_addr               <= fout(17 downto 16);
--  src_o.tag               <= post_addr;
-  src_o.last              <= q_valid and fout(18);
-  src_o.error             <= '0';  -- fixme
-  src_o.valid             <= q_valid;
+  post_data                <= fout(15 downto 0);
+  src_o.data(31 downto 16) <= (others => '0');
+  src_o.data(15 downto 0)  <= post_data;
+  post_addr                <= fout(17 downto 16);
+  src_o.last               <= q_valid and fout(18);
+  src_o.error              <= '0';  -- fixme
+  src_o.valid              <= q_valid;
+  src_o.hdr                <= '0';

 end arch;
--- a/hdl/rtl/endpoint/mt_wr_source.vhd
+++ b/hdl/rtl/endpoint/mt_wr_source.vhd
@@ -72,6 +72,8 @@ begin  -- arch

  snk_o.ready <= not full;

+  snk_o.pkt_ready <= '0';
+
  rd <= (not src_i.stall) and status_sent;
  we <= (snk_i.valid or snk_i.error) and (not full);