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Mock Turtle
Commit 21f29bfd authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl/sim: remove obsolete 'debug' testbench

parent 24c843cd
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hdl/testbench/debug/.gitignore deleted 100644 → 0
View file @ 24c843cd
work/
Makefile
modelsim.ini
transcript
*.wlf
hdl/testbench/debug/Manifest.py deleted 100644 → 0
View file @ 24c843cd
# HDLMake 'develop' branch required.
#
# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
# branch of hdlmake, commit db4e1ab.
sim_tool = "modelsim"
sim_top = "main"
action = "simulation"
target = "xilinx"
syn_device = "xc6slx150t"
vcom_opt = "-93 -mixedsvvh"
include_dirs = [
"../include",
"../../ip_cores/general-cores/sim/",
"../../ip_cores/urv-core/rtl/",
]
files = [
"main.sv",
]
modules = {
"local" : [
"../../rtl",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/urv-core.git",
],
}
fetchto = "../../ip_cores"
hdl/testbench/debug/main.sv deleted 100644 → 0
View file @ 24c843cd
//------------------------------------------------------------------------------
// CERN BE-CO-HT
// Mock Turtle
// https://gitlab.cern.ch/coht/mockturtle
//------------------------------------------------------------------------------
//
// unit name: main
//
// description: A SystemVerilog testbench for the supplied SVEC MT demo.
//
//------------------------------------------------------------------------------
// Copyright CERN 2018
//------------------------------------------------------------------------------
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 2.0 (the "License"); you may not use this file except
// in compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-2.0.
// Unless required by applicable law or agreed to in writing, software,
// hardware and materials distributed under this License is distributed on an
// "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
// or implied. See the License for the specific language governing permissions
// and limitations under the License.
//------------------------------------------------------------------------------
import wishbone_pkg::*;
`include "vhd_wishbone_master.svh"
`include "mt_mqueue_host_driver.svh"
`include "mock_turtle_driver.svh"
`timescale 1ns/1ps
module main;
reg rst_n = 0;
reg clk_sys = 0;
reg clk_cpu = 0;
always #4ns clk_cpu <= ~clk_cpu;
always@(posedge clk_cpu)
clk_sys <= ~clk_sys;
initial begin
repeat(20) @(posedge clk_sys);
rst_n = 1;
end
wire host_irq;
IVHDWishboneMaster Host ( clk_sys, rst_n );
mock_turtle_core #
(
.g_double_core_clock(1'b0),
//.g_cpu_arch("LM32")
.g_cpu_arch("URV")
)
DUT (
.clk_i (clk_sys),
.rst_n_i (rst_n),
.host_slave_i (Host.master.out),
.host_slave_o (Host.master.in),
.host_irq_o(host_irq)
);
initial begin
MQueueHost hmq;
MTCPUControl cpu_csr;
uint64_t rv;
CBusAccessor host_acc;
uint32_t v;
#10us;
host_acc = Host.get_accessor();
cpu_csr = new ( Host.get_accessor(), 'hc000 );
hmq = new ( Host.get_accessor(), 0 );
// enable all IRQs
host_acc.write(`MQUEUE_GCR_IRQ_MASK, 'hffff);
cpu_csr.init();
// enable debug message interrupts for CPU0
cpu_csr.debug_int_enable(0, 1);
// clear reset
cpu_csr.writel('h4, 0);
// clear force
cpu_csr.writel('h34, 0);
cpu_csr.readl('h30, v);
$display("CPU status: %x", v);
cpu_csr.writel('h3c, 'h001005b7); // la t1, 0x10001c
cpu_csr.writel('h3c, 'h01c5e593);
cpu_csr.writel('h3c, 'h06800513); // li t0, 'h'
cpu_csr.writel('h3c, 'h00a58023); // sb t0, 0(t1)
cpu_csr.writel('h3c, 'h7d459073); // csrrw zero, 0x7d4, t1
cpu_csr.writel('h3c, 'h06300513); // li t0, 0x63 (bra 0)
cpu_csr.writel('h3c, 'h00502023); // sw t0, 0(zero)
while (1) begin
cpu_csr.readl('h38, v);
if ((v & 1) == 1'b1)
break;
end
//cpu_csr.load_firmware (0, "../sw/hw-tests/hello/hello.ram.lm32");
//cpu_csr.load_firmware (0, "../sw/hw-tests/hello/hello.ram.urv");
//cpu_csr.reset_core(0, 0);
$display("CPU0 started\n");
cpu_csr.readl('h44, v);
$display("mbx data: %x", v);
cpu_csr.writel('h44, 32'h12345678);
cpu_csr.readl('h44, v);
$display("mbx data: %x", v);
cpu_csr.writel('h3c, 'h00100073); // ebreak
forever begin
cpu_csr.update();
while(host_irq)
hmq.update();
#1us;
@(posedge clk_sys);
end
end // initial begin
endmodule
hdl/testbench/debug/run.do deleted 100644 → 0
View file @ 24c843cd
vsim -L unisim work.main -novopt
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 1000us
\ No newline at end of file
hdl/testbench/debug/wave.do deleted 100644 → 0
View file @ 24c843cd
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