Commit 3bfff1d4 authored by Federico Vaga's avatar Federico Vaga

kernel: move common header to include directory

Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent e8cc350d
/*
Register definitions for slave core: WR Node CPU Control/Status registers block
* File : wrn_cpu_csr.h
* Author : auto-generated by wbgen2 from wrn_cpu_csr.wb
* Created : Mon Dec 8 15:40:37 2014
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrn_cpu_csr.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WRN_CPU_CSR_WB
#define __WBGEN2_REGDEFS_WRN_CPU_CSR_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Application ID Register */
/* definitions for register: CPU Reset Register */
/* definitions for register: CPU Enable Register */
/* definitions for register: CPU Upload Address Register */
/* definitions for field: Address in reg: CPU Upload Address Register */
#define WRN_CPU_CSR_UADDR_ADDR_MASK WBGEN2_GEN_MASK(0, 20)
#define WRN_CPU_CSR_UADDR_ADDR_SHIFT 0
#define WRN_CPU_CSR_UADDR_ADDR_W(value) WBGEN2_GEN_WRITE(value, 0, 20)
#define WRN_CPU_CSR_UADDR_ADDR_R(reg) WBGEN2_GEN_READ(reg, 0, 20)
/* definitions for register: Core Select Register */
/* definitions for register: Core Count Register */
/* definitions for register: Core Memory Size */
/* definitions for register: CPU Upload Data Register */
/* definitions for register: CPU Debug Register */
/* definitions for field: JTAG data in reg: CPU Debug Register */
#define WRN_CPU_CSR_DBG_JTAG_JDATA_MASK WBGEN2_GEN_MASK(0, 8)
#define WRN_CPU_CSR_DBG_JTAG_JDATA_SHIFT 0
#define WRN_CPU_CSR_DBG_JTAG_JDATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define WRN_CPU_CSR_DBG_JTAG_JDATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for field: JTAG address in reg: CPU Debug Register */
#define WRN_CPU_CSR_DBG_JTAG_JADDR_MASK WBGEN2_GEN_MASK(8, 3)
#define WRN_CPU_CSR_DBG_JTAG_JADDR_SHIFT 8
#define WRN_CPU_CSR_DBG_JTAG_JADDR_W(value) WBGEN2_GEN_WRITE(value, 8, 3)
#define WRN_CPU_CSR_DBG_JTAG_JADDR_R(reg) WBGEN2_GEN_READ(reg, 8, 3)
/* definitions for field: JTAG reset in reg: CPU Debug Register */
#define WRN_CPU_CSR_DBG_JTAG_RSTN WBGEN2_GEN_MASK(16, 1)
/* definitions for field: JTAG TCK in reg: CPU Debug Register */
#define WRN_CPU_CSR_DBG_JTAG_TCK WBGEN2_GEN_MASK(17, 1)
/* definitions for field: JTAG Update in reg: CPU Debug Register */
#define WRN_CPU_CSR_DBG_JTAG_UPDATE WBGEN2_GEN_MASK(18, 1)
/* definitions for register: CPU Debug Message Register */
/* definitions for field: Debug message byte for the selected core in reg: CPU Debug Message Register */
#define WRN_CPU_CSR_DBG_MSG_DATA_MASK WBGEN2_GEN_MASK(0, 8)
#define WRN_CPU_CSR_DBG_MSG_DATA_SHIFT 0
#define WRN_CPU_CSR_DBG_MSG_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define WRN_CPU_CSR_DBG_MSG_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: CPU Debug Messge Poll Register */
/* definitions for field: Debug Message data available in reg: CPU Debug Messge Poll Register */
#define WRN_CPU_CSR_DBG_POLL_READY_MASK WBGEN2_GEN_MASK(0, 8)
#define WRN_CPU_CSR_DBG_POLL_READY_SHIFT 0
#define WRN_CPU_CSR_DBG_POLL_READY_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define WRN_CPU_CSR_DBG_POLL_READY_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: CPU Debug Messge Interrupt Mask Register */
/* definitions for field: Per-CPU Debug Message Interrupt Enable in reg: CPU Debug Messge Interrupt Mask Register */
#define WRN_CPU_CSR_DBG_IMSK_ENABLE_MASK WBGEN2_GEN_MASK(0, 8)
#define WRN_CPU_CSR_DBG_IMSK_ENABLE_SHIFT 0
#define WRN_CPU_CSR_DBG_IMSK_ENABLE_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define WRN_CPU_CSR_DBG_IMSK_ENABLE_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* [0x0]: REG Application ID Register */
#define WRN_CPU_CSR_REG_APP_ID 0x00000000
/* [0x4]: REG CPU Reset Register */
#define WRN_CPU_CSR_REG_RESET 0x00000004
/* [0x8]: REG CPU Enable Register */
#define WRN_CPU_CSR_REG_ENABLE 0x00000008
/* [0xc]: REG CPU Upload Address Register */
#define WRN_CPU_CSR_REG_UADDR 0x0000000c
/* [0x10]: REG Core Select Register */
#define WRN_CPU_CSR_REG_CORE_SEL 0x00000010
/* [0x14]: REG Core Count Register */
#define WRN_CPU_CSR_REG_CORE_COUNT 0x00000014
/* [0x18]: REG Core Memory Size */
#define WRN_CPU_CSR_REG_CORE_MEMSIZE 0x00000018
/* [0x1c]: REG CPU Upload Data Register */
#define WRN_CPU_CSR_REG_UDATA 0x0000001c
/* [0x20]: REG CPU Debug Register */
#define WRN_CPU_CSR_REG_DBG_JTAG 0x00000020
/* [0x24]: REG CPU Debug Message Register */
#define WRN_CPU_CSR_REG_DBG_MSG 0x00000024
/* [0x28]: REG CPU Debug Messge Poll Register */
#define WRN_CPU_CSR_REG_DBG_POLL 0x00000028
/* [0x2c]: REG CPU Debug Messge Interrupt Mask Register */
#define WRN_CPU_CSR_REG_DBG_IMSK 0x0000002c
#endif
......@@ -3,6 +3,7 @@ CROSS_COMPILE_TARGET ?= lm32-elf-
INSTALL_PREFIX ?= .
PATH_COMMON_RT ?= .
PATH_COMMON_H ?= ../include
WRNC ?= ../../
CC = $(CROSS_COMPILE_TARGET)gcc
LD = $(CROSS_COMPILE_TARGET)ld
......@@ -14,18 +15,19 @@ RT_GIT_VERSION = 0x$(shell cd ../../..; git rev-parse --short=8 HEAD)
CFLAGS += -DWRNODE_RT -g -O3 -mmultiply-enabled -mbarrel-shift-enabled
CFLAGS += -I.
CFLAGS += -I$(PATH_COMMON)/rt
CFLAGS += -I$(PATH_COMMON)/include
CFLAGS += -I$(WRNC)/applications/common/rt
CFLAGS += -I$(WRNC)/applications/common/include
CFLAGS += -I$(WRNC)/include
CFLAGS += -DGIT_VERSION=$(RT_GIT_VERSION)
CFLAGS += $(EXTRA_CFLAGS)
OBJS += $(PATH_COMMON)/rt/wrn-crt0.o
OBJS += $(PATH_COMMON)/rt/vsprintf-xint.o
OBJS += $(PATH_COMMON)/rt/printf.o
OBJS += $(PATH_COMMON)/rt/rt-common.o
OBJS += $(WRNC)/applications/common/rt/wrn-crt0.o
OBJS += $(WRNC)/applications/common/rt/vsprintf-xint.o
OBJS += $(WRNC)/applications/common/rt/printf.o
OBJS += $(WRNC)/applications/common/rt/rt-common.o
LDSCRIPT = $(PATH_COMMON)/rt/wrnode.ld
LDSCRIPT = $(WRNC)/applications/common/rt/wrnode.ld
all: $(OUTPUT)
......
......@@ -8,7 +8,7 @@ WRNC ?= ../../../
LIB = libdemo.a
LOBJ := libdemo.o
CFLAGS += -Wall -ggdb -O2 -I. -I../include -I$(WRNC)/lib -I$(WRNC)/kernel $(EXTRACFLAGS)
CFLAGS += -Wall -ggdb -O0 -I. -I../include -I$(WRNC)/include -I$(WRNC)/lib $(EXTRACFLAGS)
LDLIBS += -L. -ldemo
......
OBJS = autodemo.o
OUTPUT = autodemo
PATH_COMMON = ../../../common/
WRNC = ../../../../
include $(PATH_COMMON)/rt/Makefile
include $(WRNC)/applications/common/rt/Makefile
OBJS = rt-demo.o
OUTPUT = rt-demo
PATH_COMMON = ../../../common/
WRNC = ../../../../
EXTRA_CFLAGS += -I../../include
EXTRA_CFLAGS += -DRTPERFORMANCE
include $(PATH_COMMON)/rt/Makefile
include $(WRNC)/applications/common/rt/Makefile
......@@ -7,7 +7,7 @@ DESTDIR ?= /usr/local
WRNC ?= ../../../
CFLAGS += -Wall -ggdb -I. -I../include -I$(WRNC)/lib -I$(WRNC)/kernel -I../lib $(EXTRACFLAGS)
CFLAGS += -Wall -ggdb -I. -I../include -I$(WRNC)/include -I$(WRNC)/lib -I../lib
LDLIBS += -L../lib -ldemo -L$(WRNC)/lib -lwrnc
PROGS := demo
......
......@@ -14,7 +14,8 @@ LOBJ += libwrtd-logging.o
LOBJ += libwrtd-input.o
LOBJ += libwrtd-output.o
CFLAGS += -Wall -ggdb -O2 -I. -I../include -I$(WRNC)/lib -I$(WRNC)/kernel -I$(LIBFD) -I$(LIBTDC) -I$(LIBFD)/../kernel $(EXTRACFLAGS)
CFLAGS += -Wall -ggdb -O2 -I. -I../include -I$(WRNC)/include -I$(WRNC)/lib -I$(LIBFD) -I$(LIBTDC) -I$(LIBFD)/../kernel
CFLAGS += $(EXTRACFLAGS)
LDLIBS += -L. -lwrtd
......
OBJS := rt-fd.o
OBJS += ../common/loop-queue.o
OUTPUT = rt-fd
PATH_COMMON = ../../../common/
WRNC = ../../../../
EXTRA_CFLAGS += -I../../include
EXTRA_CFLAGS += -I../common
include $(PATH_COMMON)/rt/Makefile
include $(WRNC)/applications/common/rt/Makefile
OBJS := rt-tdc.o
OBJS += ../common/loop-queue.o
OUTPUT = rt-tdc
PATH_COMMON = ../../../common/
WRNC = ../../../../
EXTRA_CFLAGS += -I../../include
EXTRA_CFLAGS += -I../common
include $(PATH_COMMON)/rt/Makefile
include $(WRNC)/applications/common/rt/Makefile
......@@ -7,7 +7,8 @@ DESTDIR ?= /usr/local
WRNC ?= ../../../
CFLAGS += -Wall -ggdb -I. -I../include -I$(WRNC)/lib -I$(WRNC)/kernel -I../lib $(EXTRACFLAGS)
CFLAGS += -Wall -ggdb -I. -I../include -I$(WRNC)/include -I$(WRNC)/lib -I../lib
CFLAGS += $(EXTRACFLAGS)
LDLIBS += -L../lib -lwrtd -L$(WRNC)/lib -lwrnc
PROGS := wrtd-boot
......
......@@ -17,7 +17,9 @@ endif
ccflags-y += -DGIT_VERSION=\"$(GIT_VERSION)\" \
-I$(FMC_BUS)/kernel/include \
-I$(src)
-I$(src) \
-I$(src)/../include
ccflags-$(CONFIG_WRNC_DEBUG) += -DDEBUG
......
/*
* This work is part of the White Rabbit Node Core project.
*
* Copyright (C) 2013-2014 CERN (www.cern.ch)
* Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
/*.
* White Rabbit Node Core
*
* mqueue.h: MQ register definitions (Host side)
*/
#ifndef __MQUEUE_H
#define __MQUEUE_H
// Nax number of supported incoming/outgoing slots
#define MAX_MQUEUE_SLOTS 16
// HMQ base address (wrs to the base addr of the WR Node Core)
#define BASE_HMQ 0x00000
// Global Control Registers base address, relative to BASE_HMQ (SLOT_COUNT, SLOT_STATUS, interrupt control, etc).
// Common for all incoming/outgoing slots in the queue
#define MQUEUE_BASE_GCR (0x0)
// Incoming slot base address, relative to BASE_HMQ
#define MQUEUE_BASE_IN(slot) (0x4000 + (slot) * 0x400)
// Outgoung slot base address, relative to BASE_HMQ
#define MQUEUE_BASE_OUT(slot) (0x8000 + (slot) * 0x400)
// MQ slot registers, relative to the base address of each slot: MQUEUE_BASE_IN(slot_no) or MQUEUE_BASE_OUT(slot_no)
#define MQUEUE_SLOT_COMMAND 0
// Status register
#define MQUEUE_SLOT_STATUS 4
// Start of data block
#define MQUEUE_SLOT_DATA_START 8
// Layout of MQUEUE_SLOT_COMMAND register:
// Claim: prepares a slot to send a message (w/o)
#define MQUEUE_CMD_CLAIM (1<<24)
// Purge: erases all messages from a slot (w/o)
#define MQUEUE_CMD_PURGE (1<<25)
// Ready: pushes the message to the queue. (w/o)
#define MQUEUE_CMD_READY (1<<26)
// Discard: removes last message from the queue, advancing to the next one (w/o)
#define MQUEUE_CMD_DISCARD (1<<27)
// Size of the message to be sent, in words (w/o). Must be written together with the
// READY command, e.g.:
// writel (MQUEUE_CMD_READY | 10, MQUEUE_SLOT_COMMAND);
#define MQUEUE_CMD_MSG_SIZE_MASK 0xff
#define MQUEUE_CMD_MSG_SIZE_SHIFT 0
// Layout of MQUEUE_SLOT_STATUS register:
// [0] Slot is full
#define MQUEUE_SLOT_STATUS_FULL (1<<0)
// [1] Slot is empty
#define MQUEUE_SLOT_STATUS_EMPTY (1<<1)
// [15:8] Number of occupied entries
#define MQUEUE_SLOT_STATUS_OCCUPIED_SHIFT 8
#define MQUEUE_SLOT_STATUS_OCCUPIED_MASK 0xff00
// [23:16] Number of transferred words in the message currently on top of the slot
#define MQUEUE_SLOT_STATUS_MSG_SIZE_SHIFT 16
#define MQUEUE_SLOT_STATUS_MSG_SIZE_MASK 0xff0000
// [31:28] log2(number of words in the slot).
#define MQUEUE_SLOT_STATUS_LOG2_WIDTH_SHIFT 28
#define MQUEUE_SLOT_STATUS_LOG2_WIDTH_MASK 0xf0000000
// [7:2] log2(number of entries in the slot).
#define MQUEUE_SLOT_STATUS_LOG2_ENTRIES_SHIFT 2
#define MQUEUE_SLOT_STATUS_LOG2_ENTRIES_MASK 0xfc
//
// MQ Global Control Registers.Adresses relative to MQUEUE_BASE_GCR:
//
#define MQUEUE_GCR_INCOMING_STATUS_MASK (0x0000ffff)
// Number of slots in this implementation of HMQ
#define MQUEUE_GCR_SLOT_COUNT 0
// EMPTY bits of all slots in a single register (for polling/IRQ status)
#define MQUEUE_GCR_SLOT_STATUS 4
// Interrupt mask (Outgoing: EMPTY, Incoming: not EMPTY)
#define MQUEUE_GCR_IRQ_MASK 8
// IRQ Coalescing register (reserved for future use)
#define MQUEUE_GCR_IRQ_COALESCE 12
// Layout of SLOT_COUNT register
// [7:0] Number of Incoming slots
#define MQUEUE_GCR_SLOT_COUNT_N_IN_SHIFT 0
#define MQUEUE_GCR_SLOT_COUNT_N_IN_MASK 0xff
// [15:8] Number of Outgoing slots
#define MQUEUE_GCR_SLOT_COUNT_N_OUT_SHIFT 8
#define MQUEUE_GCR_SLOT_COUNT_N_OUT_MASK 0xff00
// Layout of SLOT_STATUS register
// [15:0] Outgoing slots status. Each bit indicates a NOT EMPTY status of the corresponding outgoing slot
#define MQUEUE_GCR_SLOT_STATUS_OUT_SHIFT 0
#define MQUEUE_GCR_SLOT_STATUS_OUT_MASK 0xffff
// [31:16] Incoming slots status. Each bit indicates an EMPTY status of the corresponding incoming slot
#define MQUEUE_GCR_SLOT_STATUS_IN_SHIFT 16
#define MQUEUE_GCR_SLOT_STATUS_IN_MASK 0xffff0000
// Layout of IRQ_MASK register
// [15:0] Outgoing slots status interrupt mask. Each bit enables generation of interrupt on NOT EMPTY status of the corresponding outgoing slot.
#define MQUEUE_GCR_IRQ_MASK_OUT_SHIFT 0
#define MQUEUE_GCR_IRQ_MASK_OUT_MASK 0xffff
// [31:16] Incoming slots status interrupt mask. Each bit enables generation of interrupt on EMPTY status of the corresponding incoming slot.
#define MQUEUE_GCR_IRQ_MASK_IN_SHIFT 16
#define MQUEUE_GCR_IRQ_MASK_IN_MASK 0xffff0000
// Layout of IRQ_COALSESCE register
// The register is left for future IRQ coalescing support (if ever needed)
#endif
/*
Register definitions for slave core: WR Node CPU Local Registers
* File : wrn_cpu_lr.h
* Author : auto-generated by wbgen2 from wrn_cpu_lr.wb
* Created : Mon Dec 8 15:40:37 2014
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrn_cpu_lr.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WRN_CPU_LR_WB
#define __WBGEN2_REGDEFS_WRN_CPU_LR_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: CPU Polling Register */
/* definitions for field: HMQ Slot Status in reg: CPU Polling Register */
#define WRN_CPU_LR_POLL_HMQ_MASK WBGEN2_GEN_MASK(0, 16)
#define WRN_CPU_LR_POLL_HMQ_SHIFT 0
#define WRN_CPU_LR_POLL_HMQ_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define WRN_CPU_LR_POLL_HMQ_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: RMQ Slot Status in reg: CPU Polling Register */
#define WRN_CPU_LR_POLL_RMQ_MASK WBGEN2_GEN_MASK(16, 16)
#define WRN_CPU_LR_POLL_RMQ_SHIFT 16
#define WRN_CPU_LR_POLL_RMQ_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define WRN_CPU_LR_POLL_RMQ_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: CPU Status Register */
/* definitions for field: WR Link Up in reg: CPU Status Register */
#define WRN_CPU_LR_STAT_WR_LINK WBGEN2_GEN_MASK(0, 1)
/* definitions for field: WR Time OK in reg: CPU Status Register */
#define WRN_CPU_LR_STAT_WR_TIME_OK WBGEN2_GEN_MASK(1, 1)
/* definitions for field: WR Aux Clock OK in reg: CPU Status Register */
#define WRN_CPU_LR_STAT_WR_AUX_CLOCK_OK_MASK WBGEN2_GEN_MASK(2, 8)
#define WRN_CPU_LR_STAT_WR_AUX_CLOCK_OK_SHIFT 2
#define WRN_CPU_LR_STAT_WR_AUX_CLOCK_OK_W(value) WBGEN2_GEN_WRITE(value, 2, 8)
#define WRN_CPU_LR_STAT_WR_AUX_CLOCK_OK_R(reg) WBGEN2_GEN_READ(reg, 2, 8)
/* definitions for field: Core ID in reg: CPU Status Register */
#define WRN_CPU_LR_STAT_CORE_ID_MASK WBGEN2_GEN_MASK(28, 4)
#define WRN_CPU_LR_STAT_CORE_ID_SHIFT 28
#define WRN_CPU_LR_STAT_CORE_ID_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define WRN_CPU_LR_STAT_CORE_ID_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: TAI Cycles */
/* definitions for register: TAI Seconds */
/* definitions for register: GPIO Input */
/* definitions for register: GPIO Set */
/* definitions for register: GPIO Clear */
/* definitions for register: Debug Message Output */
/* [0x0]: REG CPU Polling Register */
#define WRN_CPU_LR_REG_POLL 0x00000000
/* [0x4]: REG CPU Status Register */
#define WRN_CPU_LR_REG_STAT 0x00000004
/* [0x8]: REG TAI Cycles */
#define WRN_CPU_LR_REG_TAI_CYCLES 0x00000008
/* [0xc]: REG TAI Seconds */
#define WRN_CPU_LR_REG_TAI_SEC 0x0000000c
/* [0x10]: REG GPIO Input */
#define WRN_CPU_LR_REG_GPIO_IN 0x00000010
/* [0x14]: REG GPIO Set */
#define WRN_CPU_LR_REG_GPIO_SET 0x00000014
/* [0x18]: REG GPIO Clear */
#define WRN_CPU_LR_REG_GPIO_CLEAR 0x00000018
/* [0x1c]: REG Debug Message Output */
#define WRN_CPU_LR_REG_DBG_CHR 0x0000001c
#endif
......@@ -6,7 +6,7 @@
LIB = libwrnc.a
LOBJ := libwrnc.o
CFLAGS += -Wall -ggdb -I. -I../kernel $(EXTRACFLAGS)
CFLAGS += -Wall -ggdb -I. -I$(WRNC)/include $(EXTRACFLAGS)
LDFLAGS = -L. -lwrnc
......
......@@ -6,7 +6,9 @@
DESTDIR ?= /usr/local
WRNC ?= ../
CFLAGS += -Wall -ggdb -I$(WRNC)/lib -I$(WRNC)/kernel $(EXTRACFLAGS)
CFLAGS += -Wall -ggdb -I$(WRNC)/lib
CFLAGS += -I$(WRNC)/include
CFLAGS += $(EXTRACFLAGS)
LDLIBS += -L$(WRNC)/lib -lwrnc -lpthread
PROGS := wrnc-count
PROGS += lswrnc
......
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