Commit 42759da3 authored by Dimitris Lampridis's avatar Dimitris Lampridis Committed by Federico Vaga

sw:firmware: Add rule to the MT build system to also produce "bram" outputs.

"bram" files are used in order to produce FPGA bitstreams with the MT CPUs
preprogrammed with their firmware.
Signed-off-by: Dimitris Lampridis's avatarDimitris Lampridis <dimitris.lampridis@cern.ch>
Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent df18fb3c
......@@ -25,6 +25,8 @@ TRTL_SW ?= $(TRTL)/software
TRTL_FW ?= $(TRTL_SW)/firmware
TRTL_HDL ?= $(TRTL)/hdl/rtl
GEN_CORES ?= $(TRTL)/hdl/ip_cores/general-cores
RT_GIT_VERSION = 0x$(shell git rev-parse --short=8 HEAD || echo "0") # empty if git is not there
# header file generated from the .config
AUTOCONF = $(src)/$(BUILDDIR)/include/generated/autoconf.h
......@@ -57,6 +59,8 @@ OBJCOPY = $(CROSS_COMPILE_TARGET)objcopy
SIZE = $(CROSS_COMPILE_TARGET)size
STRIP = $(CROSS_COMPILE_TARGET)strip
MEM_INIT_GEN = $(GEN_CORES)/tools/mem_init_gen.py
CFLAGS += -Wall -D__TRTL_FIRMWARE__ -DARCH=urv
CFLAGS += -I.
CFLAGS += -I$(BUILDDIR)/include
......@@ -98,7 +102,7 @@ MOCKTURTLE_LDSCRIPT ?= $(TRTL_FW)/urv/mockturtle.ld
.PHONY: all clean cleanall
all: $(build_output).bin
all: $(build_output).bram $(build_output).bin $(build_output).elf
WBGEN_FILES = mt_cpu_csr.wb mt_cpu_lr.wb
WBGEN_HEADERS = mockturtle_cpu_csr.h mockturtle_cpu_lr.h
......@@ -131,6 +135,9 @@ $(build_output).bin: $(build_output).elf
${OBJCOPY} --remove-section .smem -O binary $(build_output).elf $(build_output).bin
$(SIZE) $(build_output).elf
$(build_output).bram: $(build_output).bin
$(MEM_INIT_GEN) -i $(build_output).bin > $(build_output).bram
$(BUILDDIR)/urv/emulate.o: urv/emulate.c
${CC} $(DEPFLAGS) $(CFLAGS) -march=rv32i -c $< -o $@
$(POSTCOMPILE)
......@@ -146,7 +153,7 @@ $(BUILDDIR)/%.o: %.S
$(POSTCOMPILE)
clean:
rm -f $(build_output).bin $(build_output).elf
rm -f $(build_output).bram $(build_output).bin $(build_output).elf
rm -rf $(BUILDDIR)
clean-dot-config:
......
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