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Commit 973d755c authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: introduce hello world test software for top testbench 

Now have working lm32 and urv hello world sim.
parent f5dbdb5e
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Showing with 1563 additions and 482 deletions
.gitignore deleted 100644 → 0
View file @ f5dbdb5e
*.bit
*.bin
*.ngc
*~
#*
*.ini
*.log
work
*.vstf
*.wlf
*.version
*.cfg
*.bk
*#
*.bak
run.tcl
.emacs*
.#*
transcript
*.par
*.pcf
*.pad
*.ngr
*.ncd
*.gise
*.ptwx
*.twx
*.unroutes
*.ut
*.xpi
*.bgn
*.bld
*.cmd_log
*.drc
*.lso
*.ngd
*.prj
*.stx
*.syr
*.twr
*.xst
*_bitgen.xwbt
*_envsettings.html
*_map.map
*_map.mrp
*_map.ngm
*_map.xrpt
*_ngdbuild.xrpt
*_pad.csv
*_pad.txt
*_par.xrpt
*.html
*.xml
*_usage.xml
*_xst.xrpt
xlnx_auto_0_xdb
iseconfig
_ngo
_xmsgs
*.o
*.pdf
*.aux
*.out
*.psr
*.xdl
*.orig
pa.fromNcd.tcl
pa.fromNetlist.tcl
planAhead_run_*
*.vcd
*.wlf
work/
*.elf
.Xil
xst/
*stacktrace*
rtl/*.h
scp.sh
disasm.S
*.mif
*.asy
*.xco
*.debug
.gitmodules
View file @ 973d755c
......@@ -16,3 +16,6 @@
[submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
[submodule "hdl/ip_cores/urv-core"]
path = hdl/ip_cores/urv-core
url = git://ohwr.org/hdl-core-lib/urv-core.git
general-cores @ 23f71bcc
Subproject commit 8cd05d796abf0e494a367c15ce4fde1535751efe
Subproject commit 23f71bcc79d8cf6d5a076c961e64003502fb1d47
gn4124-core @ 9b9625bb
Subproject commit e3a0bf97e125020c83bff6e40199a717e7fda738
Subproject commit 9b9625bb4270114266cd357f199d649f3d799f04
urv-core @ f1fcd338
Subproject commit f1fcd338aefb276b89c502c7c52d6e7b26cebdfe
wr-cores @ 69cc4cc3
Subproject commit 573ac5a938e53c6bedaee13b75e1c0c6c6e311db
Subproject commit 69cc4cc3132530c836cd57ce1b282e8377fe7a07
hdl/rtl/cpu/Manifest.py
View file @ 973d755c
files = [
"mt_cpu_cb.vhd",
"mt_cpu_csr_wbgen2_pkg.vhd",
"mt_cpu_csr_wb.vhd",
"mt_cpu_iram.vhd",
"mt_cpu_lr_wbgen2_pkg.vhd",
"mt_cpu_lr_wb.vhd",
"mt_lm32_wrapper.vhd",
"mt_private_pkg.vhd",
"mt_urv_wrapper.vhd",
"mt_trace_profiler.vhd",
"mt_tpu_csr_wb.vhd",
"mt_tpu_csr_wbgen2_pkg.vhd"
];
"mt_cpu_cb.vhd",
"mt_cpu_csr_wbgen2_pkg.vhd",
"mt_cpu_csr_wb.vhd",
"mt_cpu_iram.vhd",
"mt_cpu_lr_wbgen2_pkg.vhd",
"mt_cpu_lr_wb.vhd",
"mt_lm32_wrapper.vhd",
"mt_private_pkg.vhd",
"mt_urv_wrapper.vhd",
"mt_trace_profiler.vhd",
"mt_tpu_csr_wb.vhd",
"mt_tpu_csr_wbgen2_pkg.vhd",
]
hdl/rtl/mqueue/Manifest.py
View file @ 973d755c
files = [ "mt_mqueue_host.vhd",
"mt_mqueue_remote.vhd",
"mt_rmq_outgoing_slot.vhd",
"mt_rmq_incoming_slot.vhd",
"mt_mqueue_irq_unit.vhd",
"mt_mqueue_pkg.vhd",
"mt_mqueue_slot.vhd",
"mt_mqueue_remote.vhd",
"mt_mqueue_wishbone_slave.vhd",
"mt_ethernet_tx_framer.vhd",
"mt_rmq_rx_deframer.vhd",
"mt_rmq_rx_path.vhd",
"mt_rmq_tx_path.vhd",
"mt_stream_register.vhd",
"mt_udp_tx_framer.vhd",
"mt_rmq_packet_output.vhd",
"mt_wr_sink.vhd",
"mt_wr_source.vhd"];
files = [
"mt_mqueue_host.vhd",
"mt_mqueue_remote.vhd",
"mt_rmq_outgoing_slot.vhd",
"mt_rmq_incoming_slot.vhd",
"mt_mqueue_irq_unit.vhd",
"mt_mqueue_pkg.vhd",
"mt_mqueue_slot.vhd",
"mt_mqueue_remote.vhd",
"mt_mqueue_wishbone_slave.vhd",
"mt_ethernet_tx_framer.vhd",
"mt_rmq_rx_deframer.vhd",
"mt_rmq_rx_path.vhd",
"mt_rmq_tx_path.vhd",
"mt_stream_register.vhd",
"mt_udp_tx_framer.vhd",
"mt_rmq_packet_output.vhd",
"mt_wr_sink.vhd",
"mt_wr_source.vhd",
]
hdl/rtl/smem/Manifest.py
View file @ 973d755c
files = ["mt_shared_mem.vhd"]
\ No newline at end of file
files = [
"mt_shared_mem.vhd",
]
hdl/syn/spec/mt_demo/.gitignore 0 → 100644
View file @ 973d755c
*
!.gitignore
!Manifest.py
hdl/syn/spec/mt_demo/Manifest.py 0 → 100644
View file @ 973d755c
action = "synthesis"
target = "xilinx"
fetchto = "../../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "spec_mt_demo.xise"
top_module = "spec_top"
syn_tool = "ise"
modules = {
"local" : [
"../../../top/spec/mt_demo",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/urv-core.git",
"git://ohwr.org/hdl-core-lib/gn4124-core.git",
],
}
hdl/syn/spec/wr_node_demo/Manifest.py deleted 100644 → 0
View file @ f5dbdb5e
action = "synthesis"
target="xilinx"
fetchto = "../../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "spec_wr_node_demo.xise"
top_module = "spec_top"
syn_tool = "ise"
modules = { "local" : [ "../../../top/spec/wr_node_demo" ] }
hdl/syn/svec/mt_demo/.gitignore 0 → 100644
View file @ 973d755c
*
!.gitignore
!Manifest.py
hdl/syn/svec/mt_demo/Manifest.py 0 → 100644
View file @ 973d755c
action = "synthesis"
target = "xilinx"
fetchto = "../../../ip_cores"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "svec_top"
syn_project = "svec_mt_demo.xise"
top_module = "svec_top"
syn_tool = "ise"
modules = {
"local" : [
"../../../top/svec/mt_demo",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/urv-core.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git",
],
}
hdl/syn/svec/wr_node_demo/Manifest.py deleted 100644 → 0
View file @ f5dbdb5e
action = "synthesis"
target="xilinx"
fetchto = "../../../ip_cores"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "svec_top"
syn_project = "svec_wr_node_demo.xise"
top_module = "svec_top"
syn_tool = "ise"
modules = { "local" : [ "../../../top/svec/wr_node_demo" ] }
hdl/testbench/include/cpu_csr_driver.svh
View file @ 973d755c
`include "wrn_cpu_csr_regs.vh"
`include "mt_cpu_csr_regs.vh"
typedef class NodeCPUDbgQueue;
......@@ -13,7 +13,6 @@ class NodeCPUControl;
protected uint32_t core_count ,app_id;
// NodeCPUDbgQueue dbgq [$];
NodeCPUDbgQueue dbgq [$];
function new ( CBusAccessor bus_, input uint32_t base_);
......@@ -28,8 +27,6 @@ class NodeCPUControl;
task readl ( uint32_t r, ref uint32_t v );
uint64_t tmp;
bus.read (base + r, tmp );
//$display("Read %x : %x", base+r, tmp);
v= tmp;
endtask // readl
......@@ -37,8 +34,8 @@ class NodeCPUControl;
int i;
readl(`ADDR_WRN_CPU_CSR_APP_ID, app_id);
readl(`ADDR_WRN_CPU_CSR_CORE_COUNT, core_count);
readl(`ADDR_MT_CPU_CSR_APP_ID, app_id);
readl(`ADDR_MT_CPU_CSR_CORE_COUNT, core_count);
core_count&='hf;
......@@ -54,8 +51,8 @@ class NodeCPUControl;
for(i=0;i<core_count;i++)
begin
uint32_t memsize;
writel(`ADDR_WRN_CPU_CSR_CORE_SEL, i);
readl(`ADDR_WRN_CPU_CSR_CORE_MEMSIZE, memsize);
writel(`ADDR_MT_CPU_CSR_CORE_SEL, i);
readl(`ADDR_MT_CPU_CSR_CORE_MEMSIZE, memsize);
$display("Core %d: %d kB private memory", i, memsize/1024);
end
......@@ -67,25 +64,25 @@ class NodeCPUControl;
task reset_core(int core, int reset);
uint32_t rstr;
readl(`ADDR_WRN_CPU_CSR_RESET, rstr);
readl(`ADDR_MT_CPU_CSR_RESET, rstr);
if(reset)
rstr |= (1<<core);
else
rstr &= ~(1<<core);
writel(`ADDR_WRN_CPU_CSR_RESET, rstr);
writel(`ADDR_MT_CPU_CSR_RESET, rstr);
endtask // enable_cpu
task debug_int_enable(int core, int enable);
uint32_t imsk;
readl(`ADDR_WRN_CPU_CSR_DBG_IMSK, imsk);
readl(`ADDR_MT_CPU_CSR_DBG_IMSK, imsk);
if(enable)
imsk |= (1<<core);
else
imsk &= ~(1<<core);
writel(`ADDR_WRN_CPU_CSR_DBG_IMSK, imsk);
writel(`ADDR_MT_CPU_CSR_DBG_IMSK, imsk);
endtask // debug_int_enable
......@@ -97,7 +94,7 @@ class NodeCPUControl;
reset_core(core, 1);
writel(`ADDR_WRN_CPU_CSR_CORE_SEL, core);
writel(`ADDR_MT_CPU_CSR_CORE_SEL, core);
......@@ -109,28 +106,23 @@ class NodeCPUControl;
$fscanf(f,"%s %08x %08x", cmd,addr,data);
if(cmd == "write")
begin
writel(`ADDR_WRN_CPU_CSR_UADDR, addr);
writel(`ADDR_WRN_CPU_CSR_UDATA, data);
writel(`ADDR_MT_CPU_CSR_UADDR, addr);
writel(`ADDR_MT_CPU_CSR_UDATA, data);
q.push_back(data);
n++;
end
end
/* -----\/----- EXCLUDED -----\/-----
for(i=0;i<n;i++)
begin
uint32_t rv;
writel(`ADDR_WRN_CPU_CSR_UADDR, i);
readl(`ADDR_WRN_CPU_CSR_UDATA, rv);
$display("readback: addr %x d %x", i, rv);
writel(`ADDR_MT_CPU_CSR_UADDR, i);
readl(`ADDR_MT_CPU_CSR_UDATA, rv);
if(rv != q[i])
$display("verification error\n");
$display("verification error at %x, got %x, expected %x\n",
i, rv, q[i]);
end
-----/\----- EXCLUDED -----/\----- */
endtask
......@@ -149,7 +141,7 @@ class NodeCPUControl;
endtask // update
task set_smem_op(int op);
writel(`ADDR_WRN_CPU_CSR_SMEM_OP, op);
writel(`ADDR_MT_CPU_CSR_SMEM_OP, op);
endtask // set_smem_op
......@@ -176,12 +168,12 @@ class NodeCPUDbgQueue;
task update();
uint32_t rval;
cctl.readl(`ADDR_WRN_CPU_CSR_DBG_POLL , rval);
cctl.readl(`ADDR_MT_CPU_CSR_DBG_POLL , rval);
if(! (rval & (1<<core_id)))
return;
cctl.writel(`ADDR_WRN_CPU_CSR_CORE_SEL, core_id);
cctl.readl(`ADDR_WRN_CPU_CSR_DBG_MSG, rval);
cctl.writel(`ADDR_MT_CPU_CSR_CORE_SEL, core_id);
cctl.readl(`ADDR_MT_CPU_CSR_DBG_MSG, rval);
if(rval == 0)
......
hdl/testbench/include/mqueue_host.svh
View file @ 973d755c
......@@ -79,9 +79,9 @@ class MQueueHost;
endfunction // poll
function mqueue_message_t recv (int slot);
mqueue_message_t tmp = slots_in[slot][$];
slots_in[slot].pop_back();
return tmp;
mqueue_message_t ret = slots_in[slot][$];
mqueue_message_t tmp = slots_in[slot].pop_back();
return ret;
endfunction
task send (int slot, uint32_t data[$]);
......@@ -222,7 +222,8 @@ class MQueueHost;
task update();
uint32_t in_stat, irq_mask;
int i;
mqueue_message_t tmp;
if(!initialized)
init();
......@@ -248,7 +249,7 @@ class MQueueHost;
begin
if ( slots_out[i].size() )
begin
slots_out[i].pop_back();
tmp = slots_out[i].pop_back();
end
end
......
hdl/testbench/include/mt_cpu_csr_regs.vh 0 → 100644
View file @ 973d755c
`define ADDR_MT_CPU_CSR_APP_ID 6'h0
`define ADDR_MT_CPU_CSR_RESET 6'h4
`define ADDR_MT_CPU_CSR_ENABLE 6'h8
`define ADDR_MT_CPU_CSR_UADDR 6'hc
`define MT_CPU_CSR_UADDR_ADDR_OFFSET 0
`define MT_CPU_CSR_UADDR_ADDR 32'h000fffff
`define ADDR_MT_CPU_CSR_CORE_SEL 6'h10
`define ADDR_MT_CPU_CSR_CORE_COUNT 6'h14
`define ADDR_MT_CPU_CSR_CORE_MEMSIZE 6'h18
`define ADDR_MT_CPU_CSR_UDATA 6'h1c
`define ADDR_MT_CPU_CSR_DBG_JTAG 6'h20
`define MT_CPU_CSR_DBG_JTAG_JDATA_OFFSET 0
`define MT_CPU_CSR_DBG_JTAG_JDATA 32'h000000ff
`define MT_CPU_CSR_DBG_JTAG_JADDR_OFFSET 8
`define MT_CPU_CSR_DBG_JTAG_JADDR 32'h00000700
`define MT_CPU_CSR_DBG_JTAG_RSTN_OFFSET 16
`define MT_CPU_CSR_DBG_JTAG_RSTN 32'h00010000
`define MT_CPU_CSR_DBG_JTAG_TCK_OFFSET 17
`define MT_CPU_CSR_DBG_JTAG_TCK 32'h00020000
`define MT_CPU_CSR_DBG_JTAG_UPDATE_OFFSET 18
`define MT_CPU_CSR_DBG_JTAG_UPDATE 32'h00040000
`define ADDR_MT_CPU_CSR_DBG_MSG 6'h24
`define MT_CPU_CSR_DBG_MSG_DATA_OFFSET 0
`define MT_CPU_CSR_DBG_MSG_DATA 32'h000000ff
`define ADDR_MT_CPU_CSR_DBG_POLL 6'h28
`define MT_CPU_CSR_DBG_POLL_READY_OFFSET 0
`define MT_CPU_CSR_DBG_POLL_READY 32'h000000ff
`define ADDR_MT_CPU_CSR_DBG_IMSK 6'h2c
`define MT_CPU_CSR_DBG_IMSK_ENABLE_OFFSET 0
`define MT_CPU_CSR_DBG_IMSK_ENABLE 32'h000000ff
`define ADDR_MT_CPU_CSR_SMEM_OP 6'h30
hdl/testbench/include/wr_d3s_adc.vh deleted 100644 → 0
View file @ f5dbdb5e
`define ADDR_D3S_RSTR 7'h0
`define D3S_RSTR_PLL_RST_OFFSET 0
`define D3S_RSTR_PLL_RST 32'h00000001
`define ADDR_D3S_TCR 7'h4
`define D3S_TCR_WR_LOCK_EN_OFFSET 0
`define D3S_TCR_WR_LOCK_EN 32'h00000001
`define D3S_TCR_WR_LOCKED_OFFSET 1
`define D3S_TCR_WR_LOCKED 32'h00000002
`define D3S_TCR_WR_TIME_VALID_OFFSET 2
`define D3S_TCR_WR_TIME_VALID 32'h00000004
`define D3S_TCR_WR_LINK_OFFSET 3
`define D3S_TCR_WR_LINK 32'h00000008
`define ADDR_D3S_WR_FREQ 7'h8
`define D3S_WR_FREQ_METER_OFFSET 0
`define D3S_WR_FREQ_METER 32'hffffffff
`define ADDR_D3S_GPIOR 7'hc
`define D3S_GPIOR_SI57X_SCL_OFFSET 0
`define D3S_GPIOR_SI57X_SCL 32'h00000001
`define D3S_GPIOR_SI57X_SDA_OFFSET 1
`define D3S_GPIOR_SI57X_SDA 32'h00000002
`define D3S_GPIOR_SPI_CS_ADC_OFFSET 2
`define D3S_GPIOR_SPI_CS_ADC 32'h00000004
`define D3S_GPIOR_SPI_SCK_OFFSET 3
`define D3S_GPIOR_SPI_SCK 32'h00000008
`define D3S_GPIOR_SPI_MOSI_OFFSET 4
`define D3S_GPIOR_SPI_MOSI 32'h00000010
`define D3S_GPIOR_SPI_MISO_OFFSET 5
`define D3S_GPIOR_SPI_MISO 32'h00000020
`define D3S_GPIOR_SERDES_PLL_LOCKED_OFFSET 6
`define D3S_GPIOR_SERDES_PLL_LOCKED 32'h00000040
`define ADDR_D3S_SSR 7'h10
`define ADDR_D3S_CR 7'h14
`define D3S_CR_ENABLE_OFFSET 0
`define D3S_CR_ENABLE 32'h00000001
`define ADDR_D3S_RL_ERR_MIN 7'h18
`define ADDR_D3S_RL_ERR_MAX 7'h1c
`define ADDR_D3S_RL_LENGTH_MAX 7'h20
`define ADDR_D3S_TRANSIENT_THRESHOLD_PHASE 7'h24
`define ADDR_D3S_TRANSIENT_THRESHOLD_COUNT 7'h28
`define ADDR_D3S_CNT_FIXED 7'h2c
`define ADDR_D3S_CNT_TRANSIENT 7'h30
`define ADDR_D3S_CNT_RL 7'h34
`define ADDR_D3S_CNT_TSTAMP 7'h38
`define ADDR_D3S_ADC_R0 7'h3c
`define D3S_ADC_R0_PAYLOAD_OFFSET 0
`define D3S_ADC_R0_PAYLOAD 32'hffffffff
`define ADDR_D3S_ADC_CSR 7'h40
`define D3S_ADC_CSR_FULL_OFFSET 16
`define D3S_ADC_CSR_FULL 32'h00010000
`define D3S_ADC_CSR_EMPTY_OFFSET 17
`define D3S_ADC_CSR_EMPTY 32'h00020000
`define D3S_ADC_CSR_CLEAR_BUS_OFFSET 18
`define D3S_ADC_CSR_CLEAR_BUS 32'h00040000
`define D3S_ADC_CSR_USEDW_OFFSET 0
`define D3S_ADC_CSR_USEDW 32'h00003fff
hdl/testbench/include/wr_d3s_adc_slave.vh deleted 100644 → 0
View file @ f5dbdb5e
`define ADDR_D3SS_RSTR 6'h0
`define D3SS_RSTR_PLL_RST_OFFSET 0
`define D3SS_RSTR_PLL_RST 32'h00000001
`define ADDR_D3SS_TCR 6'h4
`define D3SS_TCR_WR_LOCK_EN_OFFSET 0
`define D3SS_TCR_WR_LOCK_EN 32'h00000001
`define D3SS_TCR_WR_LOCKED_OFFSET 1
`define D3SS_TCR_WR_LOCKED 32'h00000002
`define D3SS_TCR_WR_TIME_VALID_OFFSET 2
`define D3SS_TCR_WR_TIME_VALID 32'h00000004
`define D3SS_TCR_WR_LINK_OFFSET 3
`define D3SS_TCR_WR_LINK 32'h00000008
`define ADDR_D3SS_GPIOR 6'h8
`define D3SS_GPIOR_PLL_SYS_CS_N_OFFSET 0
`define D3SS_GPIOR_PLL_SYS_CS_N 32'h00000001
`define D3SS_GPIOR_PLL_SYS_RESET_N_OFFSET 1
`define D3SS_GPIOR_PLL_SYS_RESET_N 32'h00000002
`define D3SS_GPIOR_PLL_SCLK_OFFSET 2
`define D3SS_GPIOR_PLL_SCLK 32'h00000004
`define D3SS_GPIOR_PLL_SDIO_OFFSET 3
`define D3SS_GPIOR_PLL_SDIO 32'h00000008
`define D3SS_GPIOR_PLL_SDIO_DIR_OFFSET 4
`define D3SS_GPIOR_PLL_SDIO_DIR 32'h00000010
`define D3SS_GPIOR_PLL_VCXO_RESET_N_OFFSET 5
`define D3SS_GPIOR_PLL_VCXO_RESET_N 32'h00000020
`define D3SS_GPIOR_PLL_VCXO_CS_N_OFFSET 6
`define D3SS_GPIOR_PLL_VCXO_CS_N 32'h00000040
`define D3SS_GPIOR_PLL_VCXO_SDO_OFFSET 7
`define D3SS_GPIOR_PLL_VCXO_SDO 32'h00000080
`define D3SS_GPIOR_ADF_CE_OFFSET 8
`define D3SS_GPIOR_ADF_CE 32'h00000100
`define D3SS_GPIOR_ADF_CLK_OFFSET 9
`define D3SS_GPIOR_ADF_CLK 32'h00000200
`define D3SS_GPIOR_ADF_LE_OFFSET 10
`define D3SS_GPIOR_ADF_LE 32'h00000400
`define D3SS_GPIOR_ADF_DATA_OFFSET 11
`define D3SS_GPIOR_ADF_DATA 32'h00000800
`define D3SS_GPIOR_SERDES_PLL_LOCKED_OFFSET 12
`define D3SS_GPIOR_SERDES_PLL_LOCKED 32'h00001000
`define ADDR_D3SS_CR 6'hc
`define D3SS_CR_ENABLE_OFFSET 0
`define D3SS_CR_ENABLE 32'h00000001
`define ADDR_D3SS_REC_DELAY_COARSE 6'h10
`define ADDR_D3SS_FREV_TS_SEC 6'h14
`define ADDR_D3SS_FREV_TS_NS 6'h18
`define ADDR_D3SS_FREV_CR 6'h1c
`define D3SS_FREV_CR_VALID_OFFSET 0
`define D3SS_FREV_CR_VALID 32'h00000001
`define D3SS_FREV_CR_READY_OFFSET 1
`define D3SS_FREV_CR_READY 32'h00000002
`define ADDR_D3SS_PHFIFO_R0 6'h20
`define D3SS_PHFIFO_R0_PAYLOAD_OFFSET 0
`define D3SS_PHFIFO_R0_PAYLOAD 32'hffffffff
`define ADDR_D3SS_PHFIFO_CSR 6'h24
`define D3SS_PHFIFO_CSR_FULL_OFFSET 16
`define D3SS_PHFIFO_CSR_FULL 32'h00010000
`define D3SS_PHFIFO_CSR_EMPTY_OFFSET 17
`define D3SS_PHFIFO_CSR_EMPTY 32'h00020000
`define D3SS_PHFIFO_CSR_CLEAR_BUS_OFFSET 18
`define D3SS_PHFIFO_CSR_CLEAR_BUS 32'h00040000
`define D3SS_PHFIFO_CSR_USEDW_OFFSET 0
`define D3SS_PHFIFO_CSR_USEDW 32'h00003fff
hdl/testbench/include/wrn_cpu_csr_regs.vh deleted 100644 → 0
View file @ f5dbdb5e
`define ADDR_WRN_CPU_CSR_APP_ID 6'h0
`define ADDR_WRN_CPU_CSR_RESET 6'h4
`define ADDR_WRN_CPU_CSR_ENABLE 6'h8
`define ADDR_WRN_CPU_CSR_UADDR 6'hc
`define WRN_CPU_CSR_UADDR_ADDR_OFFSET 0
`define WRN_CPU_CSR_UADDR_ADDR 32'h000fffff
`define ADDR_WRN_CPU_CSR_CORE_SEL 6'h10
`define ADDR_WRN_CPU_CSR_CORE_COUNT 6'h14
`define ADDR_WRN_CPU_CSR_CORE_MEMSIZE 6'h18
`define ADDR_WRN_CPU_CSR_UDATA 6'h1c
`define ADDR_WRN_CPU_CSR_DBG_JTAG 6'h20
`define WRN_CPU_CSR_DBG_JTAG_JDATA_OFFSET 0
`define WRN_CPU_CSR_DBG_JTAG_JDATA 32'h000000ff
`define WRN_CPU_CSR_DBG_JTAG_JADDR_OFFSET 8
`define WRN_CPU_CSR_DBG_JTAG_JADDR 32'h00000700
`define WRN_CPU_CSR_DBG_JTAG_RSTN_OFFSET 16
`define WRN_CPU_CSR_DBG_JTAG_RSTN 32'h00010000
`define WRN_CPU_CSR_DBG_JTAG_TCK_OFFSET 17
`define WRN_CPU_CSR_DBG_JTAG_TCK 32'h00020000
`define WRN_CPU_CSR_DBG_JTAG_UPDATE_OFFSET 18
`define WRN_CPU_CSR_DBG_JTAG_UPDATE 32'h00040000
`define ADDR_WRN_CPU_CSR_DBG_MSG 6'h24
`define WRN_CPU_CSR_DBG_MSG_DATA_OFFSET 0
`define WRN_CPU_CSR_DBG_MSG_DATA 32'h000000ff
`define ADDR_WRN_CPU_CSR_DBG_POLL 6'h28
`define WRN_CPU_CSR_DBG_POLL_READY_OFFSET 0
`define WRN_CPU_CSR_DBG_POLL_READY 32'h000000ff
`define ADDR_WRN_CPU_CSR_DBG_IMSK 6'h2c
`define WRN_CPU_CSR_DBG_IMSK_ENABLE_OFFSET 0
`define WRN_CPU_CSR_DBG_IMSK_ENABLE 32'h000000ff
`define ADDR_WRN_CPU_CSR_SMEM_OP 6'h30
hdl/testbench/sw/hw-tests/common/genraminit.c 0 → 100644
View file @ 973d755c
/*
* This work is part of the White Rabbit project
*
* Copyright (C) 2011 CERN (www.cern.ch)
* Author: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
*
* Released according to the GNU GPL, version 2 or any later version.
*/
#include <stdio.h>
#include <stdlib.h>
int main(int argc, char *argv[])
{
if (argc < 2)
return -1;
FILE *f = fopen(argv[1], "rb");
if (!f)
return -1;
unsigned char x[4];
int i = 0;
fseek(f, 0, SEEK_END);
int n = (ftell(f) + 3) / 4;
rewind(f);
printf("Argc: %d\n", argc);
if(argc > 2)
n = atoi(argv[2]);
while (!feof(f)) {
fread(x, 1, 4, f);
printf("write %x %02X%02X%02X%02X\n", i++, x[0], x[1], x[2],
x[3]);
}
for (; i < n;) {
printf("write %x %02X%02X%02X%02X\n", i++, 0, 0, 0, 0);
}
fclose(f);
return 0;
}
software/rt/hw-tests/common/lm32/wrnode.mk → hdl/testbench/sw/hw-tests/common/lm32/mt.mk
View file @ 973d755c
......@@ -8,11 +8,11 @@ OBJCOPY = $(CROSS_COMPILE)objcopy
SIZE = $(CROSS_COMPILE)size
CFLAGS = -DWRNODE_RT -g -O3 -I. -I../common -I../../include -I../include/ -mmultiply-enabled -mbarrel-shift-enabled -ffunction-sections -fdata-sections -Wl,--gc-sections
OBJS += ../common/lm32/wrn-crt0.o ../common/rt-common.o ../common/printf.o ../common/vsprintf-xint.o
LDSCRIPT = ../common/lm32/wrnode.ld
OBJS += ../common/lm32/crt0.o ../common/rt-common.o ../common/printf.o ../common/vsprintf-xint.o
LDSCRIPT = ../common/lm32/mt.ld
LDFLAGS= -ffunction-sections -fdata-sections -Wl,--gc-sections
$(OUTPUT): $(LDSCRIPT) $(OBJS)
$(OUTPUT): $(LDSCRIPT) $(OBJS) ../common/genraminit
${CC} -o $(OUTPUT).elf -nostartfiles $(OBJS) -T $(LDSCRIPT) -lgcc -lc $(LDFLAGS)
${OBJCOPY} --remove-section .smem -O binary $(OUTPUT).elf $(OUTPUT).bin
${OBJDUMP} -S $(OUTPUT).elf > disasm.S
......@@ -21,6 +21,6 @@ $(OUTPUT): $(LDSCRIPT) $(OBJS)
clean:
rm -f $(OBJS) $(OUTPUT).bin
install:
cp $(OUTPUT).bin /acc/local/share/firmware/list
\ No newline at end of file
cp $(OUTPUT).bin /acc/local/share/firmware/list
software/rt/hw-tests/common/urv/irq.S → hdl/testbench/sw/hw-tests/common/urv/irq.S
View file @ 973d755c
......@@ -113,7 +113,7 @@ jump_table_return:
lw t5,120(a0)
lw t6,124(a0)
lw a0,40(a0)
eret
mret
.weak undefined_handler
undefined_handler:
......
software/rt/hw-tests/common/urv/mt.mk → hdl/testbench/sw/hw-tests/common/urv/mt.mk
View file @ 973d755c
......@@ -7,25 +7,25 @@ OBJDUMP = $(CROSS_COMPILE)objdump
OBJCOPY = $(CROSS_COMPILE)objcopy
SIZE = $(CROSS_COMPILE)size
CFLAGS = -DWRNODE_RT -g -O2 -m32 -I. -I../common -I../../include -I../include/ -march=RV32IM
CFLAGS = -DWRNODE_RT -g -O2 -I. -I../common -I../../include -I../include/ -march=rv32im -mabi=ilp32
OBJS += ../common/urv/crt0.o ../common/urv/irq.o ../common/urv/emulate.o ../common/rt-common.o ../common/printf.o ../common/vsprintf-xint.o
LDSCRIPT = ../common/urv/mt.ld
$(OUTPUT): $(LDSCRIPT) $(OBJS)
${CC} -m32 -flto -g -o $(OUTPUT).elf -nostartfiles $(OBJS) -T $(LDSCRIPT) -lgcc -lc
${CC} $(CFLAGS) -o $(OUTPUT).elf -nostartfiles $(OBJS) -T $(LDSCRIPT) -lgcc -lc
${OBJCOPY} --remove-section .smem -O binary $(OUTPUT).elf $(OUTPUT).bin
${OBJDUMP} -S $(OUTPUT).elf > disasm.S
../common/genraminit $(OUTPUT).bin > $(OUTPUT).ram
$(SIZE) $(OUTPUT).elf
../common/urv/emulate.o: ../common/urv/emulate.c
${CC} -O2 -m32 -march=RV32I -m32 -c $^ -o $@ -I.
${CC} $(CFLAGS) -march=rv32i -c $^ -o $@ -I.
%.o: %.S
${CC} -march=RV32I -m32 -c $^ -o $@
${CC} $(CFLAGS) -c $^ -o $@
clean:
rm -f $(OBJS) $(OUTPUT).bin
install:
cp $(OUTPUT).bin /acc/local/share/firmware/list
\ No newline at end of file
cp $(OUTPUT).bin /acc/local/share/firmware/list
software/rt/hw-tests/hello/Makefile → hdl/testbench/sw/hw-tests/hello/Makefile
View file @ 973d755c
CPU=urv
CPU ?= urv
OBJS = hello.o
OUTPUT = hello
include ../common/$(CPU)/mt.mk
hdl/testbench/sw/hw-tests/hello/hello.ram.lm32 0 → 100755
View file @ 973d755c
Argc: 2
write 0 98000000
write 1 D0000000
write 2 D0200000
write 3 78010000
write 4 38210000
write 5 D0E10000
write 6 F800003A
write 7 34000000
write 8 00000000
write 9 00000000
write a 00000000
write b 00000000
write c 00000000
write d 00000000
write e 00000000
write f 00000000
write 10 00000000
write 11 00000000
write 12 00000000
write 13 00000000
write 14 00000000
write 15 00000000
write 16 00000000
write 17 00000000
write 18 00000000
write 19 00000000
write 1a 00000000
write 1b 00000000
write 1c 00000000
write 1d 00000000
write 1e 00000000
write 1f 00000000
write 20 34010004
write 21 E0000009
write 22 00000000
write 23 00000000
write 24 00000000
write 25 00000000
write 26 00000000
write 27 00000000
write 28 34010005
write 29 E0000001
write 2a E0000000
write 2b 00000000
write 2c 00000000
write 2d 00000000
write 2e 00000000
write 2f 00000000
write 30 34000000
write 31 00000000
write 32 00000000
write 33 00000000
write 34 00000000
write 35 00000000
write 36 00000000
write 37 00000000
write 38 00000000
write 39 00000000
write 3a 00000000
write 3b 00000000
write 3c 00000000
write 3d 00000000
write 3e 00000000
write 3f 00000000
write 40 98000000
write 41 98210800
write 42 98421000
write 43 98631800
write 44 781C0000
write 45 3B9C7FFC
write 46 781A0000
write 47 3B5A8860
write 48 78010000
write 49 38210864
write 4a 34020000
write 4b 78030000
write 4c 386308E4
write 4d C8611800
write 4e 34010000
write 4f 34020000
write 50 34030000
write 51 F8000002
write 52 E0000000
write 53 379CFFFC
write 54 5B9D0004
write 55 78010000
write 56 38210658
write 57 F8000016
write 58 34010000
write 59 2B9D0004
write 5a 379C0004
write 5b C3A00000
write 5c 40220000
write 5d B8201800
write 5e 34010000
write 5f 44400009
write 60 78050000
write 61 38A50668
write 62 28A40000
write 63 34210001
write 64 58820000
write 65 B4611000
write 66 40420000
write 67 5C40FFFC
write 68 78030000
write 69 38630668
write 6a 28620000
write 6b 58400000
write 6c C3A00000
write 6d 379CFFD4
write 6e 5B8B000C
write 6f 5B8C0008
write 70 5B9D0004
write 71 780B0000
write 72 396B0864
write 73 5B810010
write 74 5B820014
write 75 5B830018
write 76 B8201000
write 77 37830014
write 78 B9600800
write 79 5B84001C
write 7a 5B850020
write 7b 5B860024
write 7c 5B870028
write 7d 5B88002C
write 7e F800000A
write 7f B8206000
write 80 B9600800
write 81 FBFFFFDB
write 82 B9800800
write 83 2B9D0004
write 84 2B8B000C
write 85 2B8C0008
write 86 379C002C
write 87 C3A00000
write 88 379CFFA8
write 89 5B8B0044
write 8a 5B8C0040
write 8b 5B8D003C
write 8c 5B8E0038
write 8d 5B8F0034
write 8e 5B900030
write 8f 5B91002C
write 90 5B920028
write 91 5B930024
write 92 5B940020
write 93 5B95001C
write 94 5B960018
write 95 5B970014
write 96 5B980010
write 97 5B99000C
write 98 5B9B0008
write 99 5B9D0004
write 9a B8407000
write 9b 40420000
write 9c B820C000
write 9d B8206800
write 9e B8609800
write 9f 34010000
write a0 4440001B
write a1 78160000
write a2 78110000
write a3 34140025
write a4 3AD60680
write a5 34190078
write a6 3412000F
write a7 378F004C
write a8 3A31066C
write a9 E0000006
write aa 31A20000
write ab 35AD0001
write ac 35CE0001
write ad 41C20000
write ae 4440000C
write af 341B0001
write b0 34150020
write b1 3410000A
write b2 5C54FFF8
write b3 35CE0001
write b4 41C20000
write b5 54590099
write b6 3C410002
write b7 B6C10800
write b8 28210000
write b9 C0200000
write ba C9B80800
write bb 31A00000
write bc 2B9D0004
write bd 2B8B0044
write be 2B8C0040
write bf 2B8D003C
write c0 2B8E0038
write c1 2B8F0034
write c2 2B900030
write c3 2B91002C
write c4 2B920028
write c5 2B930024
write c6 2B940020
write c7 2B95001C
write c8 2B960018
write c9 2B970014
write ca 2B980010
write cb 2B99000C
write cc 2B9B0008
write cd 379C0058
write ce C3A00000
write cf 2A6C0000
write d0 6601000A
write d1 5B800048
write d2 0182001F
write d3 36730004
write d4 A0410800
write d5 34170000
write d6 44200006
write d7 66A30020
write d8 C80C6000
write d9 5B830048
write da 3410000A
write db 34170001
write dc 45800078
write dd 340B0010
write de B9800800
write df BA001000
write e0 F800008A
write e1 B6210800
write e2 40240000
write e3 356BFFFF
write e4 B5EB1000
write e5 30440000
write e6 B9800800
write e7 BA001000
write e8 F8000072
write e9 7D640000
write ea 7C220000
write eb B8206000
write ec A0821000
write ed 5C40FFF1
write ee 2B820048
write ef 44400006
write f0 356BFFFF
write f1 B5EB0800
write f2 3403002D
write f3 30230000
write f4 34170000
write f5 34010010
write f6 C83B2000
write f7 B4972000
write f8 4C8B0006
write f9 22A300FF
write fa 356BFFFF
write fb B5EB1000
write fc 30430000
write fd 5D64FFFD
write fe 46E00005
write ff 356BFFFF
write 100 B5EB0800
write 101 3402002D
write 102 30220000
write 103 34030010
write 104 C86B0800
write 105 49720020
write 106 A5604800
write 107 35290011
write 108 B5EB3800
write 109 01280002
write 10a B8ED2800
write 10b 20A50003
write 10c 3D030002
write 10d 64A50000
write 10e 75220003
write 10f 64640000
write 110 A0A21000
write 111 18420001
write 112 B8821000
write 113 5C400045
write 114 34040000
write 115 B4E42800
write 116 28A60000
write 117 B5A42800
write 118 34420001
write 119 58A60000
write 11a 34840004
write 11b 5502FFFA
write 11c B5635800
write 11d B5A31000
write 11e 44690007
write 11f B5EB2000
write 120 40830000
write 121 356B0001
write 122 30430000
write 123 34420001
write 124 4E4BFFFB
write 125 B5A16800
write 126 E3FFFF86
write 127 2A630000
write 128 36730004
write 129 40620000
write 12a 4440FF82
write 12b 31A20000
write 12c 34630001
write 12d 40620000
write 12e 35AD0001
write 12f 5C40FFFC
write 130 E3FFFF7C
write 131 3402000A
write 132 BA600800
write 133 5E02FF9C
write 134 282C0000
write 135 36730004
write 136 5B800048
write 137 34100008
write 138 34170000
write 139 E3FFFFA3
write 13a 2A610000
write 13b 36730004
write 13c 31A10000
write 13d 35AD0001
write 13e E3FFFF6E
write 13f 2A6C0000
write 140 34100010
write 141 5B800048
write 142 36730004
write 143 34170000
write 144 E3FFFF98
write 145 34150030
write 146 E3FFFF6D
write 147 2A700000
write 148 36730004
write 149 E3FFFF6A
write 14a 34010025
write 14b 31A10000
write 14c 35AD0001
write 14d E3FFFF5F
write 14e 3441FFCF
write 14f 202100FF
write 150 34030008
write 151 5423FF62
write 152 345BFFD0
write 153 E3FFFF60
write 154 34010030
write 155 3381005B
write 156 340B000F
write 157 E3FFFF97
write 158 B9A01000
write 159 E3FFFFC6
write 15a 379CFFFC
write 15b 5B9D0004
write 15c 44400006
write 15d 34030000
write 15e F800001C
write 15f 2B9D0004
write 160 379C0004
write 161 C3A00000
write 162 90000800
write 163 20210001
write 164 B4210800
write 165 D0010000
write 166 90E00800
write 167 BBA0F000
write 168 342100A0
write 169 C0200000
write 16a 379CFFFC
write 16b 5B9D0004
write 16c 44400006
write 16d 34030001
write 16e F800000C
write 16f 2B9D0004
write 170 379C0004
write 171 C3A00000
write 172 90000800
write 173 20210001
write 174 B4210800
write 175 D0010000
write 176 90E00800
write 177 BBA0F000
write 178 342100A0
write 179 C0200000
write 17a F4222000
write 17b 44800018
write 17c 34040001
write 17d 4C40000B
write 17e 34050000
write 17f 54410003
write 180 C8220800
write 181 B8A42800
write 182 00840001
write 183 00420001
write 184 5C80FFFB
write 185 5C600002
write 186 B8A00800
write 187 C3A00000
write 188 B4421000
write 189 B4842000
write 18a 7C860000
write 18b F4222800
write 18c A0C52800
write 18d 44A00002
write 18e 4C40FFFA
write 18f 34050000
write 190 4480FFF5
write 191 34050000
write 192 E3FFFFED
write 193 34040001
write 194 34050000
write 195 E3FFFFEA
write 196 48656C6C
write 197 6F2C2077
write 198 6F726C64
write 199 210A0000
write 19a 0010001C
write 19b 30313233
write 19c 34353637
write 19d 38396162
write 19e 63646566
write 19f 00000000
write 1a0 000002E8
write 1a1 00000538
write 1a2 00000538
write 1a3 00000538
write 1a4 00000538
write 1a5 00000538
write 1a6 00000538
write 1a7 00000538
write 1a8 00000538
write 1a9 00000538
write 1aa 00000538
write 1ab 00000538
write 1ac 00000538
write 1ad 00000538
write 1ae 00000538
write 1af 00000538
write 1b0 00000538
write 1b1 00000538
write 1b2 00000538
write 1b3 00000538
write 1b4 00000538
write 1b5 00000538
write 1b6 00000538
write 1b7 00000538
write 1b8 00000538
write 1b9 00000538
write 1ba 00000538
write 1bb 00000538
write 1bc 00000538
write 1bd 00000538
write 1be 00000538
write 1bf 00000538
write 1c0 00000538
write 1c1 00000538
write 1c2 00000538
write 1c3 00000538
write 1c4 00000538
write 1c5 00000528
write 1c6 00000538
write 1c7 00000538
write 1c8 00000538
write 1c9 00000538
write 1ca 0000051C
write 1cb 00000538
write 1cc 00000538
write 1cd 00000538
write 1ce 00000538
write 1cf 00000538
write 1d0 00000514
write 1d1 00000538
write 1d2 00000538
write 1d3 00000538
write 1d4 00000538
write 1d5 00000538
write 1d6 00000538
write 1d7 00000538
write 1d8 00000538
write 1d9 00000538
write 1da 00000538
write 1db 00000538
write 1dc 00000538
write 1dd 00000538
write 1de 00000538
write 1df 00000538
write 1e0 00000538
write 1e1 00000538
write 1e2 00000538
write 1e3 00000538
write 1e4 00000538
write 1e5 00000538
write 1e6 00000538
write 1e7 00000538
write 1e8 00000538
write 1e9 00000538
write 1ea 00000538
write 1eb 00000538
write 1ec 00000538
write 1ed 00000538
write 1ee 00000538
write 1ef 00000538
write 1f0 00000538
write 1f1 00000538
write 1f2 00000538
write 1f3 00000538
write 1f4 00000538
write 1f5 00000538
write 1f6 00000538
write 1f7 00000538
write 1f8 000004FC
write 1f9 00000538
write 1fa 00000538
write 1fb 00000538
write 1fc 00000538
write 1fd 00000538
write 1fe 00000538
write 1ff 00000538
write 200 00000538
write 201 00000538
write 202 00000538
write 203 000004E8
write 204 0000033C
write 205 00000538
write 206 00000538
write 207 00000538
write 208 00000538
write 209 0000033C
write 20a 00000538
write 20b 00000538
write 20c 00000538
write 20d 00000538
write 20e 000002B0
write 20f 000004C4
write 210 000004FC
write 211 00000538
write 212 00000538
write 213 0000049C
write 214 00000538
write 215 0000033C
write 216 00000538
write 217 00000538
write 218 000004FC
write 219 000004FC
hdl/testbench/sw/hw-tests/hello/hello.ram.urv 0 → 100755
View file @ 973d755c
Argc: 2
write 0 6F00C000
write 1 00000000
write 2 6F004004
write 3 97110000
write 4 93814132
write 5 17810000
write 6 130181BE
write 7 97820000
write 8 938202FE
write 9 F3920234
write a 97120000
write b 938282B0
write c 17130000
write d 130303B8
write e 23A00200
write f 93824200
write 10 E3EC62FE
write 11 371E0000
write 12 EF00D00B
write 13 73110134
write 14 130101EC
write 15 23221100
write 16 23263100
write 17 23284100
write 18 232A5100
write 19 232C6100
write 1a 232E7100
write 1b 23208102
write 1c 23229102
write 1d 2324A102
write 1e 2326B102
write 1f 2328C102
write 20 232AD102
write 21 232CE102
write 22 232EF102
write 23 23200105
write 24 23221105
write 25 23242105
write 26 23263105
write 27 23284105
write 28 232A5105
write 29 232C6105
write 2a 232E7105
write 2b 23208107
write 2c 23229107
write 2d 2324A107
write 2e 2326B107
write 2f 2328C107
write 30 232AD107
write 31 232CE107
write 32 232EF107
write 33 F3220034
write 34 73240030
write 35 73231034
write 36 F3233034
write 37 732E2034
write 38 23245100
write 39 23208108
write 3a 23226108
write 3b 23247108
write 3c 2326C109
write 3d 9302F0FF
write 3e 23285108
write 3f 13050100
write 40 97020000
write 41 93820202
write 42 131E2E00
write 43 B382C201
write 44 83A20200
write 45 97000000
write 46 9380C004
write 47 67800200
write 48 F8010000
write 49 F8010000
write 4a 00020000
write 4b F8010000
write 4c F8010000
write 4d F8010000
write 4e F8010000
write 4f F8010000
write 50 F8010000
write 51 F8010000
write 52 F8010000
write 53 F8010000
write 54 F8010000
write 55 F8010000
write 56 F8010000
write 57 F8010000
write 58 13050100
write 59 03230508
write 5a 83234508
write 5b 13010114
write 5c 73100134
write 5d 73901334
write 5e 83204500
write 5f 03218500
write 60 8321C500
write 61 03220501
write 62 83224501
write 63 03238501
write 64 8323C501
write 65 03240502
write 66 83244502
write 67 8325C502
write 68 03260503
write 69 83264503
write 6a 03278503
write 6b 8327C503
write 6c 03280504
write 6d 83284504
write 6e 03298504
write 6f 8329C504
write 70 032A0505
write 71 832A4505
write 72 032B8505
write 73 832BC505
write 74 032C0506
write 75 832C4506
write 76 032D8506
write 77 832DC506
write 78 032E0507
write 79 832E4507
write 7a 032F8507
write 7b 832FC507
write 7c 03258502
write 7d 73002030
write 7e 6F000000
write 7f 6F004000
write 80 130101FF
write 81 23202101
write 82 03294508
write 83 B77500FE
write 84 23229100
write 85 83270900
write 86 23261100
write 87 23248100
write 88 13D6D700
write 89 93D62701
write 8a 1376C607
write 8b 93F6C607
write 8c 9385F507
write 8d 37180002
write 8e 23200500
write 8f 3306C500
write 90 B306D500
write 91 13D77700
write 92 13083803
write 93 B3F7B700
write 94 93040500
write 95 1377F701
write 96 03250600
write 97 03A60600
write 98 6380070B
write 99 B7260002
write 9a 93863603
write 9b 638CD704
write 9c B7360002
write 9d 93863603
write 9e 638ED70A
write 9f B7460002
write a0 93863603
write a1 6386D70C
write a2 B7560002
write a3 93863603
write a4 6386D708
write a5 B7660002
write a6 93863603
write a7 6386D70C
write a8 B7760002
write a9 93863603
write aa 639AD702
write ab 13172700
write ac 93050600
write ad 3384E400
write ae EF00405C
write af 2320A400
write b0 6F00C001
write b1 13172700
write b2 93060000
write b3 9355F541
write b4 3384E400
write b5 EF00004D
write b6 2320B400
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write 2c0 C0050000
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write 2c3 30313233
write 2c4 34353637
write 2c5 38396162
write 2c6 63646566
write 2c7 00000000
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hdl/testbench/top/.gitignore 0 → 100644
View file @ 973d755c
work/
Makefile
modelsim.ini
transcript
*.wlf
hdl/testbench/top/Manifest.py
View file @ 973d755c
......@@ -8,12 +8,13 @@ sim_top = "main"
action = "simulation"
target = "xilinx"
syn_device = "xc6slx150t"
vcom_opt = "-mixedsvvh"
vcom_opt = "-93 -mixedsvvh"
include_dirs = [
"../include",
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/",
"../../ip_cores/general-cores/sim/",
"../../ip_cores/urv-core/rtl/",
]
files = [
......@@ -23,8 +24,12 @@ files = [
modules = {
"local" : [
"../../rtl",
"../../ip_cores/etherbone-core",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/wr-cores.git",
"git://ohwr.org/hdl-core-lib/urv-core.git",
],
}
fetchto = "../../ip_cores"
hdl/testbench/top/main.sv
View file @ 973d755c
import wishbone_pkg::*;
import wr_node_pkg::*;
`include "vhd_wishbone_master.svh"
`include "cpu_csr_driver.svh"
`include "mqueue_host.svh"
class CWRNode;
function new ( CBusAccessor acc_, input uint32_t base_);
endfunction // new
endclass // CWRNode
`timescale 1ns/1ps
module main;
......@@ -24,132 +15,67 @@ module main;
always #4ns clk_cpu <= ~clk_cpu;
always@(posedge clk_cpu)
clk_sys <= ~clk_sys;
initial begin
repeat(20) @(posedge clk_sys);
rst_n = 1;
end
wire host_irq;
wire host_irq;
IVHDWishboneMaster Host ( clk_sys, rst_n );
wr_node_core # (
.g_double_core_clock(1'b0)
)DUT (
.clk_i (clk_sys),
.clk_cpu_i(clk_cpu),
.rst_n_i (rst_n),
.host_slave_i (Host.master.out),
.host_slave_o (Host.master.in),
.host_irq_o(host_irq)
);
mock_turtle_core #
(
.g_double_core_clock(1'b0),
//.g_cpu_arch("LM32")
.g_cpu_arch("URV")
)
DUT (
.clk_i (clk_sys),
.clk_cpu_i(clk_cpu),
.rst_n_i (rst_n),
.host_slave_i (Host.master.out),
.host_slave_o (Host.master.in),
.host_irq_o(host_irq)
);
initial begin
NodeCPUControl cpu_csr;
MQueueHost hmq;
uint64_t rv;
CBusAccessor host_acc;
#10us;
host_acc = Host.get_accessor();
cpu_csr = new ( Host.get_accessor(), 'hc000 );
hmq = new ( Host.get_accessor(), 0 );
// enable all IRQs
host_acc.write(`MQUEUE_GCR_IRQ_MASK, 'hffff);
cpu_csr.init();
cpu_csr.load_firmware (0, "../../sw/debug-test/debug-test.ram");
//cpu_csr.load_firmware (0, "../sw/hw-tests/hello/hello.ram.lm32");
cpu_csr.load_firmware (0, "../sw/hw-tests/hello/hello.ram.urv");
cpu_csr.reset_core(0, 0);
/* -----\/----- EXCLUDED -----\/-----
cpu_csr.load_firmware (1, "../../sw/debug-test/debug-test.ram");
cpu_csr.reset_core(1, 0);
-----/\----- EXCLUDED -----/\----- */
$display("CPU0 started\n");
/* -----\/----- EXCLUDED -----\/-----
forever begin
cpu_csr.update();
@(posedge clk_sys);
end
-----/\----- EXCLUDED -----/\----- */
/* -----\/----- EXCLUDED -----\/-----
host_acc.read('h08, rv);
$display("GCR_IRQ_MASK %x", rv);
host_acc.read('h04, rv);
$display("GCR_STATUS %x", rv);
hmq.send(0, '{1,2,3} );
#20us;
$display("GCR_STATUS %x", rv);
forever begin
hmq.update();
#1us;
end
-----/\----- EXCLUDED -----/\----- */
/* -----\/----- EXCLUDED -----\/-----
cpu_csr.set_smem_op(`SMEM_OP_DIRECT);
host_acc.write('h10000, 'hcafebabe);
host_acc.write('h10004, 'hdeadbeef);
host_acc.read('h10000, rv);
$display("smem-read: %x", rv);
host_acc.read('h10004, rv);
$display("smem-read: %x", rv);
cpu_csr.set_smem_op(`SMEM_OP_ADD);
$display("Atomic add...\n");
host_acc.write('h10000, 'h1);
host_acc.write('h10004, 'h2);
host_acc.read('h10000, rv);
$display("smem-read: %x", rv);
host_acc.read('h10004, rv);
$display("smem-read: %x", rv);
-----/\----- EXCLUDED -----/\----- */
$error("Loop");
forever begin
cpu_csr.update();
while(host_irq)
hmq.update();
#1us;
hmq.update();
#1us;
@(posedge clk_sys);
end
end // initial begin
endmodule
hdl/testbench/top/run.do
View file @ 973d755c
......@@ -5,4 +5,4 @@ set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 200us
\ No newline at end of file
run 1000us
\ No newline at end of file
hdl/top/spec/mt_demo/Manifest.py
View file @ 973d755c
files = [ "synthesis_descriptor.vhd", "spec_top.vhd", "spec_top.ucf" ]
fetchto = "../../ip_cores"
files = [
"synthesis_descriptor.vhd",
"spec_top.vhd",
"spec_top.ucf",
]
modules = {
"local" : [ "../../../rtl",
"../mt_template",
"../../../ip_cores/gn4124-core" ],
}
"local" : [
"../mt_template",
],
}
hdl/top/spec/mt_demo/spec_top.ucf
View file @ 973d755c
......@@ -222,7 +222,7 @@ net "leds_n_o[3]" IOSTANDARD=LVCMOS18;
# GN4124
NET "l_rst_n" TIG;
NET "U_Node_Template/gen_with_gennum.U_GN4124_Core/rst_*" TIG;
NET "U_MT_Template/gen_with_gennum.U_GN4124_Core/rst_*" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20
#INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
#INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
......@@ -232,7 +232,7 @@ NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_Node_Template/U_GN4124_Core/cmp_clk_in/P_clk;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_P_clk = PERIOD "U_Node_Template/U_GN4124_Core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "U_Node_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback;
TIMESPEC TS_U_Node_Template_U_GN4124_Core_cmp_clk_in_feedback = PERIOD "U_Node_Template/U_GN4124_Core/cmp_clk_in/feedback" 5 ns HIGH 50%;
NET "U_MT_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/P_clk" TNM_NET = U_MT_Template/U_GN4124_Core/cmp_clk_in/P_clk;
TIMESPEC TS_U_MT_Template_U_GN4124_Core_cmp_clk_in_P_clk = PERIOD "U_MT_Template/U_GN4124_Core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
NET "U_MT_Template/gen_with_gennum.U_GN4124_Core/cmp_clk_in/feedback" TNM_NET = U_MT_Template/U_GN4124_Core/cmp_clk_in/feedback;
TIMESPEC TS_U_MT_Template_U_GN4124_Core_cmp_clk_in_feedback = PERIOD "U_MT_Template/U_GN4124_Core/cmp_clk_in/feedback" 5 ns HIGH 50%;
hdl/top/spec/mt_template/Manifest.py
View file @ 973d755c
files = [ "spec_mt_pkg.vhd",
"spec_mt_template.vhd",
"spec_reset_gen.vhd" ];
files = [
"spec_mt_pkg.vhd",
"spec_mt_template.vhd",
"spec_reset_gen.vhd"
]
modules = { "local" : [ "../../../rtl" ] };
modules = {
"local" : [
"../../../rtl",
],
}
hdl/top/svec/mt_demo/Manifest.py
View file @ 973d755c
files = [ "synthesis_descriptor.vhd", "svec_top.vhd", "svec_top.ucf" ]
fetchto = "../../ip_cores"
files = [
"synthesis_descriptor.vhd",
"svec_top.vhd",
"svec_top.ucf",
]
modules = {
"local" : [ "../../../rtl",
"../mt_template",
"../../../ip_cores/vme64x-core" ],
}
"local" : [
"../mt_template",
],
}
hdl/top/svec/mt_template/Manifest.py
View file @ 973d755c
files = [ "svec_mt_pkg.vhd",
"svec_mt_template.vhd",
"bicolor_led_ctrl.vhd",
"bicolor_led_ctrl_pkg.vhd" ];
files = [
"svec_mt_pkg.vhd",
"svec_mt_template.vhd",
"bicolor_led_ctrl.vhd",
"bicolor_led_ctrl_pkg.vhd",
]
modules = {
"local" : [
"../../../rtl",
],
}
hdl/top/svec/mt_template/svec_mt_pkg.vhd
View file @ 973d755c
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2017-04-24
-- Last update: 2018-03-08
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -43,15 +43,15 @@ library work;
use work.wishbone_pkg.all;
use work.mock_turtle_pkg.all;
use work.mt_mqueue_pkg.all;
use work.xvme64x_core_pkg.all;
use work.vme64x_pkg.all;
package svec_mt_pkg is
constant c_unused_wisbone_slave_out : t_wishbone_slave_out :=
('1', '0', '0', '0', '0', x"deadbeef");
constant c_unused_fmc0_record : t_sdb_record := f_sdb_embed_device(cc_dummy_sdb_device, x"00010000");
constant c_unused_fmc1_record : t_sdb_record := f_sdb_embed_device(cc_dummy_sdb_device, x"00018000");
constant c_unused_fmc0_record : t_sdb_record := f_sdb_embed_device(cc_dummy_sdb_device, x"00001000");
constant c_unused_fmc1_record : t_sdb_record := f_sdb_embed_device(cc_dummy_sdb_device, x"00004000");
component svec_mt_template is
......
hdl/top/svec/mt_template/svec_mt_template.vhd
View file @ 973d755c
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2017-04-26
-- Last update: 2018-03-08
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -49,7 +49,7 @@ use ieee.numeric_std.all;
use work.svec_mt_pkg.all;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
use work.xvme64x_core_pkg.all;
use work.vme64x_pkg.all;
use work.mock_turtle_pkg.all;
use work.gencores_pkg.all;
use work.wrcore_pkg.all;
......@@ -688,7 +688,7 @@ begin
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_softpll_enable_debugger => false,
g_dpram_initf => "wrc.bram")
g_dpram_initf => "../../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram")
port map (
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd,
......@@ -1048,12 +1048,10 @@ begin
fp_gpio1_a2b_o <= mt_gpio_out(24);
fp_gpio2_a2b_o <= mt_gpio_out(25);
fp_gpio34_a2b_o <= mt_gpio_out(26);
fp_gpio1_a2b_o <= wrn_gpio_out(24);
mt_gpio_in(0) <= fp_gpio1_b;
mt_gpio_in(1) <= fp_gpio2_b;
mt_gpio_in(2) <= fp_gpio3_b;
mt_gpio_in(3) <= fp_gpio4_b;
fp_gpio2_a2b_o <= wrn_gpio_out(25);
fp_gpio1_b <= 'Z' when mt_gpio_out(24) = '0' else mt_gpio_out(0);
fp_gpio2_b <= 'Z' when mt_gpio_out(25) = '0' else mt_gpio_out(1);
fp_gpio3_b <= 'Z' when mt_gpio_out(26) = '0' else mt_gpio_out(2);
......
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