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Mock Turtle
Commit afbd59f3 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: import of masterFIP-deployed branch from legacy wr-node-core repository. 

Import of commit 96a7859 from git://ohwr.org/white-rabbit/wr-node-core.git.

This is the commit used by currently deployed masterFIP, a "known-to-work" version of Mock Turtle.

Things not working (to be fixed in subsequent commit):
  * Demo projects for SPEC and SVEC
  * Testbenches
  * Documentation
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.gitignore
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*.so *.bit
*.a
*.mod.c
*.o
*.ko
*.o.cmd
*~
\#*\#
.*
*TAGS
Module.symvers
modules.order
Makefile.specific
*.S
*.bin *.bin
*.ngc
*~
#*
*.ini
*.log
work
*.vstf
*.wlf
*.version
*.cfg
*.bk
*#
*.bak
run.tcl
.emacs*
.#*
transcript
*.par
*.pcf
*.pad
*.ngr
*.ncd
*.gise
*.ptwx
*.twx
*.unroutes
*.ut
*.xpi
*.bgn
*.bld
*.cmd_log
*.drc
*.lso
*.ngd
*.prj
*.stx
*.syr
*.twr
*.xst
*_bitgen.xwbt
*_envsettings.html
*_map.map
*_map.mrp
*_map.ngm
*_map.xrpt
*_ngdbuild.xrpt
*_pad.csv
*_pad.txt
*_par.xrpt
*.html
*.xml
*_usage.xml
*_xst.xrpt
xlnx_auto_0_xdb
iseconfig
_ngo
_xmsgs
*.o
*.pdf
*.aux
*.out
*.psr
*.xdl
*.orig
*.ram
pa.fromNcd.tcl
pa.fromNetlist.tcl
planAhead_run_*
*.vcd
*.wlf
work/
*.elf *.elf
*.gdb .Xil
GPATH xst/
\ No newline at end of file *stacktrace*
rtl/*.h
scp.sh
disasm.S
\ No newline at end of file
.gitmodules
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[submodule "fmc-bus"] [submodule "fmc-bus"]
path = software/fmc-bus path = software/fmc-bus
url = git://ohwr.org/fmc-projects/fmc-bus.git url = git://ohwr.org/fmc-projects/fmc-bus.git
[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
[submodule "hdl/ip_cores/etherbone-core"]
path = hdl/ip_cores/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git
[submodule "hdl/ip_cores/vme64x-core"]
path = hdl/ip_cores/vme64x-core
url = git://ohwr.org/hdl-core-lib/vme64x-core.git
[submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
doc/technical-spec/drawings/general.eps 0 → 100644
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doc/technical-spec/drawings/host_mqueue.eps 0 → 100644
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doc/technical-spec/drawings/mq_block.eps 0 → 100644
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doc/technical-spec/drawings/mqueue_msg_way.eps 0 → 100644
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doc/technical-spec/drawings/mqueue_slot_layout.eps 0 → 100644
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doc/technical-spec/drawings/node_tech_block.eps 0 → 100644
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doc/technical-spec/drawings/remote_mqueue.eps 0 → 100644
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doc/technical-spec/node-tech.tex 0 → 100644
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etherbone-core @ 23903f61
Subproject commit 23903f6123b24b96895d4c04a6fcb237b14fb55f
general-cores @ 8cd05d79
Subproject commit 8cd05d796abf0e494a367c15ce4fde1535751efe
gn4124-core @ e3a0bf97
Subproject commit e3a0bf97e125020c83bff6e40199a717e7fda738
vme64x-core @ aa37242a
Subproject commit aa37242a6ef7a317360fe730cf349d1cdf02ac9a
wr-cores @ 573ac5a9
Subproject commit 573ac5a938e53c6bedaee13b75e1c0c6c6e311db
hdl/rtl/Manifest.py 0 → 100644
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modules = {
"local" : [ "wrnc" ] }
hdl/rtl/wrnc/Manifest.py 0 → 100644
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files = [ "wr_node_core.vhd",
"wr_node_pkg.vhd",
"wr_node_core_with_etherbone.vhd",
"wb_remapper.vhd" ]
modules = {
"local" : [ "cpu", "mqueue", "smem" ] }
hdl/rtl/wrnc/cpu/Manifest.py 0 → 100644
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files = ["wrn_cpu_cb.vhd",
"wrn_cpu_csr_wbgen2_pkg.vhd",
"wrn_cpu_csr_wb.vhd",
"wrn_cpu_iram.vhd",
"wrn_cpu_lr_wbgen2_pkg.vhd",
"wrn_cpu_lr_wb.vhd",
"wrn_lm32_wrapper.vhd",
"wrn_private_pkg.vhd"];
hdl/rtl/wrnc/cpu/build_wb.sh 0 → 100755
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#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/wrn_cpu_csr.html -V wrn_cpu_csr_wb.vhd -p wrn_cpu_csr_wbgen2_pkg.vhd --cstyle defines -C wrn_cpu_csr.h --hstyle record --lang vhdl -K wrn_cpu_csr_regs.vh wrn_cpu_csr.wb
wbgen2 -D ./doc/wrn_cpu_lr.html -V wrn_cpu_lr_wb.vhd -p wrn_cpu_lr_wbgen2_pkg.vhd --cstyle defines -C wrn_cpu_lr.h --hstyle record --lang vhdl wrn_cpu_lr.wb
hdl/rtl/wrnc/cpu/wrn_cpu_cb.vhd 0 → 100644
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hdl/rtl/wrnc/cpu/wrn_cpu_csr.wb 0 → 100644
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-- -*- Mode: LUA; tab-width: 2 -*-
-------------------------------------------------------------------------------
-- Title : White Rabbit Node Core
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : wrn_cpu_csr.wb
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2014-11-26
-------------------------------------------------------------------------------
-- Description:
--
-- CPU Control/Status Registers block layout (wbgen2)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
peripheral {
name = "WR Node CPU Control/Status registers block";
prefix = "wrn_cpu_csr";
hdl_entity = "wrn_cpu_csr_wb_slave";
reg {
name = "Application ID Register";
prefix = "APP_ID";
field {
name = "User application ID";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CPU Reset Register";
prefix = "RESET";
field {
name = "CPU reset lines";
size = 8;
type = SLV;
reset_value = 0xff;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "CPU Enable Register";
prefix = "ENABLE";
field {
name = "CPU enable lines";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "CPU Upload Address Register";
prefix = "UADDR";
field {
name = "Address";
prefix = "ADDR";
size = 20;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Core Select Register";
prefix = "CORE_SEL";
field {
name = "CPU core select";
size = 4;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Core Count Register";
prefix = "CORE_COUNT";
field {
name = "Number of CPU Cores";
size = 4;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Core Memory Size";
prefix = "CORE_MEMSIZE";
field {
name = "Memory size for the selected core.";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CPU Upload Data Register";
prefix = "UDATA";
field {
name = "CPU IRAM read/write data";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CPU Debug Register";
prefix = "DBG_JTAG";
field {
name = "JTAG data";
prefix = "jdata";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "JTAG address";
prefix = "jaddr";
align = 8;
size = 3;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "JTAG reset";
prefix = "rstn";
align = 8;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "JTAG TCK";
prefix = "tck";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "JTAG Update";
prefix = "update";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "CPU Debug Message Register";
prefix = "DBG_MSG";
field {
prefix = "DATA";
name = "Debug message byte for the selected core";
type = SLV;
size = 8;
ack_read = "dbg_msg_data_rd_ack_o";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CPU Debug Messge Poll Register";
prefix = "DBG_POLL";
field {
prefix = "READY";
name = "Debug Message data available";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CPU Debug Messge Interrupt Mask Register";
prefix = "DBG_IMSK";
field {
prefix = "ENABLE";
name = "Per-CPU Debug Message Interrupt Enable";
description = "1: IRQ enabled";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "SMEM Operation Select";
description = "Selects the operation mode for Shared Memory writes from host";
prefix = "SMEM_OP";
field {
name = "Operation code";
description = "0x0: write\
0x1: add\
0x2: subtract\
0x3: bit set\
0x3: bit clear\
0x3: bit flip";
type = SLV;
size = 3;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
hdl/rtl/wrnc/cpu/wrn_cpu_csr_regs.vh 0 → 100644
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`define ADDR_WRN_CPU_CSR_APP_ID 6'h0
`define ADDR_WRN_CPU_CSR_RESET 6'h4
`define ADDR_WRN_CPU_CSR_ENABLE 6'h8
`define ADDR_WRN_CPU_CSR_UADDR 6'hc
`define WRN_CPU_CSR_UADDR_ADDR_OFFSET 0
`define WRN_CPU_CSR_UADDR_ADDR 32'h000fffff
`define ADDR_WRN_CPU_CSR_CORE_SEL 6'h10
`define ADDR_WRN_CPU_CSR_CORE_COUNT 6'h14
`define ADDR_WRN_CPU_CSR_CORE_MEMSIZE 6'h18
`define ADDR_WRN_CPU_CSR_UDATA 6'h1c
`define ADDR_WRN_CPU_CSR_DBG_JTAG 6'h20
`define WRN_CPU_CSR_DBG_JTAG_JDATA_OFFSET 0
`define WRN_CPU_CSR_DBG_JTAG_JDATA 32'h000000ff
`define WRN_CPU_CSR_DBG_JTAG_JADDR_OFFSET 8
`define WRN_CPU_CSR_DBG_JTAG_JADDR 32'h00000700
`define WRN_CPU_CSR_DBG_JTAG_RSTN_OFFSET 16
`define WRN_CPU_CSR_DBG_JTAG_RSTN 32'h00010000
`define WRN_CPU_CSR_DBG_JTAG_TCK_OFFSET 17
`define WRN_CPU_CSR_DBG_JTAG_TCK 32'h00020000
`define WRN_CPU_CSR_DBG_JTAG_UPDATE_OFFSET 18
`define WRN_CPU_CSR_DBG_JTAG_UPDATE 32'h00040000
`define ADDR_WRN_CPU_CSR_DBG_MSG 6'h24
`define WRN_CPU_CSR_DBG_MSG_DATA_OFFSET 0
`define WRN_CPU_CSR_DBG_MSG_DATA 32'h000000ff
`define ADDR_WRN_CPU_CSR_DBG_POLL 6'h28
`define WRN_CPU_CSR_DBG_POLL_READY_OFFSET 0
`define WRN_CPU_CSR_DBG_POLL_READY 32'h000000ff
`define ADDR_WRN_CPU_CSR_DBG_IMSK 6'h2c
`define WRN_CPU_CSR_DBG_IMSK_ENABLE_OFFSET 0
`define WRN_CPU_CSR_DBG_IMSK_ENABLE 32'h000000ff
`define ADDR_WRN_CPU_CSR_SMEM_OP 6'h30
hdl/rtl/wrnc/cpu/wrn_cpu_csr_wb.vhd 0 → 100644
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hdl/rtl/wrnc/cpu/wrn_cpu_csr_wbgen2_pkg.vhd 0 → 100644
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---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for WR Node CPU Control/Status registers block
---------------------------------------------------------------------------------------
-- File : wrn_cpu_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wrn_cpu_csr.wb
-- Created : Fri Sep 18 15:20:23 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrn_cpu_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package wrn_cpu_csr_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_wrn_cpu_csr_in_registers is record
app_id_i : std_logic_vector(31 downto 0);
core_count_i : std_logic_vector(3 downto 0);
core_memsize_i : std_logic_vector(31 downto 0);
udata_i : std_logic_vector(31 downto 0);
dbg_jtag_jdata_i : std_logic_vector(7 downto 0);
dbg_jtag_jaddr_i : std_logic_vector(2 downto 0);
dbg_jtag_rstn_i : std_logic;
dbg_jtag_tck_i : std_logic;
dbg_jtag_update_i : std_logic;
dbg_msg_data_i : std_logic_vector(7 downto 0);
dbg_poll_ready_i : std_logic_vector(7 downto 0);
end record;
constant c_wrn_cpu_csr_in_registers_init_value: t_wrn_cpu_csr_in_registers := (
app_id_i => (others => '0'),
core_count_i => (others => '0'),
core_memsize_i => (others => '0'),
udata_i => (others => '0'),
dbg_jtag_jdata_i => (others => '0'),
dbg_jtag_jaddr_i => (others => '0'),
dbg_jtag_rstn_i => '0',
dbg_jtag_tck_i => '0',
dbg_jtag_update_i => '0',
dbg_msg_data_i => (others => '0'),
dbg_poll_ready_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_wrn_cpu_csr_out_registers is record
reset_o : std_logic_vector(7 downto 0);
enable_o : std_logic_vector(7 downto 0);
uaddr_addr_o : std_logic_vector(19 downto 0);
core_sel_o : std_logic_vector(3 downto 0);
udata_o : std_logic_vector(31 downto 0);
udata_load_o : std_logic;
dbg_jtag_jdata_o : std_logic_vector(7 downto 0);
dbg_jtag_jdata_load_o : std_logic;
dbg_jtag_jaddr_o : std_logic_vector(2 downto 0);
dbg_jtag_jaddr_load_o : std_logic;
dbg_jtag_rstn_o : std_logic;
dbg_jtag_rstn_load_o : std_logic;
dbg_jtag_tck_o : std_logic;
dbg_jtag_tck_load_o : std_logic;
dbg_jtag_update_o : std_logic;
dbg_jtag_update_load_o : std_logic;
dbg_imsk_enable_o : std_logic_vector(7 downto 0);
smem_op_o : std_logic_vector(2 downto 0);
end record;
constant c_wrn_cpu_csr_out_registers_init_value: t_wrn_cpu_csr_out_registers := (
reset_o => (others => '0'),
enable_o => (others => '0'),
uaddr_addr_o => (others => '0'),
core_sel_o => (others => '0'),
udata_o => (others => '0'),
udata_load_o => '0',
dbg_jtag_jdata_o => (others => '0'),
dbg_jtag_jdata_load_o => '0',
dbg_jtag_jaddr_o => (others => '0'),
dbg_jtag_jaddr_load_o => '0',
dbg_jtag_rstn_o => '0',
dbg_jtag_rstn_load_o => '0',
dbg_jtag_tck_o => '0',
dbg_jtag_tck_load_o => '0',
dbg_jtag_update_o => '0',
dbg_jtag_update_load_o => '0',
dbg_imsk_enable_o => (others => '0'),
smem_op_o => (others => '0')
);
function "or" (left, right: t_wrn_cpu_csr_in_registers) return t_wrn_cpu_csr_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body wrn_cpu_csr_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_wrn_cpu_csr_in_registers) return t_wrn_cpu_csr_in_registers is
variable tmp: t_wrn_cpu_csr_in_registers;
begin
tmp.app_id_i := f_x_to_zero(left.app_id_i) or f_x_to_zero(right.app_id_i);
tmp.core_count_i := f_x_to_zero(left.core_count_i) or f_x_to_zero(right.core_count_i);
tmp.core_memsize_i := f_x_to_zero(left.core_memsize_i) or f_x_to_zero(right.core_memsize_i);
tmp.udata_i := f_x_to_zero(left.udata_i) or f_x_to_zero(right.udata_i);
tmp.dbg_jtag_jdata_i := f_x_to_zero(left.dbg_jtag_jdata_i) or f_x_to_zero(right.dbg_jtag_jdata_i);
tmp.dbg_jtag_jaddr_i := f_x_to_zero(left.dbg_jtag_jaddr_i) or f_x_to_zero(right.dbg_jtag_jaddr_i);
tmp.dbg_jtag_rstn_i := f_x_to_zero(left.dbg_jtag_rstn_i) or f_x_to_zero(right.dbg_jtag_rstn_i);
tmp.dbg_jtag_tck_i := f_x_to_zero(left.dbg_jtag_tck_i) or f_x_to_zero(right.dbg_jtag_tck_i);
tmp.dbg_jtag_update_i := f_x_to_zero(left.dbg_jtag_update_i) or f_x_to_zero(right.dbg_jtag_update_i);
tmp.dbg_msg_data_i := f_x_to_zero(left.dbg_msg_data_i) or f_x_to_zero(right.dbg_msg_data_i);
tmp.dbg_poll_ready_i := f_x_to_zero(left.dbg_poll_ready_i) or f_x_to_zero(right.dbg_poll_ready_i);
return tmp;
end function;
end package body;
hdl/rtl/wrnc/cpu/wrn_cpu_iram.vhd 0 → 100644
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-------------------------------------------------------------------------------
-- Title : White Rabbit Node Core
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : wrn_cpu_iram.vhd
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2014-12-01
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
--
-- WR Node CPU Internal RAM block. To be replaced with direct cache execution.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
use work.genram_pkg.all;
entity wrn_cpu_iram is
generic (
g_size : integer);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(31 downto 0);
db_i : in std_logic_vector(31 downto 0);
qa_o : out std_logic_vector(31 downto 0);
qb_o : out std_logic_vector(31 downto 0);
ena_i : in std_logic;
enb_i : in std_logic;
wea_i : in std_logic;
web_i : in std_logic
);
end wrn_cpu_iram;
architecture rtl of wrn_cpu_iram is
type t_ram_type is array(0 to g_size - 1) of std_logic_vector(31 downto 0);
function f_empty_ram_array return t_ram_type is
variable rv : t_ram_type;
begin
for i in 0 to g_size-1 loop
rv(i) := (others => '0');
end loop; -- i
return rv;
end function;
shared variable iram : t_ram_type := f_empty_ram_array;
begin -- rtl
process(clk_i)
begin
if rising_edge(clk_i) then
if(ena_i = '1') then
if(wea_i = '1') then
iram(to_integer(unsigned(aa_i))) := da_i;
end if;
qa_o <= iram(to_integer(unsigned(aa_i)));
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if(enb_i = '1') then
if(web_i = '1') then
iram(to_integer(unsigned(ab_i))) := db_i;
end if;
qb_o <= iram(to_integer(unsigned(ab_i)));
end if;
end if;
end process;
end rtl;
hdl/rtl/wrnc/cpu/wrn_cpu_lr.wb 0 → 100644
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-------------------------------------------------------------------------------
-- Title : White Rabbit Node Core
-- Project : White Rabbit
-------------------------------------------------------------------------------
-- File : wrn_cpu_lr.wb
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2014-04-01
-- Last update: 2014-11-26
-------------------------------------------------------------------------------
-- Description:
--
-- CPU Local Registers block layout (wbgen2)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "WR Node CPU Local Registers";
prefix = "wrn_cpu_lr";
hdl_entity = "wrn_cpu_lr_wb_slave";
reg {
name = "CPU Polling Register";
prefix = "POLL";
field {
name = "HMQ Slot Status";
prefix = "HMQ";
size = 16;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RMQ Slot Status";
prefix = "RMQ";
size = 16;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CPU Status Register";
prefix = "STAT";
field {
name = "WR Link Up";
prefix = "WR_LINK";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "WR Time OK";
prefix = "WR_TIME_OK";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "WR Aux Clock OK";
prefix = "WR_AUX_CLOCK_OK";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Core ID";
prefix = "CORE_ID";
description = "ID (number) of the CPU core owning this register.";
type = SLV;
align = 28;
size = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "TAI Cycles";
prefix = "TAI_CYCLES";
field {
name = "TAI Cycles";
size = 28;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "TAI Seconds";
prefix = "TAI_SEC";
field {
name = "TAI Seconds";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
ack_read = "tai_sec_rd_ack_o";
};
};
reg {
name = "GPIO Input";
prefix = "GPIO_IN";
field {
name = "GPIO In";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "GPIO Set";
prefix = "GPIO_SET";
field {
name = "GPIO Set";
size = 32;
type = PASS_THROUGH;
};
};
reg {
name = "GPIO Clear";
prefix = "GPIO_CLEAR";
field {
name = "GPIO Clear";
size = 32;
type = PASS_THROUGH;
};
};
reg {
name = "Debug Message Output";
prefix = "DBG_CHR";
field {
name = "Debug Message Character";
size = 8;
type = PASS_THROUGH;
};
};
reg {
name = "Delay Counter Register";
prefix = "DELAY_CNT";
description = "Counts down at every system clock cycle and stops at 0. Used for generating delays";
field {
name = "Delay";
size = 32;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Application ID";
prefix = "APP_ID";
field {
name = "APP_ID";
-- prefix = "APP_ID";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
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files = [ "wrn_mqueue_host.vhd",
"wrn_mqueue_remote.vhd",
"wrn_mqueue_etherbone_output.vhd",
"wrn_mqueue_irq_unit.vhd",
"wrn_mqueue_pkg.vhd",
"wrn_mqueue_slot.vhd",
"wrn_eb_cycle_gen.vhd",
"wrn_mqueue_wishbone_slave.vhd" ];
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files = ["wrn_shared_mem.vhd"]
\ No newline at end of file
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OBJS = debug-test.o
OUTPUT = debug-test
include ../common/wrnode.mk
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action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
vlog_opt="+incdir+../../include/wb +incdir+../../include/vme64x_bfm +incdir+../../include"
vcom_opt="-mixedsvvh l"
files = [ "main.sv" ]
modules = { "local" : [ "../../rtl" ] }
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