mt_urv_wrapper: update after changes in urv.

e140c291 · Tristan Gingold · 1df956cb · e140c291
Commit e140c291 authored Jan 31, 2019 by Tristan Gingold
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Showing with 11 additions and 15 deletions

mt_urv_wrapper.vhd hdl/rtl/cpu/mt_urv_wrapper.vhd +11 -15

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--- a/hdl/rtl/cpu/mt_urv_wrapper.vhd
+++ b/hdl/rtl/cpu/mt_urv_wrapper.vhd
@@ -58,7 +58,7 @@ architecture arch of mt_urv_wrapper is
      if( x(i) = 'U' or x(i) = 'Z' or x(i) = 'X' ) then
        found_undef := true;
      end if;
-      
+
      if x(i) = '1' or x(i) = 'H' then
        tmp(i) := '1';
      else
@@ -70,7 +70,7 @@ architecture arch of mt_urv_wrapper is
    if found_undef then
      report "Undefined data value read from memory" severity warning;
    end if;
-    
+
 -- synthesis translate_on
    return x;
  end function f_x_to_zero;
@@ -98,9 +98,9 @@ architecture arch of mt_urv_wrapper is

  signal im_addr_muxed : std_logic_vector(31 downto 0);

-  signal dm_addr, dm_data_s, dm_data_l                            : std_logic_vector(31 downto 0);
-  signal dm_data_select                                           : std_logic_vector(3 downto 0);
-  signal dm_load, dm_store, dm_load_done, dm_store_done, dm_ready : std_logic;
+  signal dm_addr, dm_data_s, dm_data_l                  : std_logic_vector(31 downto 0);
+  signal dm_data_select                                 : std_logic_vector(3 downto 0);
+  signal dm_load, dm_store, dm_load_done, dm_store_done : std_logic;

  signal dm_cycle_in_progress, dm_is_wishbone : std_logic;

@@ -134,7 +134,6 @@ begin
      dm_data_s_o      => dm_data_s,
      dm_data_l_i      => dm_data_l,
      dm_data_select_o => dm_data_select,
-      dm_ready_i       => dm_ready,
      dm_store_o       => dm_store,
      dm_load_o        => dm_load,
      dm_load_done_i   => dm_load_done,
@@ -148,6 +147,9 @@ begin
      dbg_mbx_write_i  => cpu_csr_i.dbg_mbx_wr_o,
      dbg_mbx_data_o   => cpu_csr_o.dbg_mbx_i);

+  -- 1st MByte of the mem is the IRAM
+  dm_is_wishbone <= '1' when dm_addr(31 downto 20) /= x"000" else '0';
+
  dm_data_write <= not dm_is_wishbone and dm_store;

  U_iram : generic_dpram
@@ -199,9 +201,6 @@ begin
    end if;
  end process p_iram_host_access;

-  -- 1st MByte of the mem is the IRAM
-  dm_is_wishbone <= '1' when dm_addr(31 downto 20) /= x"000" else '0';
-
  -- Wishbone bus arbitration / internal RAM access
  p_wishbone_master : process(clk_sys_i)
  begin
@@ -218,21 +217,19 @@ begin
        dm_store_done        <= '0';
        dm_select_wb         <= '0';
      else
-
-        if dm_cycle_in_progress = '0' then  -- access to internal memory
+        if dm_cycle_in_progress = '0' then
          if dm_is_wishbone = '0' then
+            -- access to internal memory
+            dm_select_wb  <= '0';
            if dm_store = '1' then
              dm_load_done  <= '0';
              dm_store_done <= '1';
-              dm_select_wb  <= '0';
            elsif dm_load = '1' then
              dm_load_done  <= '1';
              dm_store_done <= '0';
-              dm_select_wb  <= '0';
            else
              dm_store_done <= '0';
              dm_load_done  <= '0';
-              dm_select_wb  <= '0';
            end if;
          else
            if dm_load = '1' or dm_store = '1' then
@@ -281,7 +278,6 @@ begin
  dm_data_write <= not dm_is_wishbone and dm_store;
  dm_data_l     <= dm_wb_rdata when dm_select_wb = '1' else dm_mem_rdata;
  im_addr_muxed <= ha_im_addr  when cpu_rst = '1'      else im_addr;
-  dm_ready      <= '1';

  p_dbg_insn : process(clk_sys_i)
  begin